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M16C/64A Group
24.5
Notes on Serial Interface SI/O3 and SI/O4
24.5.1
SOUTi Pin Level When SOUTi Output Is Disabled
When the SMi2 bit in the SiC register is set to 1 (SOUTi output disabled), the target pin becomes high-
impedance regardless of which pin function being used.
24.5.2
External Clock Control
The data written to the SiTRR register shifts each time the external clock is input. When completing
data transmission/reception of the eighth bit, read or write to the SiTRR register before inputting the
clock for the next data transmission/reception.
24.5.3
Register Access When Using the External Clock
When the SMi6 bit in the SiC register is 0 (external clock), write to the SMi7 bit in the SiC register and
SiTRR register under the following conditions:
•
When the SMi4 bit in the SiC register is 0 (transmit data is output at the falling edge of
transmit/receive clock and receive data is input at the rising edge): CLKi input is high.
•
When the SMi4 bit in the SiC register is 1 (transmit data is output at the rising edge of
transmit/receive clock and receive data is input at the falling edge): CLKi input is low.
24.5.4
SiTRR Register Access
Write transmit data to the SiTRR register while transmission/reception is stopped. Read receive data
from the SiTRR register while transmission/reception is stopped.
The IR bit in the SiIC register becomes 1 (interrupt requested) during output of the eighth bit.
When the SM26 bit (SOUT3) or SM27 bit (SOUT4) in the S34C2 register is 0 (high-impedance after
transmission), the SOUTi pin becomes high-impedance when the transmit data is written to the SiTRR
register immediately after an interrupt request is generated, and the hold time of the transmit data
becomes shorter.
24.5.5
Pin Function Switch When Using the Internal Clock
(Technical update number: TN-16C-121A/EA)
If the SMi3 bit in the SiC register (i = 3, 4) changes from 0 (I/O port) to 1 (SOUTi output, CLKi function)
when setting the SMi2 bit to 0 (SOUTi output) and the SMi6 bit to 1 (internal clock), the SOUTi initial
value set to the SOUTi pin by the SMi7 bit may be output for about 10 ns. Then, the SOUTi pin
becomes high-impedance.
If the output level from the SOUTi pin when the SMi3 bit changes from 0 to 1 becomes a problem, set
the SOUTi initial value by the SMi7 bit.
24.5.6
Operation after Reset When Selecting the External Clock
When the SMi6 bit in the SiC register is 0 (external clock) after reset, the IR bit in the SiIC register
becomes 1 (interrupt requested) by inputting an external clock for 8 bits to the CLKi pin. This will also
occur even when the SMi3 bit in the SiC register is 0 (serial interface disabled) or before a value is
written to the SiTRR register.
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
24. Serial Interface SI/O3 and SI/O4
Page 531 of 800
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