Renesas R5F364AENFB#V2 Manuals

Manuals and User Guides for Renesas R5F364AENFB#V2. We have 1 Renesas R5F364AENFB#V2 manual available for free PDF download: User Manual

Renesas R5F364AENFB#V2 User Manual

Renesas R5F364AENFB#V2 User Manual (853 pages)

Brand: Renesas | Category: Microcontrollers | Size: 10.91 MB

Table of Contents

Table of Contents
8
Quick Reference

27
1 Overview

34
- Features
  34
  - Applications
    34
- Specifications
  35
- Product List
  37
- Block Diagram
  39
- Pin Assignments
  40
- Pin Functions
  44
2 Central Processing Unit (CPU)

47
3 Address Space

50
- Memory Map
  51
- Accessible Area in each Mode
  52
4 Special Function Registers (Sfrs)

53
- Sfrs
  53
- Notes on Sfrs
  71
  - Register Settings
    71
5 Protection

73
- Introduction
  73
- Register
  73
  - Protect Register (PRCR)
    73
- Notes on Protection
  75
6 Resets

76
- Introduction
  76
- Registers
  78
  - Processor Mode Register 0 (PM0)
    79
  - Reset Source Determine Register (RSTFR)
    80
- Optional Function Select Area
  81
  - Optional Function Select Address 1 (OFS1)
    81
- Operations
  83
  - Status after Reset
    83
  - Hardware Reset
    86
  - Power-On Reset Function
    87
  - Voltage Monitor 0 Reset
    88
  - Voltage Monitor 1 Reset
    88
  - Voltage Monitor 2 Reset
    88
  - Oscillator Stop Detect Reset
    89
  - Watchdog Timer Reset
    89
  - Software Reset
    89
  - Cold/Warm Start Discrimination
    90
- Notes on Resets
  91
7 Voltage Detector

93
- Introduction
  93
- Registers
  95
- Optional Function Select Area
  105
  - Optional Function Select Address 1 (OFS1)
    105
- Operations
  106
  - Digital Filter
    106
  - Voltage Detector 0
    107
  - Voltage Detector 1
    109
  - Voltage Detector 2
    112
- Interrupts
  115
8 Clock Generator

116
- Introduction
  116
- Registers
  118
- Clocks Generated by Clock Generators
  129
  - Main Clock
    129
  - PLL Clock
    130
  - 125 Khz On-Chip Oscillator Clock (Foco-S)
    130
  - Sub Clock (Fc)
    131
- CPU Clock and Peripheral Function Clocks
  132
  - CPU Clock and BCLK
    132
  - Peripheral Function Clocks (F1, Foco-S, Fc32, Fc)
    132
- Clock Output Function
  134
- System Clock Protection Function
  134
- Oscillator Stop/Restart Detect Function
  135
- Interrupt
  137
- Notes on Clock Generator
  138
  - Oscillator Using a Crystal or a Ceramic Resonator
    138
  - Noise Countermeasure
    139
  - CPU Clock
    140
  - Oscillator Stop/Restart Detect Function
    140
  - PLL Frequency Synthesizer
    141
  - Starting PLL Clock Oscillation
    142
9 Power Control

143
- Introduction
  143
- Registers
  143
  - Flash Memory Control Register 0 (FMR0)
    144
  - Flash Memory Control Register 2 (FMR2)
    145
- Clock
  147
  - Normal Operating Mode
    147
  - CPU Clock
    149
  - Clock Mode Transition Procedure
    151
  - Wait Mode
    154
  - Stop Mode
    156
- Power Control in Flash Memory
  158
  - Stopping Flash Memory
    158
  - Reading Flash Memory
    159
  - Low Current Consumption Read Mode
    160
- Reducing Power Consumption
  161
  - Ports
    161
  - A/D Converter
    161
  - D/A Converter
    161
  - Stopping Peripheral Functions
    161
  - Switching the Oscillation-Driving Capacity
    161
- Notes on Power Control
  162
  - CPU Clock
    162
  - Wait Mode
    162
  - Stop Mode
    162
  - Low Current Consumption Read Mode
    163
  - Slow Read Mode
    163
10 Processor Mode

164
- Introduction
  164
- Registers
  165
- Operations
  169
  - Processor Mode Settings
    169
11 Bus

171
- Introduction
  171
- Registers
  171
  - Chip Select Control Register (CSR)
    172
  - Chip Select Expansion Control Register (CSE)
    173
- Operations
  174
  - Common Specifications between the Internal Bus and External Bus
    174
  - Internal Bus
    175
  - External Bus
    176
  - External Bus Mode
    176
  - External Bus Control
    177
- Notes on Bus
  186
  - Reading Data Flash
    186
  - External Bus
    186
  - External Access Immediately after Writing to the Sfrs
    186
  - Hold
    186
12 Memory Space Expansion Function

187
- Introduction
  187
- Registers
  187
  - Data Bank Register (DBR)
    188
- Operations
  189
  - 1-MB Mode
    189
  - 4-MB Mode
    191
13 Programmable I/O Ports

198
- Introduction
  198
- I/O Ports and Pins
  199
- Registers
  211
- Peripheral Function I/O
  219
  - Peripheral Function I/O and Port Direction Bits
    219
  - Priority Level of Peripheral Function I/O
    219
  - NMI/SD Digital Filter
    220
  - CNVSS Pin
    220
- Unassigned Pin Handling
  221
- Notes on Programmable I/O Ports
  223
  - Influence of SD
    223
  - Influence of SI/O3 and SI/O4
    223
14 Interrupts

224
- Introduction
  224
- Registers
  225
- Types of Interrupts
  237
- Software Interrupts
  238
  - Undefined Instruction Interrupt
    238
  - Overflow Interrupt
    238
  - BRK Interrupt
    238
  - INT Instruction Interrupt
    238
- Hardware Interrupts
  239
  - Special Interrupts
    239
  - Peripheral Function Interrupts
    239
- Interrupts and Interrupt Vectors
  240
  - Fixed Vector Tables
    240
  - Relocatable Vector Tables
    241
- Interrupt Control
  243
  - Maskable Interrupt Control
    243
  - Interrupt Sequence
    244
  - Interrupt Response Time
    245
  - Variation of IPL When Interrupt Request Is Accepted
    245
  - Saving Registers
    246
  - Returning from an Interrupt Routine
    247
  - Interrupt Priority
    247
  - Interrupt Priority Level Select Circuit
    247
  - Multiple Interrupts
    249
- INT Interrupt
  249
- NMI Interrupt
  250
- 14.10 Key Input Interrupt
  250
- 14.11 Address Match Interrupt
  251
- 14.12 Non-Maskable Interrupt Source Discrimination
  252
- 14.13 Notes on Interrupts
  253
15 Watchdog Timer

257
- Introduction
  257
- Registers
  258
- Optional Function Select Area
  262
  - Optional Function Select Address 1 (OFS1)
    262
- Operations
  263
  - Count Source Protection Mode Disabled
    263
  - Count Source Protection Mode Enabled
    264
- Interrupts
  265
- Notes on the Watchdog Timer
  266
16 Dmac

267
- Introduction
  267
- Registers
  269
- Operations
  276
  - DMA Enabled
    276
  - DMA Request
    276
  - Transfer Cycles
    277
  - DMAC Transfer Cycles
    279
  - Single Transfer Mode
    280
  - Repeat Transfer Mode
    281
  - Channel Priority and DMA Transfer Timing
    282
- Interrupts
  283
- Notes on DMAC
  284
  - Write to the DMAE Bit in the Dmicon Register (I = 0 to 3)
    284
  - Changing the DMA Request Source
    284
17 Timer a

285
- Introduction
  285
- Registers
  288
- Operations
  300
- Interrupts
  328
- Notes on Timer a
  329
  - Common Notes on Multiple Modes
    329
  - Timer a (Timer Mode)
    330
  - Timer a (Event Counter Mode)
    330
  - Timer a (One-Shot Timer Mode)
    330
  - Timer a (Pulse Width Modulation Mode)
    331
  - Timer a (Programmable Output Mode)
    332
18 Timer B

333
- Introduction
  333
- Registers
  336
- Operations
  344
  - Common Operations
    344
  - Timer Mode
    346
  - Event Counter Mode
    348
  - Pulse Period/Pulse Width Measurement Modes
    351
- Interrupts
  356
- Notes on Timer B
  357
19 Three-Phase Motor Control Timer Function

359
- Introduction
  359
- Registers
  363
- Operations
  374
- Interrupts
  397
  - Timer B2 Interrupt
    397
  - Timer A1, A2, and A4 Interrupts
    397
- Notes on Three-Phase Motor Control Timer Function
  398
  - Timer a and Timer B
    398
  - Influence of SD
    398
20 Real-Time Clock

399
21 Pulse Width Modulator

426
- Introduction
  426
- Registers
  427
- Operations
  431
  - Setting Procedure
    431
  - Operation Example
    431
22 Remote Control Signal Receiver

433
23 Serial Interface Uarti (I = 0 to 2, 5 to 7)

481
24 Serial Interface SI/O3 and SI/O4

551
- Introduction
  551
- Registers
  553
- Operations
  557
  - Basic Operations
    557
  - CLK Polarity Selection
    557
  - LSB First or MSB First Selection
    558
  - Internal Clock
    559
  - Function for Selecting Souti State after Transmission
    560
  - External Clock
    561
  - Souti Pin
    561
  - Function for Setting Souti Initial Value
    562
- Interrupt
  563
- Notes on Serial Interface SI/O3 and SI/O4
  564
- Introduction
  565
25 Multi-Master I C-Bus Interface

566
- Registers Descriptions
  568
- Notes on Multi-Master I C-Bus Interface
  612
- Limitation on CPU Clock
  612
- Register Access
  612
- Low/High-Level Input Voltage and Low-Level Output Voltage
  612
- Generating Stop Condition
  613
- Notes on CEC
  648
- Registers and Bit Operation
  648
- VIH of the CEC Pin
  648
- Notes on A/D Converter
  678
- Analog Input Voltage
  678
- Analog Input Pin
  678
- Pin Configuration
  678
- Register Access
  678
- A/D Conversion Start
  678
- A/D Operation Mode Change
  678
- State When Forcibly Terminated
  679
- A/D Open-Circuit Detection Assist Function
  679
- Detecting Completion of A/D Conversion
  679
- Notes on D/A Converter
  684
- When Not Using the D/A Converter
  684
- 30.11 Notes on Flash Memory
  729
- 30.11.1 OFS1 Address and ID Code Storage Address
  729
- 30.11.2 Reading Data Flash
  729
- 30.11.3 CPU Rewrite Mode
  730
- 30.11.4 User Boot
  732
- 30.11.5 EW1 Mode
  732

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