Block Diagram - Renesas M16C/64A Series User Manual

M16C/64A Group
1.4

Block Diagram

Figure 1.3 shows block diagram.
8
Port P0
Internal peripheral functions
Timer (16 bit)
Outputs (timer A): 5
Inputs (timer B): 6
Three-phase motor control
Real-time clock
PWM function (8 bit x 2)
Remote control signal
receiver (2 circuits)
Watchdog timer
(15 bit)
A/D converter
(10-bit resolution x 26
channels)
D/A converter
(8-bit resolution x 2
circuits)
Port P10
8
Notes:
1. ROM size depends on MCU type.
2. RAM size depends on MCU type.
Figure 1.3 Block Diagram for the 100-Pin Package
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
8 8
Port P1 Port P2
VCC2 ports
clock synchronous serial I/O
Clock synchronous serial I/O
Multi-master I
circuit
M16C/60 Series CPU core
VCC1 ports
Port P9 Port P8
8 8
8 8
Port P3 Port P4
UART or
(6 channels)
(8 bit x 2 channels)
2
C-bus interface
(1 channel)
CEC function
R0H R0L
R1H R1L
R2
R3
INTB
A0
PC
A1
FB
Port P7 Port P6
8
8
Port P5
System clock generator
XIN-XOUT
XCIN-XCOUT
PLL frequency synthesizer
On-chip oscillator (125 kHz)
DMAC (4 channels)
CRC calculator
(CRC-CCITT or CRC-16)
Voltage detector
Power-on reset
On-chip debugger
Memory
ROM
SB
USP
ISP
RAM
FLG Multiplier
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