Renesas M16C/64A Series User Manual page 796

M16C/64A Group
32.9 Notes on Interrupts
32.9.1 Reading Address 00000h
Do not read address 00000h by a program. When a maskable interrupt request is accepted, the CPU
reads interrupt information (interrupt number and interrupt request priority level) from address 00000h
during the interrupt sequence. At this time, the IR bit of the accepted interrupt is cleared to 0 (interrupt
not requested).
If address 00000h is read by a program, the IR bit for the interrupt which has the highest priority among
the enabled interrupts becomes 0. This may cause problems such as interrupts being canceled or an
unexpected interrupt request being generated.
32.9.2 SP Setting
Set a value in the SP (USP, ISP) before accepting an interrupt. The SP (USP, ISP) is set to 0000h after
reset. Therefore, if an interrupt is accepted before setting a value in the SP (USP, ISP), the program
may go out of control.
Set a value in the ISP at the beginning of the program. For the first instruction after reset only, all
interrupts are disabled.
NMI Interrupt
32.9.3
When not using the NMI interrupt, set the PM24 bit in the PM2 register to 0 ( NMI interrupt dis-
•
abled).
The NMI interrupt is disabled after reset. The NMI interrupt is enabled by setting the PM24 bit in the
•
PM2 register to 1. Set the PM24 bit to 1 when a high-level signal is applied to the NMI pin. When
the PM24 bit is set to 1 while a low-level signal is applied, an NMI interrupt is generated. Once the
NMI interrupt is enabled, it cannot be disabled until the MCU is reset.
The MCU cannot enter stop mode while the PM24 bit is 1 ( NMI interrupt enabled) and input on the
•
NMI pin is low. When input on the NMI pin is low, the CM10 bit in the CM1 register is fixed to 0.
Do not enter wait mode while the PM24 bit is 1 ( NMI interrupt enabled) and a low signal is input to
•
the NMI pin. When the NMI pin is driven low, the CPU clock remains active even though the CPU
stops, and therefore, the current consumption of the chip does not drop. In this case, the normal
condition is restored by the next interrupt generation.
Set the low- and high-level durations of the input signal to the NMI pin to 2 CPU clock cycles + 300
•
ns or more.
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
32. Usage Notes
Page 763 of 800