Renesas M16C/64A Series User Manual page 472

M16C/64A Group
PMCi internal input signal
EN bit
Counter operation
Counter value
Bits TYP1 to TYP0 are 00b (period measurement (between rising edge and rising edge)
Bits TYP1 to TYP0 are 01b (period measurement between falling edge and falling edge)
Bits TYP1 to TYP0 are 10b (pulse width measurement)
i = 0, 1
EN: Bit in the PMCiCON0 register
TYP1 to TYP0: Bits in the PMCiCON1 register
CEFLG: Bit in the PMCiCON2 register
IR: Bit in the PMCiIC register
The above diagram shows an instance in which the following condition is met:
The TIMINT bit in the PMCiINT register is 1 (timer measure interrupt enabled)
The CEINT bit in the PMCiCON2 register is 0 (counter overflow interrupt enabled)
Figure 22.9 Operations in Input Capture Mode
22.3.4.1 Count Operation
In input capture mode, the counter counts from 0000h to FFFFh, and then returns to 0000h to
continue counting.
When the counter becomes 0000h after FFFFh, the CEFLG bit in the PMCiCON2 register becomes 1
(counter overflow) and stays 1 until the next measurement timing.
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
Count started
PMCiTIM register
IR bit
CEFLG bit
PMCiTIM register
IR bit
CEFLG bit
PMCiTIM register
IR bit
CEFLG bit
a b c d
b
The bit becomes 0 when an
interrupt request is accepted, or
by setting the bit to 0.
a c
a b c d
22. Remote Control Signal Receiver
FFFFh
e f
d
e
The bit becomes 0 when an
interrupt request is accepted, or
by setting the bit to 0.
e
The bit becomes 0 when an
interrupt request is accepted, or
by setting the bit to 0.
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