Renesas M16C/64A Series User Manual page 649

M16C/64A Group
27. A/D Converter
27.1 Introduction
The A/D converter consists of one 10-bit successive approximation A/D converter.
Table 27.1 lists the A/D Converter Specifications and Figure 27.1 shows an A/D Converter Block Diagram.
Table 27.1 A/D Converter Specifications
Item
A/D conversion
method
Analog input voltage
Operating clock φ AD
Resolution
Integral nonlinearity
error
Operation modes
Analog input pins
A/D conversion start
conditions
Conversion rate per
pin
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
Successive approximation
0 V to AVCC (VCC1)
f1, f1 divided by 2, f1 divided by 3, f1 divided by 4, f1 divided by 6, or f1 divided by
12
10 bits
AVCC = VREF = 5 V
AN0 to AN7, AN0_0 to AN0_7, or AN2_0 to AN2_7 input: ±3 LSB
ANEX0 or ANEX1 input: ±3 LSB
AVCC = VREF = 3.0 V
AN0 to AN7, AN0_0 to AN0_7, or AN2_0 to AN2_7 input: ±3 LSB
ANEX0 or ANEX1 input: ±3 LSB
One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0,
repeat sweep mode 1
8 pins (AN0 to AN7) + 2 pins (ANEX0 and ANEX1) + 8 pins (AN0_0 to AN0_7)
+ 8 pins (AN2_0 to AN2_7)
•
Software trigger
The ADST bit in the ADCON0 register is set to 1 (A/D conversion start).
•
External trigger (retrigger is enabled)
Input to the ADTRG pin changes from high to low after the ADST bit is set to 1
(A/D conversion start).
Minimum 43 φ AD cycles
Specification
27. A/D Converter
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