Renesas M16C/64A Series User Manual page 108

M16C/64A Group
7.4.2.1 Voltage Monitor 0 Reset
When using voltage monitor 0 reset, set the VDSEL1 bit in the OFS1 address to 0 (Vdet0_2).
When the LVDAS bit in the OFS1 address is 1 (voltage monitor 0 reset disabled after hardware
reset), set the related bits according to the procedure listed in Table 7.6. When the LVDAS bit in the
OFS1 address is 0 (voltage monitor 0 reset enabled after hardware reset), the procedure listed in
Table 7.6 is unnecessary.
Table 7.6 Procedure for Setting Voltage Monitor 0 Reset Related Bits
Step
1 Set the VC25 bit in the VCR2 register to 1 (voltage detector 0 enabled).
2 Wait for td(E-A).
3 Set the VW0C0 bit in the VW0C register to 1 (voltage monitor 0 reset enabled).
When voltage monitor 0 reset is generated, the CWR bit in the RSTFR register becomes 0 (cold
start). Refer to 6.4.4 "Voltage Monitor 0 Reset" for status after reset.
Figure 7.4 shows Voltage Monitor 0 Reset Operation Example.
Internal reset signal
The above diagram assumes the following:
• The VC25 bit in the VCR2 register is 1 (voltage detector 0 enabled).
• The VW0C0 bit in the VW0C register is 1 (voltage monitor 0 reset enabled).
The pins, CPU, and SFRs are initialized when the internal reset signal goes low.
The MCU executes the program at the address indicated by the reset vector when the internal reset signal
changes from low to high.
Refer to 4. "SFRs" for the SFR status after reset.
Note:
1. Make sure that VCC1 does not drop to recommended operating condition VCC1 during sampling time.
Figure 7.4 Voltage Monitor 0 Reset Operation Example
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
VCC1
Vdet0
Processing
7. Voltage Detector
1
× 32
fOCO-S
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