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Renesas V850ES/IE2 User Manual

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Page 1 On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding.
Page 2 Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as “Specific”...
Page 3 User’s Manual V850ES/IE2 32-bit Single-Chip Microcontrollers Hardware μ PD70F3713 μ PD70F3714 Document No. U17716EJ2V0UD00 (2nd edition) Date Published February 2008 N 2005 Printed in Japan...
Page 4 [MEMO] User’s Manual U17716EJ2V0UD...
Page 5 NOTES FOR CMOS DEVICES VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V (MAX) and V (MIN) due to noise, etc., the device may malfunction.
Page 6 • The information in this document is current as of January, 2008. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country.
Page 7 This manual is intended to give users an understanding of the hardware functions. Organization The V850ES/IE2 User’s Manual is divided into two parts: Hardware (this manual) and Architecture (V850ES Architecture User’s Manual). The organization of each manual is as follows:...
Page 8 Conventions Data significance: Higher digits on the left and lower digits on the right Active low representation: xxx (overscore over pin or signal name) Memory map address: Higher addresses on the top and lower addresses on the bottom Note: Footnote for item marked with Note in the text Caution: Information requiring particular attention Remark:...
Page 9 Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents related to V850ES/IE2 Document Name Document No. V850ES Architecture User’s Manual U15943E V850ES/IE2 Hardware User’s Manual This manual Documents related to development tools (user’s manuals)
Page 10: Table Of Contents
CONTENTS CHAPTER 1 INTRODUCTION......................... 14 General ............................14 Features .............................15 Applications..........................16 Ordering Information ........................16 Pin Configuration ........................17 Function Blocks ........................19 CHAPTER 2 PIN FUNCTIONS ....................... 22 List of Pin Functions.........................22 Pin I/O Circuits and Recommended Connection of Unused Pins........26 Pin I/O Circuits...........................28 CHAPTER 3 CPU FUNCTION ........................
Page 11 4.7.2 Cautions on bit manipulation instruction for port n register (Pn) ..........120 CHAPTER 5 CLOCK GENERATOR .....................121 Overview ..........................121 Configuration ..........................122 Control Registers........................124 PLL Function ...........................130 5.4.1 Overview............................. 130 5.4.2 PLL mode ........................... 130 5.4.3 Clock-through mode ........................130 Operation ..........................131 5.5.1 Operation of each clock ......................
Page 12 Configuration.......................... 352 Control Register ........................353 Operation ..........................354 8.4.1 Interval timer mode ........................354 Cautions ..........................358 CHAPTER 9 MOTOR CONTROL FUNCTION ..................359 Functional Overview ......................359 Configuration.......................... 360 Control Registers ........................364 Operation ..........................377 9.4.1 System outline ..........................377 9.4.2 Dead-time control (generation of negative-phase wave signal) ..........382 9.4.3...
Page 13 11.9.4 Timer interrupt request signal in timer trigger mode ..............468 11.9.5 Re-conversion start trigger input during stabilization time ............468 11.9.6 Variation of A/D conversion results..................... 468 11.9.7 A/D conversion result hysteresis characteristics................. 468 11.9.8 Restrictions on setting one-shot mode and software trigger mode ..........469 11.10 How to Read A/D Converter Characteristics Table .............470 CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) ..........474 12.1 Features ...........................474...
Page 14 14.2.2 Restore ............................550 14.2.3 Non-maskable interrupt status flag (NP) ..................551 14.3 Maskable Interrupts ....................... 552 14.3.1 Operation ............................552 14.3.2 Restore ............................554 14.3.3 Priorities of maskable interrupts....................555 14.3.4 Interrupt control registers (xxICn) ....................559 14.3.5 Interrupt mask registers 0 to 3 (IMR0 to IMR3)................562 14.3.6 In-service priority register (ISPR) ....................564 14.3.7 Maskable interrupt status flag (ID) ....................565 14.4 External Interrupt Request Input Pins (INTP0 to INTP6) ............
Page 15 CHAPTER 17 REGULATOR ........................605 17.1 Overview ..........................605 17.2 Operation ..........................606 CHAPTER 18 FLASH MEMORY......................607 18.1 Features ...........................607 18.2 Memory Configuration......................608 18.3 Functional Overview.......................609 18.4 Rewriting by Dedicated Flash Memory Programmer ............613 18.4.1 Programming environment ......................613 18.4.2 Communication mode......................... 614 18.4.3 Flash memory control .........................
Page 16: Chapter 1 Introduction
CHAPTER 1 INTRODUCTION The V850ES/IE2 is one of the low-power operation products in the NEC Electronics V850 Series of single-chip microcontrollers designed for real-time control applications. 1.1 General The V850ES/IE2 is a 32-bit single-chip microcontroller that includes the V850ES CPU core and peripheral functions such as ROM/RAM, a timer/counter, serial interfaces, a watchdog timer, and an A/D converter.
Page 17: Features
CHAPTER 1 INTRODUCTION 1.2 Features Minimum instruction execution time: 50 ns (at internal 20 MHz operation) General-purpose registers: 32 bits × 32 Signed multiplication (16 × 16 → 32): 1 to 2 clocks CPU features: Signed multiplication (32 × 32 → 64): 1 to 5 clocks Saturated operation instructions (with overflow/underflow detection function) 32-bit shift instructions: 1 clock Bit manipulation instructions...
Page 18: Applications
CHAPTER 1 INTRODUCTION Clock generator: 2.5 MHz resonator connectable (external clock input prohibited) Multiplication function by PLL clock synthesizer (fixed to multiplication by eight, f 20 MHz) CPU clock division function (f /2, f /4, f Power-save function: HALT/IDLE/ STOP mode Power-on-clear function Low-voltage detection function μ...
Page 19: Pin Configuration
CHAPTER 1 INTRODUCTION 1.5 Pin Configuration • 64-pin plastic LQFP (14 × 14) μ PD70F3713GC-8BS-A μ PD70F3714GC-8BS-A Top View P25/TOQ1B3 PDL3 P24/TOQ1T3 PDL4 P23/TOQ1B2 PDL5/FLMD1 P22/TOQ1T2 PDL6 P21/TOQ1B1 PDL7 P20/TOQ1T1 ANI13 ANI12 FLMD0 ANI11 P10/TOQH01/TIQ01/TOQ01 ANI10 P11/TIQ02/TOQ02 P12/TOQH02/TIQ03/TOQ03 REF1 P13/TIQ00 P14/TOQH03/EVTQ0 Note Note...
Page 20 CHAPTER 1 INTRODUCTION Pin Identification ADTRG0, ADTRG1: A/D trigger input SCKB0: Serial clock ANI00 to ANI03, SIB0: Serial input ANI10 to ANI13: Analog input SOB0: Serial output , AV Analog power supply TIP00, TIP01, , AV Analog reference voltage TIP20, TIP21, REF0 REF1 , AV...
Page 21: Function Blocks
CHAPTER 1 INTRODUCTION 1.6 Function Blocks (1) Internal block diagram INTC INTP0 to INTP6 Instruction queue Multiplier × 1 ch (16 × 16 → 32) 32-bit barrel shifter TIQ00 to TIQ03, EVTQ0, TOQ1OFF, TOQH0OFF System TOQ00 to TOQ03, TOQ10, × 2 ch registers TOQH01 to TOQH03, TOQ1T1 to TOQ1T3,...
Page 22 CHAPTER 1 INTRODUCTION (2) Internal units (a) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as a multiplier (16 bits × 16 bits → 32 bits) and a barrel shifter (32 bits), help accelerate complex processing.
Page 23 CHAPTER 1 INTRODUCTION (i) Serial interface The V850ES/IE2 includes two asynchronous serial interface A (UARTA) channels and one 3-wire variable length serial I/O (CSIB) channel as the serial interface. For UARTA, data is transferred via the TXDAn and RXDAn pins (n = 0, 1).
Page 24: Chapter 2 Pin Functions
CHAPTER 2 PIN FUNCTIONS 2.1 List of Pin Functions The names and functions of the pins in the V850ES/IE2 are listed below. These pins can be divided into port pins and non-port pins according to their function. There are two power supplies for the I/O buffer of a pin: power supply for A/D converter (AV...
Page 25 CHAPTER 2 PIN FUNCTIONS (2/2) Pin Name Pin No. Function Alternate Function Port 2 TOQ1T1 8-bit I/O port TOQ1B1 Input data read/output data write is enabled in 1-bit units. TOQ1T2 Use of an on-chip pull-up resistor can be specified in 1-bit units (the on-chip pull-up resistor can be connected only in TOQ1B2 the input mode of the port mode, or when TOQ1T1 to...
Page 26 CHAPTER 2 PIN FUNCTIONS (2) Non-port pins (1/2) Pin Name Pin No. Function Alternate Function ADTRG0 Input External trigger input for A/D converters 0, 1 INTP4/P04 ADTRG1 Input INTP5/P05 − ANI00 Input Analog input to A/D converters 0, 1 − ANI01 Input −...
Page 27 CHAPTER 2 PIN FUNCTIONS (2/2) Pin Name Pin No. Function Alternate Function TIP00 Input External event count input/external trigger input/capture TOP00/P43 trigger input of TMP0 TIP01 Capture trigger input of TMP0 TOP01/P44 Note External event count input/external trigger input/capture TOQ00 (CLMER) TIP20 Note trigger input of TMP2...
Page 28: Pin I/O Circuits And Recommended Connection Of Unused Pins
CHAPTER 2 PIN FUNCTIONS 2.2 Pin I/O Circuits and Recommended Connection of Unused Pins (1/2) Pin Name Alternate-Function Pin Name Pin No. I/O Circuit Recommended Connection Type INTP0/TOQH0OFF Input: Independently connect to EV via a resistor. INTP1/TOQ1OFF Output: Leave open. INTP2/TOP2OFF INTP3/TOP3OFF INTP4/ADTRG0...
Page 29 CHAPTER 2 PIN FUNCTIONS (2/2) Pin Name Alternate-Function Pin Name Pin No. I/O Circuit Recommended Connection Type − Input: Independently connect to PDL0 5-AG or EV via a resistor. − PDL1 Output: Leave open. − PDL2 − PDL3 − PDL4 PDL5 FLMD1 −...
Page 30: Pin I/O Circuits
CHAPTER 2 PIN FUNCTIONS 2.3 Pin I/O Circuits Type 7 Type 2 P-ch Comparator N-ch – , AV Schmitt-triggered input with hysteresis characteristics (Threshold voltage) Type 8-P Type 5-AG Pull-up Pull-up P-ch P-ch enable enable Data P-ch Data P-ch IN/OUT IN/OUT Output N-ch...
Page 31: Chapter 3 Cpu Function
CHAPTER 3 CPU FUNCTION The CPU of the V850ES/IE2 is based on the RISC architecture and executes most instructions in one clock cycle by using 5-stage pipeline control. 3.1 Features Minimum instruction execution time: 50 ns (@ 20 MHz operation: 4.5 to 5.5 V (when using A/D converter), 3.5 to 5.5 V (when not using A/D converter))
Page 32: Cpu Register Set
CHAPTER 3 CPU FUNCTION 3.2 CPU Register Set The CPU registers of the V850ES/IE2 can be classified into two categories: a general-purpose program register set and a dedicated system register set. All the registers have 32-bit width. For details, refer to the V850ES Architecture User’s Manual.
Page 33: Program Register Set
CHAPTER 3 CPU FUNCTION 3.2.1 Program register set The program register set includes general-purpose registers and a program counter. (1) General-purpose registers (r0 to r31) Thirty-two general-purpose registers, r0 to r31, are available. All of these registers can be used as a data variable or address variable.
Page 34: System Register Set
CHAPTER 3 CPU FUNCTION 3.2.2 System register set System registers control the status of the CPU and hold interrupt information. Read from and write to system registers are performed by setting the system register numbers shown below with the system register load/store instructions (LDSR, STSR instructions). Table 3-2.
Page 35 CHAPTER 3 CPU FUNCTION (1) Interrupt status saving registers (EIPC, EIPSW) There are two interrupt status saving registers, EIPC and EIPSW. Upon occurrence of a software exception or a maskable interrupt, the contents of the program counter (PC) are saved to EIPC and the contents of the program status word (PSW) are saved to EIPSW (upon occurrence of a non-maskable interrupt (NMI), the contents are saved to the NMI status saving registers (FEPC, FEPSW)).
Page 36 CHAPTER 3 CPU FUNCTION (2) NMI status saving registers (FEPC, FEPSW) There are two NMI status saving registers, FEPC and FEPSW. Upon occurrence of a non-maskable interrupt (NMI), the contents of the program counter (PC) are saved to FEPC and the contents of the program status word (PSW) are saved to FEPSW. The address of the next instruction following the instruction executed when a non-maskable interrupt occurs is saved to FEPC, except for some instructions.
Page 37 CHAPTER 3 CPU FUNCTION (4) Program status word (PSW) The program status word (PSW) is a collection of flags that indicate the program status (instruction execution result) and the CPU status. When the contents of this register are changed using the LDSR instruction, the new contents become valid immediately following completion of LDSR instruction execution.
Page 38 CHAPTER 3 CPU FUNCTION (2/2) Note During saturated operation, the saturated operation results are determined by the contents of the OV flag and S flag. The SAT flag is set (to 1) only when the OV flag is set (to 1) during saturated operation. Operation result status Flag status Saturated...
Page 39 CHAPTER 3 CPU FUNCTION (6) Exception/debug trap status saving registers (DBPC, DBPSW) There are two exception/debug trap status saving registers, DBPC and DBPSW. Upon occurrence of an exception trap or debug trap, the contents of the program counter (PC) are saved to DBPC, and the program status word (PSW) contents are saved to DBPSW.
Page 40: Operating Modes
CHAPTER 3 CPU FUNCTION 3.3 Operating Modes The V850ES/IE2 has the following operating modes. (1) Normal operating mode After the system has been released from the reset state, the pins related to the bus interface are set to the port mode, execution branches to the reset entry address of the internal ROM, and instruction processing is started.
Page 41: Address Space
CHAPTER 3 CPU FUNCTION 3.4 Address Space 3.4.1 CPU address space For instruction addressing, an internal ROM area of up to 1 MB, and an internal RAM area are supported in a linear address space (program space) of up to 64 MB. For operand addressing (data access), up to 4 GB of a linear address space (data space) is supported.
Page 42: Wraparound Of Cpu Address Space
CHAPTER 3 CPU FUNCTION 3.4.2 Wraparound of CPU address space (1) Program space Of the 32 bits of the program counter (PC), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid. Even if a carry or borrow occurs from bit 25 to bit 26 as a result of branch address calculation, the higher 6 bits ignore this and remain 0.
Page 43: Memory Map
CHAPTER 3 CPU FUNCTION 3.4.3 Memory map The V850ES/IE2 has reserved areas as shown below. Figure 3-2. Data Memory Map (Physical Addresses) 3FFFFFFH 3FFFFFFH On-chip peripheral I/O area (4 KB) 3FFF000H (80 KB) 3FFEFFFH 3FEC000H 3FEBFFFH Internal RAM area (60 KB)
Page 44 CHAPTER 3 CPU FUNCTION Figure 3-3. Program Memory Map 03FFFFFFH Access-prohibited area (program fetch disabled area) 03FFF000H 03FFEFFFH Internal RAM area (60 KB) 3FF0000H 3FEFFFFH Access-prohibited area (program fetch disabled area) 00100000H 000FFFFFH Internal ROM area (1 MB) 00000000H User’s Manual U17716EJ2V0UD...
Page 45: Areas
CHAPTER 3 CPU FUNCTION 3.4.4 Areas (1) Internal ROM area An area of 1 MB from 0000000H to 00FFFFFH is reserved for the internal ROM area. (a) Internal ROM (128 KB) μ A 128 KB area from 0000000H to 001FFFFH is provided in the PD70F3714.
Page 46 An area of 60 KB maximum from 3FF0000H to 3FFEFFFH is reserved for the internal RAM area. A 6 KB area from 3FFD800H to 3FFEFFFH is provided as physical internal RAM for the V850ES/IE2. Addresses 3FF0000H to 3FFD7FFH are an access-prohibited area.
Page 47 CHAPTER 3 CPU FUNCTION (c) Internal memory size setting register (IMS) The IMS register is used to set the internal RAM size of the V850ES/IE2. This register is write-only, in 8-bit units. Reset sets this register to 00H. Cautions 1. Write the IMS register before the internal RAM is accessed. This register can be written only once after reset has been released.
Page 48 CHAPTER 3 CPU FUNCTION (3) On-chip peripheral I/O area A 4 KB area from 3FFF000H to 3FFFFFFH is reserved as the on-chip peripheral I/O area. Figure 3-7. On-Chip Peripheral I/O Area Physical address space Logical address space 3FFFFFFH FFFFFFFH On-chip peripheral I/O area (4 KB) 3FFF000H FFFF000H...
Page 49: Recommended Use Of Address Space
(2) Data space With the V850ES/IE2 it seems that there are sixty-four 64 MB address spaces on the 4 GB CPU address space. Therefore, the least significant bit (bit 25) of a 26-bit address is sign-extended to 32 bits and allocated as an address.
Page 50 CHAPTER 3 CPU FUNCTION (a) Application example of wraparound If R = r0 (zero register) is specified for the LD/ST disp16 [R] instruction, a range of addresses 00000000H ±32 KB can be addressed by sign-extended disp16. All the resources, including the internal hardware, can be addressed by one pointer.
Page 51 CHAPTER 3 CPU FUNCTION Figure 3-8. Recommended Memory Map Program space Data space FFFFFFFFH On-chip peripheral I/O FFFFF000H FFFFEFFFH Internal RAM xFFFFFFFH FFFF0000H On-chip FFFEFFFFH peripheral I/O xFFFF000H xFFFEFFFH Internal RAM xFFFD800H xFFFD7FFH xFFF0000H 0 4 0 0 0 0 0 0 H xFFEFFFFH 03FFFFFFH On-chip...
Page 52: On-Chip Peripheral I/O Registers
CHAPTER 3 CPU FUNCTION 3.4.6 On-chip peripheral I/O registers (1/6) Address Function Register Name Symbol Bit Units for Manipulation After Reset √ √ FFFFF004H Port DL register L PDLL Undefined √ √ FFFFF024H Port DL mode register L PMDL √ FFFFF06EH System wait control register VSWC...
Page 53 CHAPTER 3 CPU FUNCTION (2/6) Address Function Register Name Symbol Bit Units for Manipulation After Reset √ √ FFFFF158H Interrupt control register TP2CCIC1 √ √ FFFFF15AH Interrupt control register TP3OVIC √ √ FFFFF15CH Interrupt control register TP3CCIC0 √ √ FFFFF15EH Interrupt control register TP3CCIC1 √...
Page 54 CHAPTER 3 CPU FUNCTION (3/6) Address Function Register Name Symbol Bit Units for Manipulation After Reset √ √ FFFFF310H External interrupt noise elimination control INTPNRC register √ √ FFFFF400H Port 0 register Undefined √ √ FFFFF402H Port 1 register Undefined √...
Page 55 CHAPTER 3 CPU FUNCTION (4/6) Address Function Register Name Symbol Bit Units for Manipulation After Reset √ FFFFF60CH TMQ1 capture/compare register 3 TQ1CCR3 0000H √ FFFFF60EH TMQ1 counter read buffer register TQ1CNT 0000H √ √ FFFFF620H TMQ1 option register 1 TQ1OPT1 √...
Page 56 CHAPTER 3 CPU FUNCTION (5/6) Address Function Register Name Symbol Bit Units for Manipulation After Reset √ √ FFFFF802H System status register √ √ FFFFF820H Power save mode register PSMR √ FFFFF822H Clock control register √ √ FFFFF828H Processor clock control register √...
Page 57 CHAPTER 3 CPU FUNCTION (6/6) Address Function Register Name Symbol Bit Units for Manipulation After Reset √ FFFFFD04H CSIB0 receive data register CB0RX 0000H √ FFFFFD04H CSIB0 receive data register L CB0RXL √ FFFFFD06H CSIB0 transmit data register CB0TX 0000H √...
Page 58: Special Registers
Special registers Special registers are registers that are protected from being written with illegal data due to a program hang-up. The V850ES/IE2 has the following seven special registers divided into two types. [Special registers subject to error report by SYS.PRERR bit] •...
Page 59 CHAPTER 3 CPU FUNCTION (1) Setting data to special registers Set data to the special registers in the following sequence. <1> Prepare data to be set to the special register in a general-purpose register. <2> Write the data prepared in <1> to the command register. <3>...
Page 60 CHAPTER 3 CPU FUNCTION (2) Command register PRCMD is an 8-bit register that protects the registers that may seriously affect the application system from being written, so that the system does not inadvertently stop due to a program hang-up. This register can be used as PRCMD or PRCMD2 via a special register setting.
Page 61 CHAPTER 3 CPU FUNCTION (3) System status register Status flags that indicate the operation status of the overall system are allocated to this register. This register can be used as SYS or SYS2 via a special register setting. (a) System status register (SYS) If this register is not written in the correct sequence including an access to the PRCMD register, data is not written to the intended register, a protection error occurs, and the PRERR flag is set.
Page 62 CHAPTER 3 CPU FUNCTION The operating conditions of the PRERR flag are shown below. For the operating conditions of the PRERR2 flag, read PRCMD and SYS as PRCMD2 and SYS2 in the following explanation. (i) Set condition (PRERR flag = 1) •...
Page 63: System Wait Control Register (Vswc)
Access to on-chip peripheral I/O registers of the V850ES CPU core is basically made in 3 clocks; however, in the V850ES/IE2, a wait is required in addition to those 3 clocks. Set 11H (set wait for 2 clocks) to the VSWC register.
Page 64: Chapter 4 Port Functions
TOP2OFF, TOQ1OFF, TOP3OFF, and TOQH0OFF pins or software. Basic Port Configuration The V850ES/IE2 incorporates a total of 39 I/O ports labeled ports 0 to 4 and DL. The port configuration is shown below. Figure 4-1. Port Configuration...
Page 65: Port Configuration
CHAPTER 4 PORT FUNCTIONS Port Configuration Table 4-2. Port Configuration Item Configuration Control registers Port n register (Pn: n = 0 to 4, DLL) Port n mode register (PMn: n = 0 to 4, DLL) Port n mode control register (PMCn: n = 0 to 4) Port n function control register (PFCn: n = 1, 3, 4) Port 1 function control expansion register (PFCE1) Pull-up resistor option register (PUn: n = 0 to 4, DLL)
Page 66 CHAPTER 4 PORT FUNCTIONS (2) Port n mode register (PMn) The PMn register specifies the input or output mode of the corresponding port pin. Each bit of this register corresponds to one pin of port n, and the input or output mode can be specified in 1-bit units.
Page 67 CHAPTER 4 PORT FUNCTIONS (5) Port n function control expansion register (PFCEn) The PFCEn register specifies the alternate function of a port pin to be used if the pin has three or more alternate functions. Each bit of this register corresponds to one pin of port n, and the alternate function of a port pin can be specified in 1-bit units.
Page 68 CHAPTER 4 PORT FUNCTIONS (7) Port settings Set the ports as follows. Figure 4-2. Register Settings and Pin Functions Port mode Output mode "0" PMn register Input mode "1" Alternate function (when two alternate functions are available) "0" Alternate function 1 "0"...
Page 69: Port 0
CHAPTER 4 PORT FUNCTIONS 4.3.1 Port 0 Port 0 can be set to the input or output mode in 1-bit units. Port 0 has an alternate function as the following pins. Table 4-4. Alternate-Function Pins of Port 0 Note 1 Pin Name Pin No.
Page 70 CHAPTER 4 PORT FUNCTIONS A noise elimination function is included as an alternate function of port 0. Noise Edge To INTC elimination detection Analog delay PMC0n INTR0n INTF0n To high-impedance output controller Noise Edge To INTC elimination detection Analog delay PMC0m INTR0m INTF0m...
Page 71 CHAPTER 4 PORT FUNCTIONS (1) Registers (a) Port 0 register (P0) After reset: Undefined Address: FFFFF400H Control of output data (in output mode) (n = 0 to 6) Output 0. Output 1. (b) Port 0 mode register (PM0) After reset: FFH Address: FFFFF420H PM06 PM05...
Page 72 CHAPTER 4 PORT FUNCTIONS (c) Port 0 mode control register (PMC0) After reset: 00H Address: FFFFF440H PMC0 PMC06 PMC05 PMC04 PMC03 PMC02 PMC01 PMC00 Specification of operating mode of P06 pin PMC06 I/O port INTP6 input Specification of operating mode of P05 pin PMC05 I/O port INTP5 input/ADTRG1 input...
Page 73 CHAPTER 4 PORT FUNCTIONS (2) Block diagrams Figure 4-3. Block Diagram of P00 to P05 Pins PU0n P-ch INTR INTR0 INTR0n INTF INTF0 INTF0n PMC0 PMC0n PM0n P00/INTP0/TOQH0OFF PORT P01/INTP1/TOQ1OFF P02/INTP2/TOP2OFF P03/INTP3/TOP3OFF P04/INTP4/ADTRG0 P05/INTP5/ADTRG1 Address RESET Analog Noise elimination INTP0 to INTP5 input noise Edge detection elimination...
Page 74 CHAPTER 4 PORT FUNCTIONS Figure 4-4. Block Diagram of P06 Pin PU06 P-ch INTR INTR0 INTR06 INTF INTF0 INTF06 PMC0 PMC06 PM06 PORT P06/INTP6 Address RESET Digital Noise elimination INTP6 input noise Edge detection elimination User’s Manual U17716EJ2V0UD...
Page 75: Port 1
CHAPTER 4 PORT FUNCTIONS 4.3.2 Port 1 Port 1 can be set to the input or output mode in 1-bit units. Port 1 has an alternate function as the following pins. Table 4-5. Alternate-Function Pins of Port 1 Note 1 Pin Name Pin No.
Page 76 CHAPTER 4 PORT FUNCTIONS (1) Registers (a) Port 1 register (P1) After reset: Undefined Address: FFFFF402H Control of output data (in output mode) (n = 0 to 4, 6, 7) Output 0. Output 1. (b) Port 1 mode register (PM1) After reset: FFH Address: FFFFF422H PM17...
Page 77 CHAPTER 4 PORT FUNCTIONS (c) Port 1 mode control register (PMC1) After reset: 00H Address: FFFFF442H PMC1 PMC17 PMC16 PMC14 PMC13 PMC12 PMC11 PMC10 PMC17 Specification of operating mode of P17 pin I/O port TOP21 output/TIP21 input Specification of operating mode of P16 pin PMC16 I/O port TOQ00 (CLMER) output/TIP20 input...
Page 78 CHAPTER 4 PORT FUNCTIONS (d) Port 1 function control register (PFC1) After reset: 00H Address: FFFFF462H PFC1 PFC17 PFC16 PFC14 PFC13 PFC12 PFC11 PFC10 Remark For the specification of alternate function, see 4.3.2 (1) (f) Setting of alternate function of port 1. (e) Port 1 function control expansion register (PFCE1) After reset: 00H Address: FFFFF702H...
Page 79 CHAPTER 4 PORT FUNCTIONS (f) Setting of alternate function of port 1 PFC17 Specification of alternate function of P17 pin TOP21 output TIP21 input PFC16 Specification of alternate function of P16 pin Note 1 TOQ00 (CLMER) output TIP20 input PFC14 Specification of alternate function of P14 pin Note 2 TOQH03 output...
Page 80 CHAPTER 4 PORT FUNCTIONS (g) Pull-up resistor option register 1 (PU1) After reset: 00H Address: FFFFFC42H PU17 PU16 PU14 PU13 PU12 PU11 PU10 PU1n Control of on-chip pull-up resistor connection (n = 0 to 4, 6, 7) Do not connect Note Connect Note An on-chip pull-up resistor can be connected only when the pins are in input mode in the port mode or...
Page 81 CHAPTER 4 PORT FUNCTIONS (2) Block diagrams Figure 4-5. Block Diagram of P10 and P12 Pins PU1n P-ch Note 1 Note 2 PFCE PFCE1 PFCE1n PFC1 PFC1n PMC1 PMC1n PM1n TOQH01, TOQH02 outputs TOQ01, TOQ03 outputs P10/TOQH01/TIQ01/TOQ01 PORT P12/TOQH02/TIQ03/TOQ03 Address RESET Digital noise TIQ01, TIQ03 inputs...
Page 82 CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of P11 Pin PU11 P-ch PFCE PFCE1 PFCE11 PFC1 PFC11 PMC1 PMC11 PM11 Setting prohibited TOQ02 output PORT P11/TIQ02/TOQ02 Address RESET Digital noise TIQ02 input elimination User’s Manual U17716EJ2V0UD...
Page 83 CHAPTER 4 PORT FUNCTIONS Figure 4-7. Block Diagram of P13 Pin PU13 P-ch PFC1 PFC13 PMC1 PMC13 PM13 Setting prohibited PORT P13/TIQ00 Address RESET Digital noise TIQ00 input elimination User’s Manual U17716EJ2V0UD...
Page 84 CHAPTER 4 PORT FUNCTIONS Figure 4-8. Block Diagram of P14 Pin PU14 P-ch Note 1 Note 2 PFC1 PFC14 PMC1 PMC14 PM14 TOQH03 output PORT P14/TOQH03/EVTQ0 Address RESET Digital noise EVTQ0 input elimination Notes 1. Output of high impedance setting signal from high impedance output controller 2.
Page 85 CHAPTER 4 PORT FUNCTIONS Figure 4-9. Block Diagram of P16 Pin PU16 P-ch PFC1 PFC16 PMC1 PMC16 PM16 Note 1 PORT Note 2 P16 (CLMER) Note 2 TOQ00 (CLMER) output Note 2 TOQ00 (CLMER) TIP20 Address RESET Digital noise TIP20 input elimination Notes 1.
Page 86 CHAPTER 4 PORT FUNCTIONS Figure 4-10. Block Diagram of P17 Pin PU17 P-ch Note 1 Note 2 PFC1 PFC17 PMC1 PMC17 PM17 TOP21 output PORT P17/TOP21/TIP21 Address RESET Digital noise TIP21 input elimination Notes 1. Output of high impedance setting signal from high impedance output controller 2.
Page 87: Port 2
CHAPTER 4 PORT FUNCTIONS 4.3.3 Port 2 Port 2 can be set to the input or output mode in 1-bit units. Port 2 has an alternate function as the following pins. Table 4-6. Alternate-Function Pins of Port 2 Note Pin Name Pin No.
Page 88 CHAPTER 4 PORT FUNCTIONS (1) Registers (a) Port 2 register (P2) After reset: Undefined Address: FFFFF404H Control of output data (in output mode) (n = 0 to 7) Output 0. Output 1. (b) Port 2 mode register (PM2) After reset: FFH Address: FFFFF424H PM27 PM26...
Page 89 CHAPTER 4 PORT FUNCTIONS (c) Port 2 mode control register (PMC2) After reset: 00H Address: FFFFF444H PMC2 PMC27 PMC26 PMC25 PMC24 PMC23 PMC22 PMC21 PMC20 PMC27 Specification of operating mode of P27 pin I/O port TOP31 output Specification of operating mode of P26 pin PMC26 I/O port TOQ10 output...
Page 90 CHAPTER 4 PORT FUNCTIONS (d) Pull-up resistor option register 2 (PU2) After reset: 00H Address: FFFFFC44H PU27 PU26 PU25 PU24 PU23 PU22 PU21 PU20 PU2n Control of on-chip pull-up resistor connection (n = 0 to 7) Do not connect Note Connect Note An on-chip pull-up resistor can be connected only when the pins are in input mode in the port mode.
Page 91 CHAPTER 4 PORT FUNCTIONS (2) Block diagram Figure 4-11. Block Diagram of P20 to P25 and P27 Pins PU2n P-ch Note 1 Note 2 PMC2 PMC2n PM2n TOQ1T1 to TOQ1T3, TOQ1B1 to TOQ1B3, TOP31 output P20/TOQ1T1 P21/TOQ1B1 P22/TOQ1T2 PORT P23/TOQ1B2 P24/TOQ1T3 P25/TOQ1B3 P27/TOP31...
Page 92 CHAPTER 4 PORT FUNCTIONS Figure 4-12. Block Diagram of P26 Pin PU26 P-ch PMC2 PMC26 PM26 TOQ10 output PORT P26/TOQ10 Address User’s Manual U17716EJ2V0UD...
Page 93: Port 3
CHAPTER 4 PORT FUNCTIONS 4.3.4 Port 3 Port 3 can be set to the input or output mode in 1-bit units. Port 3 has an alternate function as the following pins. Table 4-7. Alternate-Function Pins of Port 3 Note 1 Pin Name Pin No.
Page 94 CHAPTER 4 PORT FUNCTIONS (c) Port 3 mode control register (PMC3) After reset: 00H Address: FFFFF446H PMC3 PMC33 PMC32 PMC31 PMC30 PMC33 Specification of operating mode of P33 pin I/O port TXDA1 output PMC32 Specification of operating mode of P32 pin I/O port RXDA1 input PMC31...
Page 95 CHAPTER 4 PORT FUNCTIONS (e) Pull-up resistor option register 3 (PU3) After reset: 00H Address: FFFFFC46H PU33 PU32 PU31 PU30 PU3n Control of on-chip pull-up resistor connection (n = 0 to 3) Do not connect Note Connect Note An on-chip pull-up resistor can be connected only when the pins are in input mode in the port mode or when the pins function as input pins in the alternate-function mode.
Page 96 CHAPTER 4 PORT FUNCTIONS (2) Block diagram Figure 4-13. Block Diagram of P30 Pin PU30 P-ch PMC3 PMC30 PM30 PORT P30/RXDA0 Address RESET RXDA0 input User’s Manual U17716EJ2V0UD...
Page 97 CHAPTER 4 PORT FUNCTIONS Figure 4-14. Block Diagram of P31 Pin PU31 P-ch PMC3 PMC31 PM31 TXDA0 output PORT P31/TXDA0 Address User’s Manual U17716EJ2V0UD...
Page 98 CHAPTER 4 PORT FUNCTIONS Figure 4-15. Block Diagram of P32 Pin PU32 P-ch PFC3 PFC32 PMC3 PMC32 PM32 PORT P32/RXDA1 Address RESET Setting prohibited RXDA1 input User’s Manual U17716EJ2V0UD...
Page 99 CHAPTER 4 PORT FUNCTIONS Figure 4-16. Block Diagram of P33 Pin PU33 P-ch PFC3 PFC33 PMC3 PMC33 PM33 Setting prohibited TXDA1 output PORT P33/TXDA1 Address User’s Manual U17716EJ2V0UD...
Page 100: Port 4
CHAPTER 4 PORT FUNCTIONS 4.3.5 Port 4 Port 4 can be set to the input or output mode in 1-bit units. Port 4 has an alternate function as the following pins. Table 4-8. Alternate-Function Pins of Port 4 Note 1 Pin Name Pin No.
Page 101 CHAPTER 4 PORT FUNCTIONS (c) Port 4 mode control register (PMC4) After reset: 00H Address: FFFFF448H PMC4 PMC44 PMC43 PMC42 PMC41 PMC40 PMC44 Specification of operating mode of P44 pin I/O port TOP01 output/TIP01 input PMC43 Specification of operating mode of P43 pin I/O port TOP00 output/TIP00 input PMC42...
Page 102 CHAPTER 4 PORT FUNCTIONS (e) Pull-up resistor option register 4 (PU4) After reset: 00H Address: FFFFFC48H PU44 PU43 PU42 PU41 PU40 PU4n Control of on-chip pull-up resistor connection (n = 0 to 4) Do not connect Note Connect Note An on-chip pull-up resistor can be connected only when the pins are in input mode in the port mode or when the pins function as input pins in the alternate-function mode (including when in the SCKB0 pin slave mode).
Page 103 CHAPTER 4 PORT FUNCTIONS (2) Block diagram Figure 4-17. Block Diagram of P40 Pin PU40 P-ch PMC4 PMC40 PM40 PORT P40/SIB0 Address RESET SIB0 input User’s Manual U17716EJ2V0UD...
Page 104 CHAPTER 4 PORT FUNCTIONS Figure 4-18. Block Diagram of P41 Pin PU41 P-ch PMC4 PMC41 PM41 SOB0 output PORT P41/SOB0 Address User’s Manual U17716EJ2V0UD...
Page 105 CHAPTER 4 PORT FUNCTIONS Figure 4-19. Block Diagram of P42 Pin PU42 P-ch SCKB0 master mode PMC4 PMC42 PM42 SCKB0 output PORT P42/SCKB0 Address RESET SCKB0 input User’s Manual U17716EJ2V0UD...
Page 106 CHAPTER 4 PORT FUNCTIONS Figure 4-20. Block Diagram of P43 and P44 Pins PU4n P-ch PFC4 PFC4n PMC4 PMC4n PM4n TOP00, TOP01 outputs P43/TOP00/TIP00 PORT P44/TOP01/TIP01 Address RESET Digital noise TIP00, TIP01 inputs elimination Remark n = 3, 4 User’s Manual U17716EJ2V0UD...
Page 107: Port Dl
CHAPTER 4 PORT FUNCTIONS 4.3.6 Port DL Port DL can be set to the input or output mode in 1-bit units. Port DL has an alternate function as the following pins. Table 4-9. Alternate-Function Pins of Port DL Note 1 Pin Name Pin No.
Page 108 CHAPTER 4 PORT FUNCTIONS (1) Registers (a) Port DL register L (PDLL) After reset: Undefined Address: FFFFF004H PDLL PDL7 PDL6 PDL5 PDL4 PDL3 PDL2 PDL1 PDL0 PDLn Control of output data (in output mode) (n = 0 to 7) Output 0. Output 1.
Page 109 CHAPTER 4 PORT FUNCTIONS (2) Block diagram Figure 4-21. Block Diagram of PDL0 to PDL7 Pins PUDLL PUDLn P-ch PMDLL PMDLn PORT PDLL PDL0 to PDL4 Note PDLn PDL5/FLMD1 PDL6, PDL7 Address Note FLMD1 input Note This pin is used in the flash programming mode and does not have to be manipulated by a port control register.
Page 110: Output Data And Read Value Of Port For Each Setting
CHAPTER 4 PORT FUNCTIONS Output Data and Read Value of Port for Each Setting The following shows the values used to select the alternate function of the respective pins, output data and read value of each port for each setting. In addition to the settings shown here, setting of each peripheral function control register is necessary.
Page 111 Table 4-10. Output Data and Port Read Value for Each Setting (1/4) Port Name Function PMCmn PFCEmn PFCmn PMmn Output Data Pmn Read Value Remark P00 to P06 Output port None None Port latch Port latch − Input port Pin level −...
Page 112 Table 4-10. Output Data and Port Read Value for Each Setting (2/4) Port Name Function PMCmn PFCEmn PFCmn PMmn Output Data Pmn Read Value Remark × Output port None Port latch Port latch − Input port Pin level TOQH03 None Alternate output Port latch (timer output)
Page 113 Table 4-10. Output Data and Port Read Value for Each Setting (3/4) Port Name Function PMCmn PFCEmn PFCmn PMmn Output Data Pmn Read Value Remark × Output port None Port latch Port latch − Input port Pin level − RXDA1 None Port latch Alternate input (serial input)
Page 114 Table 4-10. Output Data and Port Read Value for Each Setting (4/4) Port Name Function PMCmn PFCEmn PFCmn PMmn Output Data Pmn Read Value Remark × P43, P44 Output port None Port latch Port latch − Input port Pin level TOP00, TOP01 None Alternate output...
Page 115: Port Register Settings When Alternate Function Is Used
CHAPTER 4 PORT FUNCTIONS Port Register Settings When Alternate Function Is Used The following shows the port register settings when each port is used for an alternate function. When using a port pin as an alternate-function pin, refer to the description of each pin. User’s Manual U17716EJ2V0UD...
Page 116 Table 4-11. Using Port Pin as Alternate-Function Pin (1/3) Pin Name Alternate Pin Pnx Bit of Pn Register PMnx Bit of PMn Register PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bit PMCn PFCEn Register PFCn Register (Register) Name Register −...
Page 117 Table 4-11. Using Port Pin as Alternate-Function Pin (2/3) Pin Name Alternate Pin Pnx Bit of Pn Register PMnx Bit of PMn Register PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bit PMCn PFCEn Register PFCn Register (Register) Name Register −...
Page 118 Table 4-11. Using Port Pin as Alternate-Function Pin (3/3) Pin Name Alternate Pin Pnx Bit of Pn Register PMnx Bit of PMn Register PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bit PMCn PFCEn Register PFCn Register (Register) Name Register −...
Page 119: Noise Eliminator
CHAPTER 4 PORT FUNCTIONS Noise Eliminator A timing controller used to secure the noise elimination time is provided for the following pins. Input signals that change within the noise elimination time are not internally acknowledged. <R> Table 4-12. Noise Eliminator Unit Target Pin Delay...
Page 120 CHAPTER 4 PORT FUNCTIONS The following shows an example of digital noise elimination timing of the INTP6 pin. <R> Figure 4-22. Example of Noise Elimination Timing Noise elimination clock Input signal Sampling 5 times Sampling 5 times 2 clocks 2 clocks 3 clocks 3 clocks 4 clocks...
Page 121: Cautions
CHAPTER 4 PORT FUNCTIONS <R> (1) External interrupt noise elimination control register (INTPNRC) The INTPNRC register is used to select the sampling clock that is used to eliminate digital noise on the INTP6 pin. If the same level is not detected five times in a row, the signal is eliminated as noise. This register can be read or written in 8-bit or 1-bit units.
Page 122: Cautions On Bit Manipulation Instruction For Port N Register (Pn)
Explanation: The targets of writing to and reading from the Pn register of a port whose PMnm bit is 1 are the output latch and pin status, respectively. A bit manipulation instruction is executed in the following order in the V850ES/IE2. <1> The Pn register is read in 8-bit units.
Page 123: Chapter 5 Clock Generator
CHAPTER 5 CLOCK GENERATOR Overview The features of clock generator are as follows. Oscillator • In PLL mode: = 2.5 MHz (f = 20 MHz) • In clock-through mode: f = 2.5 MHz (f = 2.5 MHz) Multiply (×8 fixed) function by PLL (Phase Locked Loop) •...
Page 124: Configuration
CHAPTER 5 CLOCK GENERATOR Configuration Figure 5-1. Clock Generator SELPLL IDLE mode CK1, CK0 bits IDLE Oscillator Prescaler 2 control HALT mode HALT CPU clock control Internal system Oscillator clock stop control STOP mode Oscillation stabilization time wait to f /2,048 Oscillation stabilization Peripheral clock...
Page 125 CHAPTER 5 CLOCK GENERATOR (1) Oscillator The main resonator oscillates the following frequencies (f • In PLL mode (×8 fixed): f = 2.5 MHz (f = 20 MHz) • In clock-through mode: f = 2.5 MHz (f = 2.5 MHz) (2) IDLE control All functions other than the oscillator, PLL, clock monitor operation, and CSIB in slave mode are stopped.
Page 126: Control Registers
CHAPTER 5 CLOCK GENERATOR Control Registers The clock generator is controlled by the following seven registers. • PLL control register (PLLCTL) • Clock control register (CKC) • Processor clock control register (PCC) • Power save control register (PSC) • Power save mode register (PSMR) •...
Page 127 CHAPTER 5 CLOCK GENERATOR (2) Clock control register (CKC) The CKC register is used to control the PLL mode. Before using the PLL mode (PLLCTL.SELPLL bit = 1), be sure to set the CKC register to 0BH. Unless the CKC register has been set, the operation is not guaranteed. The CKC register is a special register.
Page 128 CHAPTER 5 CLOCK GENERATOR (4) Power save control register (PSC) The PSC register is a special register. Data can be written to this register only in a combination of specific sequences (see 3.4.7 Special registers). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 129 CHAPTER 5 CLOCK GENERATOR (5) Power save mode register (PSMR) The PSMR register is an 8-bit register that controls the operation in the software standby mode. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H Address: FFFFF820H <...
Page 130 CHAPTER 5 CLOCK GENERATOR (6) Oscillation stabilization time select register (OSTS) The OSTS register selects the oscillation stabilization time until the oscillation stabilizes after the STOP mode is released by interrupt request. This register can be read or written in 8-bit units. Reset sets this register to 06H.
Page 131 CHAPTER 5 CLOCK GENERATOR (7) Clock monitor mode register (CLM) The CLM register sets the clock monitor operation mode. It can be written only in a combination of specific sequences (see 3.4.7 Special registers). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 132: Pll Function
(frequency stabilization time) during which the phase is locked at a specific frequency and oscillation is stabilized. In the V850ES/IE2, the lockup time after release of reset is secured automatically.
Page 133: Operation
CHAPTER 5 CLOCK GENERATOR Operation 5.5.1 Operation of each clock The following table shows the operation status of each clock. Table 5-2. Operation Status of Each Clock Power Save Mode Oscillator Internal CPU Clock Peripheral Watchdog System Clock Timer Clock Clock (f /512) /2,048)
Page 134: Operation Timing
CHAPTER 5 CLOCK GENERATOR 5.5.2 Operation timing (1) Power on (power-on reset) Oscillation stabilization time of clock from oscillator PLL lockup time 13.1 ms (2.5 MHz) 13.1 ms (2.5 MHz) RESET (input) <1> <3> OST counter 00H (initialization) PLL output clock <2>...
Page 135 CHAPTER 5 CLOCK GENERATOR (2) Reset input with power on Oscillation stabilization time PLL lockup time of clock from oscillator 13.1 ms (2.5 MHz) 13.1 ms (2.5 MHz) Note <1> Reset <3> OST counter 00H (initialization) PLL output clock <2> PLL output stabilized CPU reset signal Oscillation stabilization...
Page 136 CHAPTER 5 CLOCK GENERATOR (3) When releasing STOP mode by interrupt request Oscillation stabilization time of clock from oscillator PLL lockup time is is 1/2 of set value of 1/2 of set value of <3> OSTS register OSTS register <2> <1>...
Page 137: Clock Monitor
CHAPTER 5 CLOCK GENERATOR Clock Monitor (1) Function The clock monitor samples the clock generated by the oscillator (f ), by using the internal oscillation clock. When it detects an error (stop of oscillation), the output of the motor control timer goes into a high-impedance Note state.
Page 138 CHAPTER 5 CLOCK GENERATOR (a) Operation when oscillator is stopped (CLM.CLME bit = 1) If the oscillator is stopped when the CLME bit = 1, the CLMER signal is output from P16. Figure 5-2. When Oscillation of Main Clock Is Stopped Four internal oscillation clocks Oscillator (f Internal oscillation...
Page 139: Chapter 6 16-Bit Timer/Event Counter P (Tmp)
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Timer P (TMP) is a 16-bit timer/event counter. The V850ES/IE2 incorporates TMP0 to TMP3. Overview The TMPn of channels are outlined below (n = 0 to 3). Table 6-1. TMPn Overview Item TMP0...
Page 140: Configuration
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Configuration TMPn includes the following hardware. Table 6-3. Configuration of TMPn Item Configuration 16-bit counter × 1 Timer register Registers TMPn capture/compare registers 0, 1 (TPnCCR0, TPnCCR1) TMPn counter read buffer register (TPnCNT) CCR0 and CCR1 buffer registers Note 1 Note 1...
Page 141 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-1. TMP0 Block Diagram Internal bus TP0CNT INTTP0OV 16-bit counter Clear TOP00 /128 TOP01 CCR0 buffer CCR1 register buffer INTTP0CC0 register INTTP0CC1 TIP00 TP0CCR0 TIP01 TP0CCR1 Internal bus Remark : Peripheral clock Figure 6-2.
Page 142 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-3. TMP2 Block Diagram Internal bus TP2CNT INTTP2OV 16-bit counter Clear /128 TOP21 CCR0 buffer CCR1 register buffer INTTP2CC0 register INTTP2CC1 TIP20 TP2CCR0 TIP21 TP2CCR1 TOP2OFF Internal bus Remarks 1. f : Peripheral clock 2.
Page 143 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-4. TMP3 Block Diagram Internal bus TP3CNT INTTP3OV 16-bit counter Clear /128 TOP31 CCR0 buffer CCR1 register INTTP3CC0 buffer register INTTP3CC1 TP3CCR0 TP3CCR1 TOP3OFF Internal bus Remarks 1. f : Peripheral clock 2.
Page 144 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (3) CCR1 buffer register This is a 16-bit compare register that compares the count value of the 16-bit counter. When the TPnCCR1 register is used as a compare register, the value written to the TPnCCR1 register is transferred to the CCR1 buffer register.
Page 145: Registers
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Registers (1) TMPn control register 0 (TPnCTL0) The TPnCTL0 register is an 8-bit register that controls the operation of TMPn. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. The same value can always be written to the TPnCTL0 register by software.
Page 146 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (2) TMPn control register 1 (TPnCTL1) The TPnCTL1 register is an 8-bit register that controls the TMPn operation. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. (1/2) After reset: 00H Address: TP0CTL1 FFFFF641H, TP1CTL1 FFFFF661H,...
Page 147 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (2/2) Note TPnMD2 TPnMD1 TPnMD0 Timer mode selection Interval timer mode External event count mode External trigger pulse output mode One-shot pulse output mode PWM output mode Free-running timer mode Pulse width measurement mode Setting prohibited Note The settings that can be realized differ from one channel to another.
Page 148 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (3) TMPm I/O control register 0 (TPmIOC0) The TPmIOC0 register is an 8-bit register that controls the timer output (TOP00, TOPm1 pins). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 149 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (2/2) <R> Cautions 1. If the setting of the TPmIOC0 register is changed when TOP00 and TOPm1 are set in the output mode, the output of the pins change. Set the port in the input mode and make the port go into a high-impedance state, noting changes in the pin status.
Page 150 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (4) TMPk I/O control register 1 (TPkIOC1) The TPkIOC1 register is an 8-bit register that controls the valid edge for the capture trigger input signals (TIPk0, TIPk1 pins). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 151 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (5) TMPk I/O control register 2 (TPkIOC2) The TPkIOC2 register is an 8-bit register that controls the valid edge for the external event count input signal (TIPk0 pin) and external trigger input signal (TIPk0 pin). This register can be read or written in 8-bit or 1-bit units.
Page 152 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (6) TMPn option register 0 (TPnOPT0) The TPnOPT0 register is an 8-bit register that sets the capture/compare operation and detects overflow. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 153 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (7) TMPn capture/compare register 0 (TPnCCR0) The TP0CCR0 and TP2CCR0 registers are 16-bit registers that can be used as capture registers or compare registers depending on the mode. The TP1CCR0 and TP3CCR0 registers are 16-bit registers that can only be used as compare registers.
Page 154 (INTTPnCC0) is generated. If TOP00 pin output is enabled at this time, the output of the TOP00 pin is inverted (TOP10, TOP20, and TOP30 pins are not provided in the V850ES/IE2). When the TPnCCR0 register is used as a cycle register in the interval timer mode, external event count mode, external trigger pulse output mode, one-shot pulse output mode, or PWM output mode, the value of the 16-bit counter is cleared (0000H) if its count value matches the value of the CCR0 buffer register.
Page 155 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (8) TMPn capture/compare register 1 (TPnCCR1) The TP0CCR1 and TP2CCR1 registers are 16-bit registers that can be used as capture registers or compare registers depending on the mode. The TP1CCR1 and TP3CCR1 registers are 16-bit registers that can only be used as compare registers.
Page 156 (INTTPnCC1) is generated. If TOPm1 pin output is enabled at this time, the output of the TOPm1 pin is inverted (the TOP11 pin is not provided in the V850ES/IE2). The compare register is not cleared by the TPnCTL0.TPnCE bit = 0.
Page 157 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (9) TMPn counter read buffer register (TPnCNT) The TPnCNT register is a read buffer register that can read the count value of the 16-bit counter. If this register is read when the TPnCTL0.TPnCE bit = 1, the count value of the 16-bit counter can be read. This register is read-only, in 16-bit units.
Page 158: Timer Output Operations
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Timer Output Operations The following table shows the operations and output levels of the TOP00 and TOPm1 pins. Table 6-6. Timer Output Control in Each Mode Operation Mode TOPm1 Pin TOP00 Pin Interval timer mode PWM output External event count mode None...
Page 159: Operation
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Operation The functions of TMPn that can be realized differ from one channel to another. The functions of each channel are shown below. Table 6-8. TMP0 Specifications in Each Mode Operation TP0CTL1.TP0EST Bit TIP00 Pin (External Capture/Compare Compare Register...
Page 160 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Table 6-10. TMP2 Specifications in Each Mode Operation TP2CTL1.TP2EST Bit TIP20 Pin (External Capture/Compare Compare Register (Software Trigger Bit) Trigger Input) Register Setting Write Method Interval timer mode Invalid Invalid Compare only Anytime write Note 1 External event count mode Invalid...
Page 161 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Counter basic operation This section explains the basic operation of the 16-bit counter. For details, refer to the description of the operation in each mode. Remark n = 0 to 3 k = 0, 2 <R>...
Page 162 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (e) Interrupt operation TMPn generates the following three types of interrupt request signals. • INTTPnCC0 interrupt: This signal functions as a match interrupt request signal of the CCR0 buffer register and as a capture interrupt request signal to the TPnCCR0 register. •...
Page 163 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-6. Timing of Anytime Write TPnCE bit = 1 FFFFH 16-bit counter 0000H TPnCCR0 register CCR0 buffer register 0000H TPnCCR1 register CCR1 buffer register 0000H INTTPnCC0 signal INTTPnCC1 signal Remarks 1. D : Setting values of TPnCCR0 register : Setting values of TPnCCR1 register 2.
Page 164 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (b) Batch write In this mode, data is transferred all at once from the TPmCCR0 and TPmCCR1 registers to the CCR0 and CCR1 buffer registers during timer operation. This data is transferred upon a match between the value of the CCR0 buffer register and the value of the 16-bit counter.
Page 165 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-7. Flowchart of Basic Operation for Batch Write START Initial settings • Set values to TPmCCRa register • Timer operation enable (TPmCE bit = 1) → Transfer values of TPmCCRa register to CCRa buffer register TPmCCR0 register rewrite Batch write enable...
Page 166 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-8. Timing of Batch Write TPmCE bit = 1 FFFFH 16-bit counter 0000H TPmCCR0 register CCR0 buffer register 0000H Note 1 Note 1 Same value write TPmCCR1 register Note 2 Note 3 CCR1 buffer register 0000H Note 1...
Page 167: Interval Timer Mode (Tpnmd2 To Tpnmd0 Bits = 000)
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) 6.6.1 Interval timer mode (TPnMD2 to TPnMD0 bits = 000) In the interval timer mode, an interrupt request signal (INTTPnCC0) is generated at the interval set by the TPnCCR0 register if the TPnCTL0.TPnCE bit is set to 1. A PWM waveform with a duty factor of 50% whose half cycle is equal to the interval can be output from the TOP00 pin (TMP0 only).
Page 168 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) When the TPnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization with the count clock, and the counter starts counting. At this time, the output of the TOP00 pin is inverted. Additionally, the set value of the TPnCCR0 register is transferred to the CCR0 buffer register.
Page 169 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-11. Register Setting for Interval Timer Mode Operation (2/3) (c) TMPm I/O control register 0 (TPmIOC0) TPmOL1 TPmOE1 TP0OL0 TP0OE0 TPmIOC0 0: Disable TOP00 pin output 1: Enable TOP00 pin output Setting of TOP00 pin output level before count operation 0: Low level 1: High level...
Page 170 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-11. Register Setting for Interval Timer Mode Operation (3/3) (g) TMPn capture/compare register 1 (TPnCCR1) The TPnCCR1 register is not used in the interval timer mode. However, the set value of the TPnCCR1 register is transferred to the CCR1 buffer register.
Page 171 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Interval timer mode operation flow Figure 6-12. Software Processing Flow in Interval Timer Mode (1/2) FFFFH 16-bit counter 0000H TPnCE bit TPnCCR0 register TOP00 pin output INTTPnCC0 signal <1> <2> <1> Count operation start flow START Initial setting of these registers is performed Register initial setting...
Page 172 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-12. Software Processing Flow in Interval Timer Mode (2/2) <2> Count operation stop flow The counter is initialized and counting is stopped by clearing the TPnCE bit to 0. TPnCE bit = 0 The output level of the TOP00 pin is as specified by the TPmIOC0 register.
Page 173 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (b) Operation if TPnCCR0 register is set to FFFFH If the TPnCCR0 register is set to FFFFH, the 16-bit counter counts up to FFFFH. The counter is cleared to 0000H in synchronization with the next count-up timing. The INTTPnCC0 signal is generated and the output of the TOP00 pin is inverted.
Page 174 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Notes on rewriting TPnCCR0 register If the value of the TPnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. When an overflow may occur, stop counting and then change the set value. FFFFH 16-bit counter 0000H...
Page 175 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (d) Operation of TPnCCR1 register Figure 6-13. Configuration of TPnCCR1 Register TPnCCR1 register Output TOPm1 pin CCR1 buffer register controller Match signal INTTPnCC1 signal Clear Count clock Output 16-bit counter TOP00 pin selection controller Match signal INTTPnCC0 signal...
Page 176 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) When the TPnCCR1 register is set to the same value as the TPnCCR0 register, the INTTPnCC1 signal is generated at the same timing as the INTTPnCC0 signal and the TOPm1 pin output is inverted. In other words, a PWM waveform with a duty factor of 50% can be output from the TOPm1 pin.
Page 177 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) If the set value of the TPnCCR1 register is greater than the set value of the TPnCCR0 register, the count value of the 16-bit counter does not match the value of the TPnCCR1 register. Consequently, the INTTPnCC1 signal is not generated, nor is the output of the TOPm1 pin changed.
Page 178 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) <R> (3) Operation by external event count input (TIPk0) (a) Operation To count the 16-bit counter at the valid edge of external event count input (TIPk0) in the interval timer mode, clear the 16-bit counter from FFFFH to 0000H at the valid edge of the first external event count input after the TPkCE bit is set from 0 to 1.
Page 179: External Event Count Mode (Tpkmd2 To Tpkmd0 Bits = 001)
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) 6.6.2 External event count mode (TPkMD2 to TPkMD0 bits = 001) This mode is valid only in TMP0 and TMP2. In the external event count mode, the valid edge of the external event count input (TIPk0) is counted when the TPkCTL0.TPkCE bit is set to 1, and an interrupt request signal (INTTPkCC0) is generated each time the number of <R>...
Page 180 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-17. Basic Timing in External Event Count Mode FFFFH 16-bit counter − 1 16-bit counter 0000 0001 0000H External event count input TPkCE bit (TIPk0 pin input) TPkCCR0 register TPkCCR0 register INTTPkCC0 signal INTTPkCC0 signal External External...
Page 181 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) When the TPkCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H. The counter counts each time the valid edge of external event count input is detected. Additionally, the set value of the TPkCCR0 register is transferred to the CCR0 buffer register.
Page 182 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-18. Register Setting for Operation in External Event Count Mode (2/2) (f) TMPk capture/compare register 1 (TPkCCR1) The TPkCCR1 register is not used in the external event count mode. However, the set value of the TPkCCR1 register is transferred to the CCR1 buffer register.
Page 183 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (1) External event count mode operation flow Figure 6-19. Flow of Software Processing in External Event Count Mode FFFFH 16-bit counter 0000H TPkCE bit TPkCCR0 register INTTPkCC0 signal <1> <2> <1> Count operation start flow START Initial setting of these registers Register initial setting...
Page 184 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Operation timing in external event count mode Cautions 1. In the external event count mode, the TPkCCR0 and TPkCCR1 registers must not be cleared to 0000H. <R> 2. In the external event count mode, use of the timer output (TOP00, TOPk1) is disabled. If using timer output (TOPk1) with external event count input (TIPk0), set the interval timer mode, and enable the count clock operation with the external event count input (TPkCTL1.TPkEEE bit = 1) (see 6.6.1 (3) Operation by external event count input (TIPk0)).
Page 185 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (b) Notes on rewriting the TPkCCR0 register If the value of the TPkCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. When the overflow may occur, stop counting once and then change the set value. FFFFH 16-bit counter 0000H...
Page 186 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Operation of TPkCCR1 register Figure 6-20. Configuration of TPkCCR1 Register TPkCCR1 register CCR1 buffer register Match signal INTTPkCC1 signal Clear TIPk0 pin Edge (external event 16-bit counter detector count input) Match signal INTTPkCC0 signal TPkCE bit CCR0 buffer register...
Page 187 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) If the set value of the TPkCCR1 register is greater than the set value of the TPkCCR0 register, the INTTPkCC1 signal is not generated because the count value of the 16-bit counter and the value of the TPkCCR1 register do not match.
Page 188: External Trigger Pulse Output Mode (Tpmmd2 To Tpmmd0 Bits = 010)
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) 6.6.3 External trigger pulse output mode (TPmMD2 to TPmMD0 bits = 010) This mode is valid only in TMP0, TMP2, and TMP3 (software trigger only for TMP3). In the external trigger pulse output mode, 16-bit timer/event counter P waits for a trigger when the TPmCTL0.TPmCE bit is set to 1.
Page 189 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-24. Basic Timing in External Trigger Pulse Output Mode FFFFH 16-bit counter 0000H TPmCE bit External trigger input (TIPk0 pin input) TPmCCR0 register INTTPmCC0 signal TOP00 pin output <R> (only when using software trigger) TPmCCR1 register INTTPmCC1 signal...
Page 190 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-25. Setting of Registers in External Trigger Pulse Output Mode (1/2) (a) TMPm control register 0 (TPmCTL0) TPmCE TPmCKS2 TPmCKS1 TPmCKS0 TPmCTL0 <R> Select count clock 0: Stop counting 1: Enable counting (b) TMPm control register 1 (TPmCTL1) TPmEST TPkEEE...
Page 191 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-25. Setting of Registers in External Trigger Pulse Output Mode (2/2) (d) TMPk I/O control register 2 (TPkIOC2) TPkEES1 TPkEES0 TPkETS1 TPkETS0 <R> TPkIOC2 Select valid edge of external trigger input (TIPk0 pin) (e) TMPm counter read buffer register (TPmCNT) The value of the 16-bit counter can be read by reading the TPmCNT register.
Page 192 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Operation flow in external trigger pulse output mode Figure 6-26. Software Processing Flow in External Trigger Pulse Output Mode (1/2) FFFFH 16-bit counter 0000H TPmCE bit External trigger input (TIPk0 pin input) TPmCCR0 register CCR0 buffer register INTTPmCC0 signal...
Page 193 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-26. Software Processing Flow in External Trigger Pulse Output Mode (2/2) <1> Count operation start flow <3> TPmCCR0, TPmCCR1 register setting change flow Only writing of the TPmCCR1 START register must be performed when the set duty factor is changed.
Page 194 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (2) External trigger pulse output mode operation timing (a) Note on changing pulse width during operation To change the PWM waveform while the counter is operating, write the TPmCCR1 register last. Rewrite the TPmCCRa register after writing the TPmCCR1 register after the INTTPmCC0 signal is detected.
Page 195 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) In order to transfer data from the TPmCCRa register to the CCRa buffer register, the TPmCCR1 register must be written. To change both the cycle and active level width of the PWM waveform at this time, first set the cycle to the TPmCCR0 register and then set the active level width to the TPmCCR1 register.
Page 196 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TPmCCR1 register to 0000H. The 16-bit counter is cleared to 0000H and the INTTPmCC0 and INTTPmCC1 signals are generated at the next timing after a match between the count value of the 16-bit counter and the value of the CCR0 buffer register.
Page 197 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) To output a 100% waveform, set a value of (set value of TPmCCR0 register + 1) to the TPmCCR1 register. If the set value of the TPmCCR0 register is FFFFH, 100% output cannot be produced. Count clock −...
Page 198 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Conflict between trigger detection and match with CCR1 buffer register If the trigger is detected immediately after the INTTPmCC1 signal is generated, the 16-bit counter is immediately cleared to 0000H, the output signal of the TOPm1 pin is asserted, and the counter continues counting.
Page 199 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (d) Conflict between trigger detection and match with CCR0 buffer register If the trigger is detected immediately after the INTTPmCC0 signal is generated, the 16-bit counter is cleared to 0000H and continues counting up. Therefore, the active period of the TOPm1 pin is extended by time from generation of the INTTPmCC0 signal to trigger detection.
Page 200 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (e) Generation timing of compare match interrupt request signal (INTTPmCC1) The timing of generation of the INTTPmCC1 signal in the external trigger pulse output mode differs from the timing of INTTPmCC1 signals in other mode; the INTTPmCC1 signal is generated when the count value of the 16-bit counter matches the value of the TPmCCR1 register.
Page 201: One-Shot Pulse Output Mode (Tpmmd2 To Tpmmd0 Bits = 011)
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) 6.6.4 One-shot pulse output mode (TPmMD2 to TPmMD0 bits = 011) This mode is valid only in TMP0, TMP2, and TMP3 (software trigger only for TMP3). In the one-shot pulse output mode, 16-bit timer/event counter P waits for a trigger when the TPmCTL0.TPmCE bit is set to 1.
Page 202 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-28. Basic Timing in One-Shot Pulse Output Mode FFFFH 16-bit counter 0000H TPmCE bit External trigger input (TIPk0 pin input) TPmCCR0 register INTTPmCC0 signal TOP00 pin output (only when using software trigger) TPmCCR1 register INTTPmCC1 signal TOPm1 pin output...
Page 203 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-29. Setting of Registers in One-Shot Pulse Output Mode (1/2) (a) TMPm control register 0 (TPmCTL0) TPmCE TPmCKS2 TPmCKS1TPmCKS0 TPmCTL0 <R> Select count clock 0: Stop counting 1: Enable counting (b) TMPm control register 1 (TPmCTL1) TPmEST TPkEEE TPmMD2 TPmMD1 TPmMD0...
Page 204 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-29. Setting of Registers in One-Shot Pulse Output Mode (2/2) (d) TMPk I/O control register 2 (TPkIOC2) TPkEES1 TPkEES0 TPkETS1 TPkETS0 <R> TPkIOC2 Select valid edge of external trigger input (TIPk0 pin) (e) TMPm counter read buffer register (TPmCNT) The value of the 16-bit counter can be read by reading the TPmCNT register.
Page 205 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Operation flow in one-shot pulse output mode <R> Figure 6-30. Software Processing Flow in One-Shot Pulse Output Mode FFFFH 16-bit counter 0000H TPmCE bit External trigger input (TIPk0 pin input) TPmCCR0 register INTTPmCC0 signal TPmCCR1 register INTTPmCC1 signal...
Page 206 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Operation timing in one-shot pulse output mode (a) Note on rewriting TPmCCRa register If the value of the TPmCCRa register is rewritten to a smaller value during counting, the 16-bit counter may overflow.
Page 207 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (b) Generation timing of compare match interrupt request signal (INTTPmCC1) The generation timing of the INTTPmCC1 signal in the one-shot pulse output mode is different from INTTPmCC1 signals in other mode; the INTTPmCC1 signal is generated when the count value of the 16- bit counter matches the value of the TPmCCR1 register.
Page 208: Pwm Output Mode (Tpmmd2 To Tpmmd0 Bits = 100)
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) 6.6.5 PWM output mode (TPmMD2 to TPmMD0 bits = 100) This mode is valid only in TMP0, TMP2, and TMP3. In the PWM output mode, a PWM waveform is output from the TOPm1 pin when the TPmCTL0.TPmCE bit is set to In addition, a PWM waveform with a duty factor of 50% with the set value of the TPmCCR0 register + 1 as half its cycle is output from the TOP00 pin.
Page 209 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-32. Basic Timing in PWM Output Mode FFFFH 16-bit counter 0000H TPmCE bit TPmCCR0 register CCR0 buffer register INTTPmCC0 signal TOP00 pin output TPmCCR1 register CCR1 buffer register INTTPmCC1 signal TOPm1 pin output Active period Cycle Inactive period...
Page 210 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-33. Register Setting in PWM Output Mode (1/2) (a) TMPm control register 0 (TPmCTL0) TPmCE TPmCKS2 TPmCKS1 TPmCKS0 TPmCTL0 Note Select count clock 0: Stop counting 1: Enable counting Note The setting is invalid when the TPmCTL1.TPkEEE bit = 1. (b) TMPm control register 1 (TPmCTL1) TPmEST TPkEEE...
Page 211 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-33. Register Setting in PWM Output Mode (2/2) (d) TMPk I/O control register 2 (TPkIOC2) TPkEES1 TPkEES0 TPkETS1 TPkETS0 TPkIOC2 Select valid edge of external event count input (TIPk0 pin). (e) TMPm counter read buffer register (TPmCNT) The value of the 16-bit counter can be read by reading the TPmCNT register.
Page 212 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Operation flow in PWM output mode Figure 6-34. Software Processing Flow in PWM Output Mode (1/2) FFFFH 16-bit counter 0000H TPmCE bit TPmCCR0 register CCR0 buffer register INTTPmCC0 signal TOP00 pin output TPmCCR1 register CCR1 buffer register INTTPmCC1 signal...
Page 213 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-34. Software Processing Flow in PWM Output Mode (2/2) <1> Count operation start flow <3> TPmCCR0, TPmCCR1 register setting change flow (duty only) Only writing of the TPmCCR1 START register must be performed when the set duty factor is changed.
Page 214 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (2) PWM output mode operation timing (a) Changing pulse width during operation To change the PWM waveform while the counter is operating, write the TPmCCR1 register last. Rewrite the TPmCCRa register after writing the TPmCCR1 register after the INTTPmCC1 signal is detected.
Page 215 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TPmCCR1 register to 0000H. The 16-bit counter is cleared to 0000H and the INTTPmCC0 and INTTPmCC1 signals are generated at the next timing after a match between the count value of the 16-bit counter and the value of the CCR0 buffer register.
Page 216 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Generation timing of compare match interrupt request signal (INTTPmCC1) The timing of generation of the INTTPmCC1 signal in the PWM output mode differs from the timing of INTTPmCC1 signals in other modes; the INTTPmCC1 signal is generated when the count value of the 16- bit counter matches the value of the TPmCCR1 register.
Page 217: Free-Running Timer Mode (Tpnmd2 To Tpnmd0 Bits = 101)
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) 6.6.6 Free-running timer mode (TPnMD2 to TPnMD0 bits = 101) The compare function is valid for all of TMP0 to TMP3. The capture function is valid only for TMP0 and TMP2. In the free-running timer mode, 16-bit timer/event counter P starts counting when the TPnCTL0.TPnCE bit is set to 1.
Page 218 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) • Compare operation When the TPnCE bit is set to 1, 16-bit timer/event counter P starts counting, and the output signals of the TOP00 and TOPm1 pins are inverted. When the count value of the 16-bit counter later matches the set value of the TPnCCRa register, a compare match interrupt request signal (INTTPnCCa) is generated, and the output signals of the TOP00 and TOPm1 pins are inverted.
Page 219 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) • Capture operation When the TPkCE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIPka pin is detected, the count value of the 16-bit counter is stored in the TPkCCRa register, and a capture interrupt request signal (INTTPkCCa) is generated.
Page 220 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-38. Register Setting in Free-Running Timer Mode (1/2) (a) TMPn control register 0 (TPnCTL0) TPnCE TPnCKS2 TPnCKS1 TPnCKS0 TPnCTL0 Note Select count clock 0: Stop counting 1: Enable counting Note The setting is invalid when the TPkCTL1.TPkEEE bit = 1. (b) TMPn control register 1 (TPnCTL1) TP1SYE TPmEST...
Page 221 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-38. Register Setting in Free-Running Timer Mode (2/2) (e) TMPk I/O control register 2 (TPkIOC2) TPkEES1 TPkEES0 TPkETS1 TPkETS0 TPkIOC2 Select valid edge of external Note event count input (TIPk0 pin) Note Set the valid edge selection of the unused alternate external input signals to “No edge detection”. (f) TMPn option register 0 (TPnOPT0) TPkCCS1 TPkCCS0...
Page 222 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Operation flow in free-running timer mode (a) When using capture/compare register as compare register Figure 6-39. Software Processing Flow in Free-Running Timer Mode (Compare Function) (1/2) FFFFH 16-bit counter 0000H TPnCE bit TPnCCR0 register INTTPnCC0 signal TOP00 pin output...
Page 223 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-39. Software Processing Flow in Free-Running Timer Mode (Compare Function) (2/2) <1> Count operation start flow START Register initial setting Initial setting of these registers TPnCTL0 register is performed before setting the (TPnCKS0 to TPnCKS2 bits) TPnCE bit to 1.
Page 224 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (b) When using capture/compare register as capture register Figure 6-40. Software Processing Flow in Free-Running Timer Mode (Capture Function) (1/2) FFFFH 16-bit counter 0000H TPkCE bit TIPk0 pin input TPkCCR0 register 0000 0000 INTTPkCC0 signal TIPk1 pin input 0000...
Page 225 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-40. Software Processing Flow in Free-Running Timer Mode (Capture Function) (2/2) <1> Count operation start flow START Register initial setting Initial setting of these registers TPkCTL0 register is performed before setting the (TPkCKS0 to TPkCKS2 bits) TPkCE bit to 1.
Page 226 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Operation timing in free-running timer mode (a) Interval operation with compare register When 16-bit timer/event counter P is used as an interval timer with the TPnCCRa register used as a compare register, software processing is necessary for setting a comparison value to generate the next interrupt request signal each time the INTTPnCCa signal has been detected.
Page 227 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (b) Pulse width measurement with capture register When pulse width measurement is performed with the TPkCCRa register used as a capture register, software processing is necessary for reading the capture register each time the INTTPkCCa signal has been detected and for calculating an interval.
Page 228 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Processing of overflow when two capture registers are used Care must be exercised in processing the overflow flag when two capture registers are used. First, an example of incorrect processing is shown below. Example of incorrect processing when two capture registers are used FFFFH 16-bit counter...
Page 229 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (1/2) Example when two capture registers are used (using overflow interrupt) FFFFH 16-bit counter 0000H TPkCE bit INTTPkOV signal TPkOVF bit Note TPkOVF0 flag TIPk0 pin input TPkCCR0 register Note TPkOVF1 flag TIPk1 pin input TPkCCR1 register <1>...
Page 230 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (2/2) Example when two capture registers are used (without using overflow interrupt) FFFFH 16-bit counter 0000H TPkCE bit INTTPkOV signal TPkOVF bit Note TPkOVF0 flag TIPk0 pin input TPkCCR0 register Note TPkOVF1 flag TIPk1 pin input TPkCCR1 register <1>...
Page 231 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (d) Processing of overflow if capture trigger interval is long If the pulse width is greater than one cycle of the 16-bit counter, care must be exercised because an overflow may occur more than once from the first capture trigger to the next. First, an example of incorrect processing is shown below.
Page 232 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Example when capture trigger interval is long FFFFH 16-bit counter 0000H TPkCE bit TIPka pin input TPkCCRa register INTTPkOV signal TPkOVF bit Overflow 2H 0H Note counter 1 cycle of 16-bit counter Pulse width <1>...
Page 233 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (e) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TPnOVF bit to 0 with the CLR instruction after reading the TPnOVF bit when it is 1 and by writing 8-bit data (bit 0 is 0) to the TPnOPT0 register after reading the TPnOVF bit when it is 1.
Page 234: Pulse Width Measurement Mode (Tpkmd2 To Tpkmd0 Bits = 110)
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) 6.6.7 Pulse width measurement mode (TPkMD2 to TPkMD0 bits = 110) The mode is valid only in TMP0 and TMP2. In the pulse width measurement mode, 16-bit timer/event counter P starts counting when the TPkCTL0.TPkCE bit is set to 1.
Page 235 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-42. Basic Timing in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TPkCE bit TIPka pin input 0000H TPkCCRa register INTTPkCCa signal INTTPkOV signal Cleared to 0 by TPkOVF bit CLR instruction Remark k = 0, 2 a = 0, 1...
Page 236 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-43. Register Setting in Pulse Width Measurement Mode (1/2) (a) TMPk control register 0 (TPkCTL0) TPkCE TPkCKS2 TPkCKS1 TPkCKS0 TPkCTL0 <R> Select count clock 0: Stop counting 1: Enable counting (b) TMPk control register 1 (TPkCTL1) TPkEST TPkEEE TPkMD2 TPkMD1 TPkMD0...
Page 237 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-43. Register Setting in Pulse Width Measurement Mode (2/2) (d) TMPk option register 0 (TPkOPT0) TPkCCS1 TPkCCS0 TPkOVF TPkOPT0 Overflow flag (e) TMPk counter read buffer register (TPkCNT) The value of the 16-bit counter can be read by reading the TPkCNT register. (f) TMPk capture/compare registers 0 and 1 (TPkCCR0 and TPkCCR1) These registers store the count value of the 16-bit counter when the valid edge input to the TIPk0 and TIPk1 pins is detected.
Page 238 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Operation flow in pulse width measurement mode Figure 6-44. Software Processing Flow in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TPkCE bit TIPk0 pin input TPkCCR0 register 0000H 0000H INTTPkCC0 signal <1>...
Page 239 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Operation timing in pulse width measurement mode (a) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TPkOVF bit to 0 with the CLR instruction after reading the TPkOVF bit when it is 1 and by writing 8-bit data (bit 0 is 0) to the TPkOPT0 register after reading the TPkOVF bit when it is 1.
Page 240: Chapter 7 16-Bit Timer/Event Counter Q (Tmq)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Timer Q (TMQ) is a 16-bit timer/event counter. The V850ES/IE2 incorporates TMQ1 and TMQ0. Overview The TMQn channels are outlined below (n = 0, 1). Caution If P16 is used as the TOQ00 output pin or an output port, when an error (oscillator stop) is detected by the clock monitor, the CLMER signal (low level) is output from P16.
Page 241: Functions
CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Functions The TMQn functions that can be realized differ from one channel to another, as shown in the table below (n = 0, 1). Table 7-2. TMQn Functions Function TMQ0 TMQ1 × √ Note 1 6-phase PWM output √...
Page 242 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-1. TMQ0 Block Diagram Internal bus INTTQ0OV TQ0CNT See Figure 7-2 TMQ0 Output Pin Configuration /128 16-bit counter Clear Note 1 TOQ00 Note 2 TOQ01/TOQH01 EVTQ0 TOQ02 Note 2 CCR0 TOQ03/TOQH02 buffer Note 2 TOQH03 CCR1...
Page 243 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-2. TMQ0 Output Pin Configuration Note 1 TOQ00 Note 2 TOQ01/TOQH01 TIQ01 input TOQ02 Note 2 TOQ03/TOQH02 TIQ03 input Note 2 TOQH03 EVTQ0 input TOQH0OFF input Notes 1. If P16 is used as the TOQ00 output pin or an output port, when an error (oscillator stop) is detected by the clock monitor, the CLMER signal (low level) is output from P16.
Page 244 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-3. TMQ1 Block Diagram Internal bus TQ1CNT INTTQ1OV 16-bit counter Clear TOQ10 /128 CCR0 buffer CCR1 register buffer CCR2 register buffer CCR3 register INTTQ1CC0 buffer TQ1CCR0 INTTQ1CC1 register INTTQ1CC2 TQ1CCR1 TQ1CCR2 INTTQ1CC3 TQ1CCR3 Internal bus Remark...
Page 245 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (3) CCR1 buffer register This is a 16-bit compare register that compares the count value of the 16-bit counter. When the TQnCCR1 register is used as a compare register, the value written to the TQnCCR1 register is transferred to the CCR1 buffer register.
Page 246: Registers
CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Registers (1) TMQn control register 0 (TQnCTL0) The TQnCTL0 register is an 8-bit register that controls the TMQn operation. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. The same value can always be written to the TQnCTL0 register by software.
Page 247 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) After reset: 00H Address: TQ0CTL1 FFFFF5C1H, TQ1CTL1 FFFFF601H Note 1 Note 1 TQnCTL1 TQ0EST TQ0EEE TQnMD2 TQnMD1 TQnMD0 (n = 0, 1) Note 1 TQ0EST Software trigger control − Generate a valid signal for external trigger input. •...
Page 248 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (3) TMQn I/O control register 0 (TQnIOC0) The TQnIOC0 register is an 8-bit register that controls the timer output (TOQ00, TOQ01/TOQH01, TOQ02, TOQ03/TOQH02, TOQH03, and TOQ1T1 to TOQ1T3 pins). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 249 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2/2) Cautions 2. Rewrite the TQnOLm and TQnOEm bits when the TQnCTL0.TQnCE bit = 0. (The same value can be written when the TQnCE bit = 1.) If rewriting was mistakenly performed, clear (0) the TQnCE bit and then set the bits again.
Page 250 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (4) TMQ0 I/O control register 1 (TQ0IOC1) The TQ0IOC1 register is an 8-bit register that controls the valid edge for the capture trigger input signals (TIQ00 to TIQ03 pins). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 251 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (5) TMQ0 I/O control register 2 (TQ0IOC2) The TQ0IOC2 register is an 8-bit register that controls the valid edge for the external event count input signal (EVTQ0 pin). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 252 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (6) TMQn option register 0 (TQnOPT0) The TQnOPT0 register is an 8-bit register used to set the capture/compare operation and detect overflow. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 253 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (7) TMQn capture/compare register 0 (TQnCCR0) The TQ0CCR0 register is a 16-bit register that can be used as a capture register or a compare register depending on the mode. The TQ1CCR0 register is a 16-bit register that can only be used as a compare register.
Page 254 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (a) Function as compare register The TQnCCR0 register can be rewritten even when the TQnCTL0.TQnCE bit = 1. The set value of the TQnCCR0 register is transferred to the CCR0 buffer register. When the value of the 16-bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal (INTTQnCC0) is generated.
Page 255 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (8) TMQn capture/compare register 1 (TQnCCR1) The TQ0CCR1 register is a 16-bit register that can be used as a capture register or a compare register depending on the mode. The TQ1CCR1 register is a 16-bit register that can only be used as a compare register.
Page 256 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (a) Function as compare register The TQnCCR1 register can be rewritten even when the TQnCTL0.TQnCE bit = 1. The set value of the TQnCCR1 register is transferred to the CCR1 buffer register. When the value of the 16-bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTQnCC1) is generated.
Page 257 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (9) TMQn capture/compare register 2 (TQnCCR2) The TQ0CCR2 register is a 16-bit register that can be used as a capture register or a compare register depending on the mode. The TQ1CCR2 register is a 16-bit register that can only be used as a compare register.
Page 258 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (a) Function as compare register The TQnCCR2 register can be rewritten even when the TQnCTL0.TQnCE bit = 1. The set value of the TQnCCR2 register is transferred to the CCR2 buffer register. When the value of the 16-bit counter matches the value of the CCR2 buffer register, a compare match interrupt request signal (INTTQnCC2) is generated.
Page 259 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (10) TMQn capture/compare register 3 (TQnCCR3) The TQ0CCR3 register is a 16-bit register that can be used as a capture register or a compare register depending on the mode. The TQ1CCR3 register is a 16-bit register that can only be used as a compare register.
Page 260 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (a) Function as compare register The TQnCCR3 register can be rewritten even when the TQnCTL0.TQnCE bit = 1. The set value of the TQnCCR3 register is transferred to the CCR3 buffer register. When the value of the 16-bit counter matches the value of the CCR3 buffer register, a compare match interrupt request signal (INTTQnCC3) is generated.
Page 261 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (11) TMQn counter read buffer register (TQnCNT) The TQnCNT register is a read buffer register that can read the count value of the 16-bit counter. If this register is read when the TQnCTL0.TQnCE bit = 1, the count value of the 16-bit timer can be read. This register is read-only, in 16-bit units.
Page 262: Timer Output Operations
CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Timer Output Operations The following table shows the operations and output levels of the TOQ00 to TOQ03, TOQ10, and TOQH01 to TOQH03 pins. Table 7-8. Timer Output Control in Each Mode Operation Mode TOQn0 Pin TOQ01 to TOQ03 Pins TOQH01 to TOQH03 Pins...
Page 263: Operation
CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Operation The functions that can be realized differ between TMQ0 and TMQ1. The functions of each channel are shown below. Table 7-10. TMQ0 Specifications in Each Mode Operation TQ0CTL1.TQ0EST Bit Capture/Compare Register Compare Register Write (Software Trigger Bit) Setting Method...
Page 264 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) Counter basic operation This section explains the basic operation of the 16-bit counter. For details, refer to the description of the operation in each mode. Remark n = 0, 1 a = 0 to 3 (a) Counting start operation <R>...
Page 265 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (e) Interrupt operation TMQn generates the following five interrupt request signals. • INTTQnCC0 interrupt: This signal functions as a match interrupt request signal of the CCR0 buffer register and as a capture interrupt request signal to the TQnCCR0 register. •...
Page 266 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) Anytime write and batch write The TQnCCR0 to TQnCCR3 registers can be rewritten in the TMQn during timer operation (TQnCTL0.TQnCE bit = 1), but the write method (anytime write, batch write) of the CCR0 to CCR3 buffer registers differs depending on the mode.
Page 267 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-5. Timing of Anytime Write TQnCE bit = 1 FFFFH 16-bit counter 0000H TQnCCR0 register CCR0 buffer 0000H register INTTQnCC0 signal TQnCCR1 register CCR1 buffer 0000H register INTTQnCC1 signal TQnCCR2 register CCR2 buffer 0000H register INTTQnCC2...
Page 268 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (b) Batch write In this mode, data is transferred all at once from the TQ0CCR0 to TQ0CCR3 registers to the CCR0 to CCR3 buffer registers during timer operation. This data is transferred upon a match between the value of the CCR0 buffer register and the value of the 16-bit counter.
Page 269 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-6. Flowchart of Basic Operation for Batch Write START Initial settings • Set values to TQ0CCRa register • Timer operation enable (TQ0CE bit = 1) → Transfer of values of TQ0CCRa register to CCRa buffer register TQ0CCRy register rewrite Batch write enable...
Page 270 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-7. Timing of Batch Write TQ0CE bit = 1 FFFFH 16-bit counter 0000H TQ0CCR0 register CCR0 buffer 0000H register Note 1 Note 1 Same value write TQ0CCR1 Note 2 Note 3 register CCR1 buffer 0000H register...
Page 271: Interval Timer Mode (Tqnmd2 To Tqnmd0 Bits = 000)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) 7.6.1 Interval timer mode (TQnMD2 to TQnMD0 bits = 000) In the interval timer mode, an interrupt request signal (INTTQnCC0) is generated at the interval set by the TQnCCR0 register if the TQnCTL0.TQnCE bit is set to 1. A PWM waveform with a duty factor of 50% whose half cycle is equal to the interval can be output from the TOQn0 pin.
Page 272 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) When the TQnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization with the count clock, and the counter starts counting. At this time, the output of the TOQn0 pin is inverted. Additionally, the set value of the TQnCCR0 register is transferred to the CCR0 buffer register.
Page 273 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-10. Register Setting for Interval Timer Mode Operation (2/3) (c) TMQn I/O control register 0 (TQnIOC0) TQ0OL3 TQ0OE3 TQ0OL2 TQ0OE2 TQ0OL1 TQ0OE1 TQnOL0 TQnOE0 TQnIOC0 0: Disable TOQn0 pin output 1: Enable TOQn0 pin output Setting of TOQn0 pin output level before count operation 0: Low level...
Page 274 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-10. Register Setting for Interval Timer Mode Operation (3/3) (g) TMQn capture/compare registers 1 to 3 (TQnCCR1 to TQnCCR3) The TQnCCR1 to TQnCCR3 registers are not used in the interval timer mode, but the set values of the TQnCCR1 to TQnCCR3 registers are transferred to the CCR1 to CCR3 buffer registers.
Page 275 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) Interval timer mode operation flow Figure 7-11. Software Processing Flow in Interval Timer Mode FFFFH 16-bit counter 0000H TQnCE bit TQnCCR0 register TOQn0 pin output INTTQnCC0 signal <1> <2> <1> Count operation start flow START Initial setting of these registers is performed Register initial setting...
Page 276 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) Interval timer mode operation timing (a) Operation if TQnCCR0 register is set to 0000H If the TQnCCR0 register is set to 0000H, the INTTQnCC0 signal is generated at each count clock, and the output of the TOQn0 pin is inverted.
Page 277 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (b) Operation if TQnCCR0 register is set to FFFFH If the TQnCCR0 register is set to FFFFH, the 16-bit counter counts up to FFFFH. The counter is cleared to 0000H in synchronization with the next count-up timing. The INTTQnCC0 signal is generated and the output of the TOQn0 pin is inverted.
Page 278 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (c) Notes on rewriting TQnCCR0 register If the value of the TQnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. When the overflow may occur, stop counting once and then change the set value. FFFFH 16-bit counter 0000H...
Page 279 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (d) Operation of TQnCCR1 to TQnCCR3 registers Figure 7-12. Configuration of TQnCCR1 to TQnCCR3 Registers TQnCCR1 register CCR1 buffer Output TOQ01 pin register controller Match signal INTTQnCC1 signal TQnCCR2 register Output CCR2 buffer TOQ02 pin controller register...
Page 280 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) <R> When the TQnCCRb register is set to the same value as that of the TQnCCR0 register, the INTTQnCCb signal is generated at the same timing as the INTTQnCC0 signal is generated, and the TOQ0b pin output is inverted.
Page 281 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) If the set value of the TQnCCRb register is greater than the set value of the TQnCCR0 register, the count value of the 16-bit counter does not match the value of the TQnCCRb register. Consequently, the INTTQnCCb signal is not generated, nor is the output of the TOQ0b pin changed.
Page 282 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) <R> (3) Operation by external event count input (EVTQ0) (a) Operation To count the 16-bit counter at the valid edge of external event count input (EVTQ0) in the interval timer mode, clear the 16-bit counter from FFFFH to 0000H at the valid edge of the first external event count input after the TQ0CE bit is set from 0 to 1.
Page 283: External Event Count Mode (Tq0Md2 To Tq0Md0 Bits = 001)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) 7.6.2 External event count mode (TQ0MD2 to TQ0MD0 bits = 001) This mode is valid only in TMQ0. In the external event count mode, the valid edge of the external event count input (EVTQ0) is counted when the TQ0CTL0.TQ0CE bit is set to 1, and an interrupt request signal (INTTQ0CC0) is generated each time the specified number of edges set by the TQ0CCR0 register have been counted.
Page 284 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-16. Basic Timing in External Event Count Mode FFFFH 16-bit counter 16-bit counter 0000 0001 0000H External event count input TQ0CE bit (EVTQ0 pin input) TQ0CCR0 register TQ0CCR0 register INTTQ0CC0 signal INTTQ0CC0 signal External External External...
Page 285 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) When the TQ0CE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H. The counter counts each time the valid edge of external event count input is detected. Additionally, the set value of the TQ0CCR0 register is transferred to the CCR0 buffer register.
Page 286 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-17. Register Setting for Operation in External Event Count Mode (2/2) (f) TMQ0 capture/compare registers 1 to 3 (TQ0CCR1 to TQ0CCR3) The TQ0CCR1 to TQ0CCR3 registers are not used in the external event count mode. However, the set values of the TQ0CCR1 to TQ0CCR3 registers are transferred to the CCR1 to CCR3 buffer registers.
Page 287 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) External event count mode operation flow Figure 7-18. Flow of Software Processing in External Event Count Mode FFFFH 16-bit counter 0000H TQ0CE bit TQ0CCR0 register INTTQ0CC0 signal <1> <2> <1> Count operation start flow START Register initial setting Initial setting of these registers...
Page 288 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) Operation timing in external event count mode Cautions 1. In the external event count mode, the TQ0CCR0 to TQ0CCR3 registers must not be cleared to 0000H. <R> 2. In the external event count mode, use of the timer output (TOQ00 to TOQ03) is disabled. If using timer output (TOQ00 to TOQ03) with external event count input (EVTQ0), set the interval timer mode, and enable the count clock operation with the external event count input (TQ0CTL1.TQ0EEE bit = 1) (see 7.6.1 (3) Operation by external event count input...
Page 289 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (b) Notes on rewriting the TQ0CCR0 register If the value of the TQ0CCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. When the overflow may occur, stop counting once and then change the set value. FFFFH 16-bit counter 0000H...
Page 290 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (c) Operation of TQ0CCR1 to TQ0CCR3 registers Figure 7-19. Configuration of TQ0CCR1 to TQ0CCR3 Registers TQ0CCR1 register CCR1 buffer register Match signal INTTQ0CC1 signal TQ0CCR2 register CCR2 buffer register Match signal INTTQ0CC2 signal TQ0CCR3 register CCR3 buffer...
Page 291 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) If the set value of the TQ0CCRb register is smaller than the set value of the TQ0CCR0 register, the INTTQ0CCb signal is generated once per cycle. ≥ D Figure 7-20. Timing Chart When D FFFFH 16-bit counter 0000H...
Page 292 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) If the set value of the TQ0CCRb register is greater than the set value of the TQ0CCR0 register, the INTTQ0CCb signal is not generated because the count value of the 16-bit counter and the value of the TQ0CCRb register do not match.
Page 293: External Trigger Pulse Output Mode (Tq0Md2 To Tq0Md0 Bits = 010)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) 7.6.3 External trigger pulse output mode (TQ0MD2 to TQ0MD0 bits = 010) This mode is valid only in TMQ0. In the external trigger pulse output mode, 16-bit timer/event counter Q waits for a trigger when the TQ0CTL0.TQ0CE bit is set to 1.
Page 294 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-23. Basic Timing in External Trigger Pulse Output Mode FFFFH 16-bit counter 0000H TQ0CE bit Software trigger TQ0CCR0 register INTTQ0CC0 signal <R> TOQ00 pin output TQ0CCR1 register INTTQ0CC1 signal TOQ01 pin output Active level Active level Active level...
Page 295 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) 16-bit timer/event counter Q waits for a trigger when the TQ0CE bit is set to 1. When the trigger is generated, the 16-bit counter is cleared from FFFFH to 0000H, starts counting at the same time, and outputs a PWM waveform from the TOQ0b pin.
Page 296 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-24. Setting of Registers in External Trigger Pulse Output Mode (2/3) (b) TMQ0 control register 1 (TQ0CTL1) TQ0EST TQ0EEE TQ0MD2 TQ0MD1 TQ0MD0 TQ0CTL1 0, 1, 0: External trigger pulse output mode 0: Operate on count clock selected by TQ0CKS0 to TQ0CKS2 bits 1: Count with external...
Page 297 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-24. Setting of Registers in External Trigger Pulse Output Mode (3/3) (d) TMQ0 I/O control register 2 (TQ0IOC2) TQ0EES1 TQ0EES0 TQ0IOC2 Select valid edge of external event count input (EVTQ0 pin) (e) TMQ0 counter read buffer register (TQ0CNT) The value of the 16-bit counter can be read by reading the TQ0CNT register.
Page 298 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) Operation flow in external trigger pulse output mode Figure 7-25. Software Processing Flow in External Trigger Pulse Output Mode (1/2) FFFFH 16-bit counter 0000H TQ0CE bit Software trigger TQ0CCR0 register CCR0 buffer register INTTQ0CC0 signal TOQ00 pin output TQ0CCR1 register...
Page 299 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-25. Software Processing Flow in External Trigger Pulse Output Mode (2/2) <1> Count operation start flow <4> TQ0CCR1 to TQ0CCR3 register setting change flow Writing of the TQ0CCR1 START Setting of TQ0CCR2, register must be performed TQ0CCR3 registers when the set duty factor is only...
Page 300 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) External trigger pulse output mode operation timing (a) Note on changing pulse width during operation To change the PWM waveform while the counter is operating, write the TQ0CCR1 register last. Rewrite the TQ0CCRb register after writing the TQ0CCR1 register after the INTTQ0CC0 signal is detected. Remark b = 1 to 3 FFFFH...
Page 301 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) In order to transfer data from the TQ0CCRa register to the CCRa buffer register, the TQ0CCR1 register must be written. To change both the cycle and active level width of the PWM waveform at this time, first set the cycle to the TQ0CCR0 register, set the active level width to the TQ0CCR2 and TQ0CCR3 registers, and then set an active level to the TQ0CCR1 register.
Page 302 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TQ0CCRb register to 0000H. The 16-bit counter is cleared to 0000H and the INTTQ0CC0 and INTTQ0CCb signals are generated at the next timing after a match between the count value of the 16-bit counter and the value of the CCR0 buffer register.
Page 303 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) To output a 100% waveform, set a value of (set value of TQ0CCR0 register + 1) to the TQ0CCRb register. If the set value of the TQ0CCR0 register is FFFFH, 100% output cannot be produced. Count clock −...
Page 304 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (c) Conflict between trigger detection and match with CCRb buffer register If the trigger is detected immediately after the INTTQ0CCb signal is generated, the 16-bit counter is immediately cleared to 0000H, the output signal of the TOQ0b pin is asserted, and the counter continues counting.
Page 305 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (d) Conflict between trigger detection and match with CCR0 buffer register If the trigger is detected immediately after the INTTQ0CC0 signal is generated, the 16-bit counter is cleared to 0000H and continues counting up. Therefore, the active period of the TOQ0b pin is extended by time from generation of the INTTQ0CC0 signal to trigger detection.
Page 306 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (e) Generation timing of compare match interrupt request signal (INTTQ0CCb) The timing of generation of the INTTQ0CCb signal in the external trigger pulse output mode differs from the timing of INTTQ0CCb signals in other mode; the INTTQ0CCb signal is generated when the count value of the 16-bit counter matches the value of the CCRb buffer register.
Page 307: One-Shot Pulse Output Mode (Tq0Md2 To Tq0Md0 Bits = 011)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) 7.6.4 One-shot pulse output mode (TQ0MD2 to TQ0MD0 bits = 011) This mode is valid only in TMQ0. In the one-shot pulse output mode, 16-bit timer/event counter Q waits for a trigger when the TQ0CTL0.TQ0CE bit is set to 1.
Page 308 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-27. Basic Timing in One-Shot Pulse Output Mode FFFFH 16-bit counter 0000H TQ0CE bit Software trigger TQ0CCR0 register INTTQ0CC0 signal TOQ00 pin output TQ0CCR1 register INTTQ0CC1 signal TOQ01 pin output Delay Active Delay Active Delay...
Page 309 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) When the TQ0CE bit is set to 1, 16-bit timer/event counter Q waits for a trigger. When the trigger is generated, the 16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a one-shot pulse from the TOQ0b pin. After the one-shot pulse is output, the 16-bit counter is cleared to 0000H, stops counting, and waits for a trigger.
Page 310 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-28. Register Setting in One-Shot Pulse Output Mode (2/3) (c) TMQ0 I/O control register 0 (TQ0IOC0) TQ0OL3 TQ0OE3 TQ0OL2 TQ0OE2 TQ0OL1 TQ0OE1 TQ0OL0 TQ0OE0 TQ0IOC0 0: Disable TOQ00 pin output 1: Enable TOQ00 pin output Setting of TOQ00 pin output level in external trigger waiting state 0: Low level...
Page 311 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-28. Register Setting in One-Shot Pulse Output Mode (3/3) (f) TMQ0 capture/compare registers 0 to 3 (TQ0CCR0 to TQ0CCR3) If D is set to the TQ0CCR0 register and D to the TQ0CCRb register, the active level width and output delay period of the one-shot pulse are as follows.
Page 312 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) Operation flow in one-shot pulse output mode <R> Figure 7-29. Software Processing Flow in One-Shot Pulse Output Mode (1/2) FFFFH 16-bit counter 0000H TQ0CE bit Software trigger TQ0CCR0 register INTTQ0CC0 signal TOQ00 pin output TQ0CCR1 register INTTQ0CC1 signal TOQ01 pin output...
Page 313 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) <R> Figure 7-29. Software Processing Flow in One-Shot Pulse Output Mode (2/2) <3> Count operation stop flow <1> Count operation start flow Count operation is stopped. TQ0CE bit = 0 START STOP Initial setting of these Register initial setting registers is performed TQ0CTL0 register...
Page 314 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) Operation timing in one-shot pulse output mode (a) Note on rewriting TQ0CCRa register If the value of the TQ0CCRa register is rewritten to a smaller value during counting, the 16-bit counter may overflow.
Page 315 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (b) Generation timing of compare match interrupt request signal (INTTQ0CCb) The generation timing of the INTTQ0CCb signal in the one-shot pulse output mode is different from INTTQ0CCb signals in other mode; the INTTQ0CCb signal is generated when the count value of the 16-bit counter matches the value of the TQ0CCRb register.
Page 316: Pwm Output Mode (Tq0Md2 To Tq0Md0 Bits = 100)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) 7.6.5 PWM output mode (TQ0MD2 to TQ0MD0 bits = 100) This mode is valid only in TMQ0. In the PWM output mode, a PWM waveform is output from the TOQ01 to TOQ03 (TOQH01 to TOQH03) pins when the TQ0CTL0.TQ0CE bit is set to 1.
Page 317 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-31. Basic Timing in PWM Output Mode FFFFH 16-bit counter 0000H TQ0CE bit TQ0CCR0 register INTTQ0CC0 signal TOQ00 pin output TQ0CCR1 register INTTQ0CC1 signal TOQ01 (TOQH01) pin output Active Active Active Active level width level width level width...
Page 318 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) When the TQ0CE bit is set to 1, the 16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs PWM waveform from the TOQ0b pin (TOQH0b). The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows. Active level width = (Set value of TQ0CCRb register) ×...
Page 319 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-32. Register Setting in PWM Output Mode (2/3) (c) TMQ0 I/O control register 0 (TQ0IOC0) TQ0OL3 TQ0OE3 TQ0OL2 TQ0OE2 TQ0OL1 TQ0OE1 TQ0OL0 TQ0OE0 TQ0IOC0 0: Disable TOQ00 pin output 1: Enable TOQ00 pin output Setting of TOQ00 pin output level before count operation 0: Low level...
Page 320 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-32. Register Setting in PWM Output Mode (3/3) (f) TMQ0 capture/compare registers 0 to 3 (TQ0CCR0 to TQ0CCR3) If D is set to the TQ0CCR0 register and D to the TQ0CCRb register, the cycle and active level of the PWM waveform are as follows.
Page 321 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) Operation flow in PWM output mode Figure 7-33. Software Processing Flow in PWM Output Mode (1/2) FFFFH 16-bit counter 0000H TQ0CE bit TQ0CCR0 register CCR0 buffer register INTTQ0CC0 signal TOQ00 pin output TQ0CCR1 register CCR1 buffer register INTTQ0CC1 signal...
Page 322 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-33. Software Processing Flow in PWM Output Mode (2/2) <1> Count operation start flow <4> TQ0CCR1 to TQ0CCR3 register setting change flow Writing of the TQ0CCR1 START Setting of TQ0CCR2, register must be performed TQ0CCR3 registers when the set duty factor is only changed after writing the...
Page 323 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) PWM output mode operation timing (a) Changing pulse width during operation To change the PWM waveform while the counter is operating, write the TQ0CCR1 register last. Rewrite the TQ0CCRa register after writing the TQ0CCR1 register after the INTTQ0CC1 signal is detected. FFFFH 16-bit counter 0000H...
Page 324 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) To transfer data from the TQ0CCRa register to the CCRa buffer register, the TQ0CCR1 register must be written. To change both the cycle and active level of the PWM waveform at this time, first set the cycle to the TQ0CCR0 register, set the active level width to the TQ0CCR2 and TQ0CCR3 registers, and then set an active level width to the TQ0CCR1 register.
Page 325 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TQ0CCRb register to 0000H. The 16-bit counter is cleared to 0000H and the INTTQ0CC0 and INTTQ0CCb signals are generated at the next timing after a match between the count value of the 16-bit counter and the value of the CCR0 buffer register.
Page 326 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (c) Generation timing of compare match interrupt request signal (INTTQ0CCb) The timing of generation of the INTTQ0CCb signal in the PWM output mode differs from the timing of INTTQ0CCb signals in other mode; the INTTQ0CCb signal is generated when the count value of the 16-bit counter matches the value of the TQ0CCRb register.
Page 327: Free-Running Timer Mode (Tqnmd2 To Tqnmd0 Bits = 101)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) 7.6.6 Free-running timer mode (TQnMD2 to TQnMD0 bits = 101) The compare function is valid in both TMQ0 and TMQ1. The capture function is valid in TMQ0 only. In the free-running timer mode, 16-bit timer/event counter Q starts counting when the TQnCTL0.TQnCE bit is set to 1.
Page 328 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) • Compare operation When the TQnCE bit is set to 1, 16-bit timer/event counter Q starts counting, and the output signals of the TOQ00 to TOQ03 and TOQ10 pins are inverted. When the count value of the 16-bit counter later matches the set value of the TQnCCRa register, a compare match interrupt request signal (INTTQnCCa) is generated, and the output signals of the TOQ00 to TOQ03 and TOQ10 pins are inverted.
Page 329 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) • Capture operation When the TQ0CE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIQ0a pin is detected, the count value of the 16-bit counter is stored in the TQ0CCRa register, and a capture interrupt request signal (INTTQ0CCa) is generated.
Page 330 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-37. Register Setting in Free-Running Timer Mode (1/3) (a) TMQn control register 0 (TQnCTL0) TQnCE TQnCKS2 TQnCKS1 TQnCKS0 TQnCTL0 Note Select count clock 0: Stop counting 1: Enable counting Note The setting is invalid when the TQ0CTL1.TQ0EEE bit = 1. (b) TMQn control register 1 (TQnCTL1) TQ0EST TQ0EEE...
Page 331 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-37. Register Setting in Free-Running Timer Mode (2/3) (c) TMQn I/O control register 0 (TQnIOC0) TQ0OL3 TQ0OE3 TQ0OL2 TQ0OE2 TQ0OL1 TQ0OE1 TQnOL0 TQnOE0 TQnIOC0 0: Disable TOQn0 pin output 1: Enable TOQn0 pin output Setting of TOQn0 pin output level before count operation 0: Low level...
Page 332 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-37. Register Setting in Free-Running Timer Mode (3/3) (e) TMQ0 I/O control register 2 (TQ0IOC2) TQ0EES1 TQ0EES0 TQ0IOC2 Select valid edge of external event count input (EVTQ0 pin) (f) TMQn option register 0 (TQnOPT0) TQ0CCS1 TQ0CCS0 TQ1CMS TQ1CUF TQnOVF...
Page 333 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) Operation flow in free-running timer mode (a) When using capture/compare register as compare register Figure 7-38. Software Processing Flow in Free-Running Timer Mode (Compare Function) (1/2) FFFFH 16-bit counter 0000H TQnCE bit TQnCCR0 register INTTQnCC0 signal TOQn0 pin output...
Page 334 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-38. Software Processing Flow in Free-Running Timer Mode (Compare Function) (2/2) <1> Count operation start flow START Initial setting of these registers Register initial setting is performed before setting the TQnCTL0 register TQnCE bit to 1.
Page 335 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (b) When using capture/compare register as capture register Figure 7-39. Software Processing Flow in Free-Running Timer Mode (Capture Function) (1/2) FFFFH 16-bit counter 0000H TQ0CE bit TIQ00 pin input TQ0CCR0 register 0000 0000 INTTQ0CC0 signal TIQ01 pin input TQ0CCR1 register...
Page 336 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-39. Software Processing Flow in Free-Running Timer Mode (Capture Function) (2/2) <1> Count operation start flow START Register initial setting Initial setting of these registers TQ0CTL0 register is performed before setting the (TQ0CKS0 to TQ0CKS2 bits) TQ0CE bit to 1.
Page 337 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) Operation timing in free-running timer mode (a) Interval operation with compare register When 16-bit timer/event counter Q is used as an interval timer with the TQnCCRa register used as a compare register, software processing is necessary for setting a comparison value to generate the next interrupt request signal each time the INTTQnCCa signal has been detected.
Page 338 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) When performing an interval operation in the free-running timer mode, two intervals can be set with one channel. To perform the interval operation, the value of the corresponding TQnCCRa register must be re-set in the interrupt servicing that is executed when the INTTQnCCa signal is detected.
Page 339 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (b) Pulse width measurement with capture register When pulse width measurement is performed with the TQ0CCRa register used as a capture register, software processing is necessary for reading the capture register each time the INTTQ0CCa signal has been detected and for calculating an interval.
Page 340 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) When executing pulse width measurement in the free-running timer mode, four pulse widths can be measured with one channel. To measure a pulse width, the pulse width can be calculated by reading the value of the TQ0CCRa register in synchronization with the INTTQ0CCa signal, and calculating the difference between the read value and the previously read value.
Page 341 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (c) Processing of overflow when two capture registers are used Care must be exercised in processing the overflow flag when two capture registers are used. First, an example of incorrect processing is shown below. Example of incorrect processing when two capture registers are used FFFFH 16-bit counter...
Page 342 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1/2) Example when two capture registers are used (using overflow interrupt) FFFFH 16-bit counter 0000H TQ0CE bit INTTQ0OV signal TQ0OVF bit Note TQ0OVF0 flag TIQ00 pin input TQ0CCR0 register Note TQ0OVF1 flag TIQ01 pin input TQ0CCR1 register <1>...
Page 343 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2/2) Example when two capture registers are used (without using overflow interrupt) FFFFH 16-bit counter 0000H TQ0CE bit INTTQ0OV signal TQ0OVF bit Note TQ0OVF0 flag TIQ00 pin input TQ0CCR0 register Note TQ0OVF1 flag TIQ01 pin input TQ0CCR1 register <1>...
Page 344 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (d) Processing of overflow if capture trigger interval is long If the pulse width is greater than one cycle of the 16-bit counter, care must be exercised because an overflow may occur more than once from the first capture trigger to the next. First, an example of incorrect processing is shown below.
Page 345 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Example when capture trigger interval is long FFFFH 16-bit counter 0000H TQ0CE bit TIQ0a pin input TQ0CCRa register INTTQ0OV signal TQ0OVF bit Overflow 2H 0H Note counter 1 cycle of 16-bit counter Pulse width <1>...
Page 346 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (3) Note on capture operation If the capture operation is used and if a slow clock is selected as the count clock, FFFFH, not 0000H, may be captured to the TQ0CCRa register if the capture trigger is input immediately after the TQ0CTL0.TQ0CE bit is set to 1 (a = 0 to 3).
Page 347: Pulse Width Measurement Mode (Tq0Md2 To Tq0Md0 Bits = 110)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) 7.6.7 Pulse width measurement mode (TQ0MD2 to TQ0MD0 bits = 110) In the pulse width measurement mode, 16-bit timer/event counter Q starts counting when the TQ0CTL0.TQ0CE bit is set to 1. Each time the valid edge input to the TIQ0a pin has been detected, the count value of the 16-bit counter is stored in the TQ0CCRa register, and the 16-bit counter is cleared to 0000H.
Page 348 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-41. Basic Timing in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TQ0CE bit TIQ0a pin input 0000H TQ0CCRa register INTTQ0CCa signal INTTQ0OV signal Cleared to 0 by TQ0OVF bit CLR instruction Remark a = 0 to 3 When the TQ0CE bit is set to 1, the 16-bit counter starts counting.
Page 349 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-42. Register Setting in Pulse Width Measurement Mode (1/2) (a) TMQ0 control register 0 (TQ0CTL0) TQ0CE TQ0CKS2 TQ0CKS1 TQ0CKS0 TQ0CTL0 Note Select count clock 0: Stop counting 1: Enable counting Note Setting is invalid when the TQ0CTL1.TQ0EEE bit = 1. (b) TMQ0 control register 1 (TQ0CTL1) TQ0EST TQ0EEE...
Page 350 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-42. Register Setting in Pulse Width Measurement Mode (2/2) (e) TMQ0 option register 0 (TQ0OPT0) TQ0CCS3 TQ0CCS2 TQ0CCS1 TQ0CCS0 TQ0OVF TQ0OPT0 Overflow flag (f) TMQ0 counter read buffer register (TQ0CNT) The value of the 16-bit counter can be read by reading the TQ0CNT register. (g) TMQ0 capture/compare registers 0 to 3 (TQ0CCR0 to TQ0CCR3) These registers store the count value of the 16-bit counter when the valid edge input to the TIQ0a pin is detected.
Page 351 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) Operation flow in pulse width measurement mode Figure 7-43. Software Processing Flow in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TQ0CE bit TIQ00 pin input 0000H 0000H TQ0CCR0 register INTTQ0CC0 signal <1>...
Page 352 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) Operation timing in pulse width measurement mode (a) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TQ0OVF bit to 0 with the CLR instruction after reading the TQ0OVF bit when it is 1 and by writing 8-bit data (bit 0 is 0) to the TQ0OPT0 register after reading the TQ0OVF bit when it is 1.
Page 353: Chapter 8 16-Bit Interval Timer M (Tmm)
CHAPTER 8 16-BIT INTERVAL TIMER M (TMM) Overview • Interval function • 8 clocks selectable • 16-bit counter × 1 (The 16-bit counter cannot be read during timer count operation.) • Compare register × 1 (The compare register cannot be written during timer counter operation.) •...
Page 354: Configuration
CHAPTER 8 16-BIT INTERVAL TIMER M (TMM) Configuration TMM0 includes the following hardware. Table 8-1. Configuration of TMM0 Item Configuration Timer register 16-bit counter Register TMM0 compare register 0 (TM0CMP0) Control register TMM0 control register 0 (TM0CTL0) Figure 8-1. Block Diagram of TMM0 Internal bus TM0CTL0 TM0CE TM0CKS2 TM0CKS1TM0CKS0...
Page 355: Control Register
CHAPTER 8 16-BIT INTERVAL TIMER M (TMM) Control Register (1) TMM0 control register 0 (TM0CTL0) The TM0CTL0 register is an 8-bit register that controls the TMM0 operation. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. The same value can always be written to the TM0CTL0 register by software.
Page 356: Operation
CHAPTER 8 16-BIT INTERVAL TIMER M (TMM) Operation 8.4.1 Interval timer mode In the interval timer mode, an interrupt request signal (INTTM0EQ0) is generated at the interval set by the TM0CMP0 register if the TM0CTL0.TM0CE bit is set to 1. Figure 8-2.
Page 357 CHAPTER 8 16-BIT INTERVAL TIMER M (TMM) When the TM0CE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization with the count clock, and the counter starts counting. When the count value of the 16-bit counter matches the value of the TM0CMP0 register, the 16-bit counter is cleared to 0000H, and a compare match interrupt request signal (INTTM0EQ0) is generated.
Page 358 CHAPTER 8 16-BIT INTERVAL TIMER M (TMM) (1) Interval timer mode operation flow Figure 8-5. Software Processing Flow in Interval Timer Mode FFFFH 16-bit counter 0000H TM0CE bit TM0CMP0 register INTTM0EQ0 signal <1> <2> <1> Count operation start flow START Initial setting of these registers is performed before setting the TM0CE bit to 1.
Page 359 CHAPTER 8 16-BIT INTERVAL TIMER M (TMM) (2) Interval timer mode operation timing (a) Operation if TM0CMP0 register is set to 0000H If the TM0CMP0 register is set to 0000H, the INTTM0EQ0 signal is generated at each count clock. The value of the 16-bit counter is always 0000H. Count clock 16-bit counter FFFFH...
Page 360: Cautions
CHAPTER 8 16-BIT INTERVAL TIMER M (TMM) Cautions (1) Error on starting timer It takes one clock to generate the first compare match interrupt request signal (INTTM0EQ0) after the TM0CTL0.TM0CE bit is set to 1 and TMM0 is started. This is because the value of the 16-bit counter is FFFFH when the TM0CE bit = 0 and TMM0 is started asynchronously to the count clock.
Page 361: Chapter 9 Motor Control Function
CHAPTER 9 MOTOR CONTROL FUNCTION Functional Overview Timer Q1 (TMQ1) and the TMQ1 option (TMQOP1) can be used as an inverter function that controls a motor. It performs a tuning operation with timer P1 (TMP1) and A/D conversion of A/D converters 0 and 1 can be started when the value of TMQ1 matches the value of TMP1.
Page 362: Configuration
CHAPTER 9 MOTOR CONTROL FUNCTION Configuration The motor control function includes the following hardware. Item Configuration Timer register Dead-time counter m Compare register TMQ1 dead-time compare register (TQ1DTC register) Control registers TMQ1 option register 0 (TQ1OPT0) TMQ1 option register 1 (TQ1OPT1) TMQ1 option register 2 (TQ1OPT2) TMQ1 option register 3 (TQ1OPT3) TMQ1 I/O control register 3 (TQ1IOC3)
Page 363 CHAPTER 9 MOTOR CONTROL FUNCTION Figure 9-1. Block Diagram of Motor Control TOQ10 TMQ1 • Carrier TOQ1T1 • 3-phase PWM TMQ1 option generation • 6-phase PWM TOQ1B1 generation with dead time from 3-phase PWM TOQ1T2 TMP1 • Culling control • A/D trigger timing •...
Page 364 CHAPTER 9 MOTOR CONTROL FUNCTION Figure 9-2. TMQ1 Option Internal bus TOQ10 TQ1DTC High-impedance (10-bit dead-time value) output controller TMQ1 Channel 1 Positive Level TOQ1T1 phase control TOQ10 Clear Edge Dead-time counter 1 Active setting Output control TOQ11 detection (10 bits) Negative (internal Level...
Page 365 CHAPTER 9 MOTOR CONTROL FUNCTION (1) TMQ1 dead-time compare register (TQ1DTC) The TQ1DTC register is a 10-bit compare register that specifies a dead-time value. Rewriting this register is prohibited when the TQ1CTL0.TQ1CE bit = 1. This register can be read or written in 16-bit units. Reset sets this register to 0000H.
Page 366: Control Registers
CHAPTER 9 MOTOR CONTROL FUNCTION Control Registers (1) TMQ1 option register 0 (TQ1OPT0) The TQ1OPT0 register is an 8-bit register that controls the timer Q1 option function. This register can be read or written in 8-bit or 1-bit units. However, the TQ1CUF bit is read-only. Reset sets this register to 00H.
Page 367 CHAPTER 9 MOTOR CONTROL FUNCTION (2) TMQ1 option register 1 (TQ1OPT1) The TQ1OPT1 register is an 8-bit register that controls the interrupt request signal generated by the timer Q1 option function. <R> The TQ1OPT1 register generates the signals output to the interrupt culling circuit, A/D trigger generator 1, and A/D trigger generator 2 shown in Figure 9-2.
Page 368 CHAPTER 9 MOTOR CONTROL FUNCTION (3) TMQ1 option register 2 (TQ1OPT2) The TQ1OPT2 register is an 8-bit register that controls the timer Q1 option function. This register can be rewritten when the TQ1CTL0.TQ1CE bit is 1. However, rewriting the TQ1DTM bit is prohibited when the TQ1CE bit is 1.
Page 369 CHAPTER 9 MOTOR CONTROL FUNCTION (2/2) TQ1ATM03 TQ1ATM03 mode selection Output A/D trigger signal (TQTADT10) for INTTP1CC1 interrupt while dead-time counter is counting up. Output A/D trigger signal (TQTADT10) for INTTP1CC1 interrupt while dead-time counter is counting down. TQ1ATM02 TQ1ATM02 mode selection Output A/D trigger signal (TQTADT10) for INTTP1CC0 interrupt while dead-time counter is counting up.
Page 370 CHAPTER 9 MOTOR CONTROL FUNCTION (4) TMQ1 option register 3 (TQ1OPT3) The TQ1OPT3 register is an 8-bit register that controls the timer Q1 option function. This register can be rewritten when the TQ1CTL0.TQ1CE bit is 1. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 371 CHAPTER 9 MOTOR CONTROL FUNCTION (5) TMQ1 I/O control register 3 (TQ1IOC3) The TQ1IOC3 register is an 8-bit register that controls the output of the timer Q1 option function. To output from the TOQ1Tm pin, set the TQ1IOC0.TQ1OEm bit to 1 and then set the TQ1IOC3 register. The TQ1IOC3 register can be rewritten only when the TQ1CTL0.TQ1CE bit is 0.
Page 372 CHAPTER 9 MOTOR CONTROL FUNCTION (a) Output from TOQ1Tm and TOQ1Bm pins The TOQ1Tm pin output is controlled by the TQ1IOC0.TQ1OLm and TQ1IOC0.TQ1OEm bits. The TOQ1Bm pin output is controlled by the TQ1IOC3.TQ1OLBm and TQ1IOC3.TQ1OEBm bits. The timer output with each setting in the 6-phase PWM output mode is shown below. <R>...
Page 373 CHAPTER 9 MOTOR CONTROL FUNCTION Table 9-1. TOQ1Tm Pin Output TQ1OLm Bit TQ1OEm Bit TQ1CE Bit TOQ1Tm Pin Output Low-level output Low-level output TOQ1Tm positive-phase output High-level output High-level output TOQ1Tm negative-phase output Remark m = 1 to 3 Table 9-2. TOQ1Bm Pin Output TQ1OLBm Bit TQ1OEBm Bit TQ1CE Bit...
Page 374 CHAPTER 9 MOTOR CONTROL FUNCTION (6) High-impedance output control registers 00, 01, 10, 11 (HZAyCTLn) The HZAyCTLn registers are 8-bit registers that control the high-impedance state of the output buffer. These registers can be read or written in 8-bit or 1-bit units. However, the HZAyDCF1 bit is a read-only bit and cannot be written.
Page 375 CHAPTER 9 MOTOR CONTROL FUNCTION (1/2) After reset: 00H Address: HZA0CTL0 FFFFF5F0H, HZA0CTL1 FFFFF5F1H, HZA1CTL0 FFFFF630H, HZA1CTL1 FFFFF631H <7> <6> <3> <2> <0> HZAyCTLn HZAyDCEn HZAyDCMn HZAyDCNn HZAyDCPn HZAyDCTn HZAyDCCn HZAyDCFn n = 0, 1 y = 0, 1 High-impedance output control HZAyDCEn Disable high-impedance output control operation.
Page 376 CHAPTER 9 MOTOR CONTROL FUNCTION (2/2) HZAyDCCn High-impedance output control clear bit No operation Pins that have gone into a high-impedance state are output-enabled by software and the HZAyDCFn bit is cleared to 0. • Pins can function as output pins when the HZAyDCM bit = 0, regardless of the Note status of the external pin •...
Page 377 CHAPTER 9 MOTOR CONTROL FUNCTION Figure 9-4. High-Impedance Output Controller Configuration Edge detection INTP0 INTP0/ Analog HZA0CTL0 TOQH0OFF delay TOQH01 TOQH02 TMQ0 TOQH03 Edge detection INTP2 INTP2/ Analog HZA0CTL1 TOP2OFF delay TMP2 TOP21 INTP1 Edge detection Edge detection INTP3 INTP3/ Analog HZA1CTL1 TOP3OFF...
Page 378 CHAPTER 9 MOTOR CONTROL FUNCTION (a) Setting procedure (i) Setting of high-impedance control operation <1> Set the HZAyDCMn, HZAyDCNn, and HZAyDCP1 bits. <2> Set the HZAyDCEn bit to 1 (enable high-impedance control). (ii) Changing setting after enabling high-impedance control operation <1>...
Page 379: Operation
CHAPTER 9 MOTOR CONTROL FUNCTION Operation 9.4.1 System outline (1) Outline of 6-phase PWM output The 6-phase PWM output mode is used to generate a 6-phase PWM output wave, by using TMQ1 and the TMQ1 option in combination. The 6-phase PWM output mode is enabled by setting the TQ1CTL1.TQ1MD2 to TQ1CTL1.TQ1MD0 bits of TMQ1 to “111”.
Page 380 CHAPTER 9 MOTOR CONTROL FUNCTION <R> Figure 9-5. Outline of 6-Phase PWM Output Mode A/D trigger 16-bit counter Up/down selection generator INTTQ1OV signal (valley interrupt) Interrupt 0001H culling circuit INTTQ1CC0 signal (crest interrupt) TOQ10 pin output TQ1CCR0 register (carrier cycle) TOQ11 (internal signal) Dead-time counter 1...
Page 381 CHAPTER 9 MOTOR CONTROL FUNCTION Figure 9-6. Timing Chart of 6-Phase PWM Output Mode M + 1 M + 1 16-bit counter 0000H TQ1CCR0 M (carrier data) register TQ1CCR1 i (phase U data) register TQ1CCR2 j (phase V data) register TQ1CCR3 k (phase W data) register...
Page 382 CHAPTER 9 MOTOR CONTROL FUNCTION (2) Interrupt requests Two types of interrupt requests are available: the INTTQ1CC0 (crest interrupt) signal and INTTQ1OV (valley interrupt) signal. The INTTQ1CC0 and INTTQ1OV signals can be culled by using the TQ1OPT1 register. For details of culling interrupts, see 9.4.3 Interrupt culling function. •...
Page 383 CHAPTER 9 MOTOR CONTROL FUNCTION Figure 9-7. Interrupt and Up/Down Flag M + 1 M + 1 16-bit counter 0000H TQ1CCR0 M (carrier data) register TQ1CCR1 i (phase U data) register TQ1CCR2 j (phase V data) register TQ1CCR3 k (phase W data) register TOQ10 pin output...
Page 384: Dead-Time Control (Generation Of Negative-Phase Wave Signal)
CHAPTER 9 MOTOR CONTROL FUNCTION 9.4.2 Dead-time control (generation of negative-phase wave signal) (1) Dead-time control mechanism In the 6-phase PWM output mode, compare registers 1 to 3 (TQ1CCR1, TQ1CCR2, and TQ1CCR3) are used to set the duty factor, and compare register 0 (TQ1CCR0) is used to set the cycle. By setting these four registers and by starting the operation of TMQ, three types of PWM output waves (basic 3-phase waves) with a variable duty factor are generated.
Page 385 (2) PWM output of 0%/100% The V850ES/IE2 is capable of 0% wave output and 100% wave output for PWM output. A low level is continuously output from TOQ1Tm pin as the 0% wave output. A high level is continuously output from TOQ1Tm pin as the 100% wave output.
Page 386 CHAPTER 9 MOTOR CONTROL FUNCTION <R> Figure 9-10. 100% PWM Output Waveform (with Dead Time) 16-bit counter TQ1CCR0 register TQ1CCR1 0000H 0000H register CCR1 0000H 0000H 0000H buffer register <1> <2> <3> <4> TOQ1T1 100% pin output 100% output output TOQ1B1 pin output Forced timing...
Page 387 CHAPTER 9 MOTOR CONTROL FUNCTION <R> Figure 9-11. PWM Output Waveform from 0% to 100% and from 100% to 0% (with Dead Time) 16-bit counter TQ1CCR0 register TQ1CCR1 0000H M + 1 0000H M + 1 0000H register CCR1 M + 1 M + 1 0000H 0000H...
Page 388 CHAPTER 9 MOTOR CONTROL FUNCTION Figure 9-12. PWM Output Waveform with Dead Time (2) (a) 0% output (TQ1CCRm register = M + 1, TQ1CCR0 register = M, TQ1DTC register = a) 16-bit counter 0000H TOQ1m signal (internal signal) 000H (dead-time counter m does not count.) Dead-time counter m TOQ1Tm...
Page 389 CHAPTER 9 MOTOR CONTROL FUNCTION (4) Automatic dead-time width narrowing function (TQ1OPT2.TQ1DTM bit = 1) The dead-time width can be automatically narrowed in the vicinity of 0% output or 100% output by setting the TQ1OPT2.TQ1DTM bit to 1. By setting the TQ1DTM bit to 1, the dead-time counter is not cleared, but starts counting down if the TOQ1m (internal signal) output of timer Q changes during dead-time counting.
Page 390 CHAPTER 9 MOTOR CONTROL FUNCTION (5) Dead-time control in case of incorrect setting Usually, the TOQ1m (internal signal) output of TMQ1 changes only once during dead-time counting, only in the vicinity of 0% and 100% output. This section shows an example where the TQ1CCR0 register (carrier cycle) and TQ1DTC register (dead-time value) are incorrectly set.
Page 391: Interrupt Culling Function
CHAPTER 9 MOTOR CONTROL FUNCTION 9.4.3 Interrupt culling function • The interrupts to be culled are INTTQ1CC0 (crest interrupt) and INTTQ1OV (valley interrupt). • The TQ1OPT1.TQ1ICE bit is used to enable output of the INTTQ1CC0 interrupt and the number of times the interrupt is to be culled.
Page 392 CHAPTER 9 MOTOR CONTROL FUNCTION (1) Interrupt culling operation Figure 9-15. Interrupt Culling Operation When TQ1OPT1.TQ1ICE Bit = 1, TQ1OPT1.TQ1IOE Bit = 1, TQ1OPT2.TQ1RDE Bit = 1 (Crest/Valley Interrupt Output) 16-bit counter TQ1OPT1.TQ1ID4 to TQ1OPT1.TQ1ID0 bits = 00000 (not culled) INTTQ1CC0 signal INTTQ1OV signal TQ1OPT1.TQ1ID4 to TQ1OPT1.TQ1ID0 bits = 00001 (1 mask)
Page 393 CHAPTER 9 MOTOR CONTROL FUNCTION Figure 9-16. Interrupt Culling Operation When TQ1OPT1.TQ1ICE Bit = 1, TQ1OPT1.TQ1IOE Bit = 0, TQ1OPT2.TQ1RDE Bit = 1 (Crest Interrupt Output) 16-bit counter TQ1OPT1.TQ1ID4 to TQ1OPT1.TQ1ID0 bits = 00000 (not culled) INTTQ1CC0 signal INTTQ1OV signal TQ1OPT1.TQ1ID4 to TQ1OPT1.TQ1ID0 bits = 00001 (1 mask) INTTQ1CC0 signal INTTQ1OV signal...
Page 394 CHAPTER 9 MOTOR CONTROL FUNCTION Figure 9-17. Interrupt Culling Operation When TQ1OPT1.TQ1ICE Bit = 0, TQ1OPT1.TQ1IOE Bit = 1, TQ1OPT2.TQ1RDE Bit = 1 (Valley Interrupt Output) 16-bit counter TQ1OPT1.TQ1ID4 to TQ1OPT1.TQ1ID0 bits = 00000 (not culled) INTTQ1CC0 signal INTTQ1OV signal TQ1OPT1.TQ1ID4 to TQ1OPT1.TQ1ID0 bits = 00001 (1 mask) INTTQ1CC0 signal INTTQ1OV signal...
Page 395 CHAPTER 9 MOTOR CONTROL FUNCTION (2) To alternately output crest interrupt (INTTQ1CC0) and valley interrupt (INTTQ1OV) To alternately output the crest and valley interrupts, set both the TQ1OPT1.TQ1ICE and TQ1OPT1.TQ1IOE bits to 1. Figure 9-18. Crest/Valley Interrupt Output (a) TQ1OPT0.TQ1CMS bit = 0, TQ1OPT2.TQ1RDE bit = 1 (with transfer culling control) 16-bit counter INTTQ1CC0...
Page 396 CHAPTER 9 MOTOR CONTROL FUNCTION (3) To output only crest interrupt (INTTQ1CC0) Set the TQ1OPT1.TQ1ICE bit to 1 and clear the TQ1OPT1.TQ1IOE bit to 0. Figure 9-19. Crest Interrupt Output (a) TQ1OPT0.TQ1CMS bit = 0, TQ1OPT2.TQ1RDE bit = 1 (with transfer culling control) 16-bit counter INTTQ1CC0...
Page 397 CHAPTER 9 MOTOR CONTROL FUNCTION (4) To output only valley interrupt (INTTQ1OV) Clear the TQ1OPT1.TQ1ICE bit to 0 and set the TQ1IOE bit to 1. Figure 9-20. Valley Interrupt Output (a) TQ1OPT0.TQ1CMS bit = 0, TQ1OPT2.TQ1RDE bit = 1 (with transfer culling control) 16-bit counter INTTQ1CC0...
Page 398: Operation To Rewrite Register With Transfer Function
CHAPTER 9 MOTOR CONTROL FUNCTION 9.4.4 Operation to rewrite register with transfer function The following seven registers are provided with a transfer function and used to control a motor. Each of registers has a buffer register. • TQ1CCR0: Register that specifies the cycle of the 16-bit counter (TMQ) •...
Page 399 CHAPTER 9 MOTOR CONTROL FUNCTION (1) Anytime rewrite mode This mode is set by setting the TQ1OPT0.TQ1CMS bit to 1. The setting of the TQ1OPT2.TQ1RDE bit is ignored. In this mode, the value written to each register with a transfer function is immediately transferred to an internal buffer register and compared with the value of the counter.
Page 400 CHAPTER 9 MOTOR CONTROL FUNCTION (b) Rewriting TQ1CCRm register Figure 9-24 shows the timing of rewriting before the value of the 16-bit counter matches the value of the TQ1CCRm register (<1> in Figure 9-23), and Figure 9-25 shows the timing of rewriting after the value of the 16-bit counter matches the value of the TQ1CCRm register (<2>...
Page 401 CHAPTER 9 MOTOR CONTROL FUNCTION Figure 9-24. Example of Rewriting TQ1CCR1 to TQ1CCR3 Registers (Rewriting Before Match Occurs) If the TQ1CCRm register is rewritten before its value matches the value of the 16-bit counter, the register value will match the value of the 16-bit counter after the register has been rewritten. Consequently, the new register value is immediately reflected.
Page 402 CHAPTER 9 MOTOR CONTROL FUNCTION Figure 9-25. Example of Rewriting TQ1CCR1 to TQ1CCR3 Registers (Rewriting After Match Occurs) 16-bit counter TQ1CCRm register CCRm buffer register TOQ1Tm <3> <1> pin output INTTQ1CCm <2> signal <1> Matching of the count value of the 16-bit counter and the value of the TQ1CCRm register as a result of rewriting the register is ignored after a match signal has been generated, and the PWM output does not change.
Page 403 CHAPTER 9 MOTOR CONTROL FUNCTION (2) Batch rewrite mode (transfer mode) This mode is set by clearing the TQ1OPT0.TQ1CMS bit to 0, the TQ1OPT1.TQ1ID4 to TQ1OPT1.TQ1ID0 bits to 00000, and the TQ1OPT2.TQ1RDE bit to 0. In this mode, the values written to each compare register are transferred to the internal buffer register all at once at the transfer timing and compared with the counter value.
Page 404 CHAPTER 9 MOTOR CONTROL FUNCTION Figure 9-26. Basic Operation in Batch Mode 16-bit counter (TMQ1) Transfer <Q2> timing <Q3> TQ1CCR0 register CCR0 buffer register TQ1CCR1 <Q3> <Q1>&<P1> register CCR1 buffer register <Q3> TQ1CCR2 register CCR2 buffer register TQ1CCR3 <Q3> register CCR3 buffer register <Q3>...
Page 405 CHAPTER 9 MOTOR CONTROL FUNCTION (b) Rewriting TQ1CCR0 register When rewriting the TQ1CCR0 register in the batch rewrite mode, the output waveform differs depending on whether transfer occurs at the crest (match between the 16-bit counter value and TQ1CCR0 register value) or at the valley (match between the 16-bit counter value and 0001H).
Page 406 CHAPTER 9 MOTOR CONTROL FUNCTION Figure 9-28. Example of Rewriting TQ1CCR0 Register (During Counting Up) (a) M > N 16-bit N + 1 N + 1 counter Transfer timing TQ1CCR0 register CCR0 buffer 0000H register TQ1CCR1 register CCR1 buffer 0000H register TOQ1T1 pin output...
Page 407 CHAPTER 9 MOTOR CONTROL FUNCTION Figure 9-29. Example of Rewriting TQ1CCR0 Register (During Counting Down) M + 1 16-bit N + 1 counter Transfer timing TQ1CCR0 register CCR0 buffer 0000H register TQ1CCR1 register CCR1 buffer 0000H register TOQ1T1 pin output INTTQ1CC0 signal INTTQ1OV...
Page 408 CHAPTER 9 MOTOR CONTROL FUNCTION (c) Rewriting TQ1CCRm register Figure 9-30. Example of Rewriting TQ1CCRm Register 16-bit counter Transfer timing TQ1CCRm register CCRm buffer 0000H register TOQ1Tm pin output INTTQ1CCm signal <1> <2> <1> <2> Rewriting during period <1> (rewriting during counting up) Because the TQ1CCRm register value is transferred at the transfer timing of the crest (match between the 16- bit counter value and TQ1CCR0 register value), an asymmetrical triangular wave is output.
Page 409 CHAPTER 9 MOTOR CONTROL FUNCTION (3) Intermittent batch rewrite mode (transfer culling mode) This mode is set by clearing the TQ1OPT0.TQ1CMS bit to 0 and setting the TQ1OPT2.TQ1RDE bit to 1. In this mode, the values written to each compare register are transferred to the internal buffer register all at once at the culled transfer timing and compared with the counter value.
Page 410 CHAPTER 9 MOTOR CONTROL FUNCTION Figure 9-31. Basic Operation in Intermittent Batch Rewrite Mode 16-bit counter (TMQ1) Transfer <Q2> <Q4> <Q4> timing TQ1CCR0 <Q3> register CCR0 buffer register TQ1CCR1 <Q3> <Q1>&<P1> register CCR1 buffer register <Q3> TQ1CCR2 register CCR2 buffer register TQ1CCR3 <Q3>...
Page 411 CHAPTER 9 MOTOR CONTROL FUNCTION (b) Rewriting TQ1CCR0 register When rewriting the TQ1CCR0 register in the intermittent batch mode, the output waveform differs depending on where the occurrence of the crest or valley interrupt is specified by the interrupt culling setting.
Page 412 CHAPTER 9 MOTOR CONTROL FUNCTION Figure 9-33. Rewriting TQ1CCR0 Register (When Valley Interrupt Is Set) M + 1 M + 1 16-bit N + 1 counter Transfer timing TQ1CCR0 register CCR0 buffer 0000H register TQ1CCR1 register CCR1 buffer 0000H register TOQ1T1 pin output INTTQ1CC0...
Page 413 CHAPTER 9 MOTOR CONTROL FUNCTION (c) Rewriting TQ1CCR1 to TQ1CCR3 registers • Transfer at crest when crest interrupt is set Because the register is transferred at the transfer timing of the crest interrupt, an asymmetrical triangular wave is output. Figure 9-34. Rewriting TQ1CCR1 Register (TQ1OPT1.TQ1ICE bit = 1, TQ1OPT1.TQ1IOE bit = 0, TQ1OPT1.TQ1ID4 to TQ1OPT1.TQ1ID0 = 00001) 16-bit counter...
Page 414 CHAPTER 9 MOTOR CONTROL FUNCTION • Transfer at valley when valley interrupt is set Because the register is transferred at the transfer timing of the valley interrupt, a symmetrical triangular wave is output. Figure 9-35. Rewriting TQ1CCR1 Register (TQ1OPT1.TQ1ICE bit = 1, TQ1OPT1.TQ1IOE bit = 1, TQ1OPT1.TQ1ID4 to TQ1OPT1.TQ1ID0 = 00001) 16-bit counter Transfer...
Page 415 CHAPTER 9 MOTOR CONTROL FUNCTION (4) Rewriting TQ1OPT0.TQ1CMS bit The TQ1CMS bit can select the anytime rewrite mode and batch rewrite mode. This bit can be rewritten during timer operation (when TQ1CTL0.TQ1CE bit = 1). However, the operation and caution illustrated in Figure 9-31 are necessary.
Page 416: Tmp1 Tuning Operation For A/D Conversion Start Trigger Signal Output
CHAPTER 9 MOTOR CONTROL FUNCTION 9.4.5 TMP1 tuning operation for A/D conversion start trigger signal output This section explains the tuning operation of TMP1 and TMQ1 in the 6-phase PWM output mode. In the 6-phase PWM output mode, the tuning operation is performed with TMQ1 serving as the master and TMP1 as a slave.
Page 417 CHAPTER 9 MOTOR CONTROL FUNCTION (2) Tuning operation clearing procedure To clear the tuning operation and exit the 6-phase PWM output mode, set the TMP1 and TMQ1 registers using the following procedure. <1> Clear the TQ1CTL0.TQ1CE bit to 0 and stop the timer operation. <2>...
Page 418 CHAPTER 9 MOTOR CONTROL FUNCTION Figure 9-37. TMP1 During Tuning Operation M + 1 M + 1 16-bit counter of TMQ1 TQ1CCR0 M (carrier data) register i (phase U data) TQ1CCR1 register TQ1CCR2 j (phase V data) register TQ1CCR3 k (phase W data) register TOQ1T1 pin output (U)
Page 419: A/D Conversion Start Trigger Output Function
9.4.6 A/D conversion start trigger output function The V850ES/IE2 has a function to select four trigger sources (INTTQ1OV, INTTQ1CC0, INTTP1CC0, INTTP1CC1) to generate the A/D conversion start trigger signal (TQTADT00, TQTADT01) of A/D converters 0 and 1. The trigger sources are specified by the TQ1OPT2.TQ1AT00 to TQ1OPT2.TQ1AT03 and TQ1OPT3.TQ1AT10 to TQ1OPT3.TQ1AT13 bits.
Page 420 CHAPTER 9 MOTOR CONTROL FUNCTION The TQ1ATM03, TQ1ATM02, TQ1AT03 to TQ1AT00, TQ1ATM13, TQ1ATM12, and TQ1AT13 to TQ1AT10 bits can be rewritten while the timer is operating. If the bit that sets the A/D conversion start trigger signal is rewritten while the timer is operating, the new setting is immediately reflected on the output status of the A/D conversion start trigger.
Page 421 CHAPTER 9 MOTOR CONTROL FUNCTION Figure 9-38. Example of A/D Conversion Start Trigger (TQTADT10) Signal Output (TQ1OPT1.TQ1ICE Bit = 1, TQ1OPT1.TQ1IOE Bit = 1, TQ1OPT1.TQ1ID4 to TQ1OPT1.TQ1ID0 Bits = 00000: Without Interrupt Culling) 16-bit counter INTTQ1CC0 signal INTTQ1OV signal INTTP1CC0 signal INTTP1CC1 signal...
Page 422 CHAPTER 9 MOTOR CONTROL FUNCTION Figure 9-39. Example of A/D Conversion Start Trigger (TQTADT10) Signal Output (TQ1OPT1.TQ1ICE Bit = 0, TQ1OPT1.TQ1IOE Bit = 1, TQ1OPT1.TQ1ID4 to TQ1OPT1.Q1ID0 Bits = 00010: With Interrupt Culling) (1) 16-bit counter INTTQ1CC0 signal INTTQ1OV signal TQ1AT03 to TQ1AT00 bits = 0011 (both INTTQ1CC0 and INTTQ1OV signals are selected but crest interrupt (INTTQ1CC0) is not output because interrupt culling is specified.) TQTADT10 signal...
Page 423 CHAPTER 9 MOTOR CONTROL FUNCTION (1) Operation under boundary condition (operation when 16-bit counter matches INTTP1CC0 signal) Table 9-3. Operation When TQ1CCR0 Register = M, TQ1ATm2 Bit = 1, TQ1ATMm2 Bit = 0 (Counting Up Period Selected) Value of TP1CCR0 Value of 16-bit Value of 16-bit Status of 16-bit Counter...
Page 424: Chapter 10 Watchdog Timer Functions
CHAPTER 10 WATCHDOG TIMER FUNCTIONS 10.1 Functions The watchdog timer has the following functions. • Reset mode: Reset operation upon overflow of the watchdog timer (generation of WDTRES signal) • Non-maskable interrupt request mode: Non-maskable interrupt operation upon overflow of the watchdog timer (generation of INTWDT signal) Caution The watchdog timer is stopped after reset is released.
Page 425: Configuration
CHAPTER 10 WATCHDOG TIMER FUNCTIONS 10.2 Configuration The block diagram of the watchdog timer is shown below. Figure 10-1. Block Diagram of Watchdog Timer INTWDT to f Output 16-bit Selector controller WDTRES counter (internal reset signal) Clear WDM1 WDM0 WDCS2 WDCS1 WDCS0 Watchdog timer enable register (WDTE)
Page 426: Control Registers
CHAPTER 10 WATCHDOG TIMER FUNCTIONS 10.3 Control Registers (1) Watchdog timer mode register (WDTM) The WDTM register sets the overflow time and operation clock of the watchdog timer. This register can be read or written in 8-bit units. This register can be read any number of times, but can be written only once following reset release;...
Page 427: Operation
CHAPTER 10 WATCHDOG TIMER FUNCTIONS (2) Watchdog timer enable register (WDTE) The counter of the watchdog timer is cleared and counting restarted by writing “ACH” to the WDTE register. The WDTE register can be read or written in 8-bit units. Reset sets this register to 1AH.
Page 428: Chapter 11 A/D Converters 0 And 1
CHAPTER 11 A/D CONVERTERS 0 AND 1 11.1 Features • Two 10-bit resolution A/D converter circuits (A/D converters 0 and 1) Simultaneous sampling of two circuits possible • Analog input Two circuits, total of eight channels A/D converter 0: ANI00 to ANI03 (4 channels) A/D converter 1: ANI10 to ANI13 (4 channels) •...
Page 429: Configuration
CHAPTER 11 A/D CONVERTERS 0 AND 1 11.2 Configuration The block diagram is shown below. Figure 11-1. Block Diagram of A/D Converters 0 and 1 REFn ANIn0 Sample & hold circuit ANIn1 Voltage comparator ANIn2 Array ANIn3 Successive approximation register (SAR) Trigger source selector in timer trigger mode (see Figure 11-2) Edge detection/...
Page 430 CHAPTER 11 A/D CONVERTERS 0 AND 1 Cautions 1. If there is noise at the analog input pins (ANIn0 to ANIn3) or at the A/D converter reference voltage input pin (AV ), that noise may generate an illegal conversion result (n = 0, 1). REFn Software processing will be needed to avoid a negative effect on the system from this illegal conversion result.
Page 431 CHAPTER 11 A/D CONVERTERS 0 AND 1 A/D converters 0 and 1 consist of the following hardware. Table 11-1. Configuration of A/D Converters 0 and 1 Item Configuration Analog input ANI00 to ANI03, ANI10 to ANI13 (two circuits, total of eight channels) Registers Successive approximation register (SAR) A/Dn conversion result registers 0 to 3 (ADAnCR0 to ADAnCR3)
Page 432 CHAPTER 11 A/D CONVERTERS 0 AND 1 (5) Successive approximation register (SAR) The SAR is a 10-bit register that sets voltage tap data whose values from the array match the voltage values of the analog input pins, 1 bit at a time starting from the most significant bit (MSB). If data is set in the SAR all the way to the least significant bit (LSB) (end of A/D conversion), the contents of the SAR (conversion results) are held in A/Dn conversion result registers 0 to 3 (ADAnCR0 to ADAnCR3) (n = 0, 1).
Page 433: Control Registers
CHAPTER 11 A/D CONVERTERS 0 AND 1 (13) AV and AV pins These pins are the ground pins of A/D converters 0 and 1. Always make the potential at the AV pin the same as that at the EV pin even when A/D converters 0 and 1 are not used. (14) AV and AV pins...
Page 434 CHAPTER 11 A/D CONVERTERS 0 AND 1 After reset: 00H Address: ADA0M0 FFFFF200H, ADA1M0 FFFFF220H < > ADAnM0 ADAnCE ADAnMD1 ADAnMD0 ADAnETS1 ADAnETS0 ADAnTMD ADAnEF (n = 0, 1) ADAnCE A/D conversion operation control Stop conversion operation Start conversion operation ADAnMD1 ADAnMD0 Operation mode specification...
Page 435 CHAPTER 11 A/D CONVERTERS 0 AND 1 (2) A/D converter n mode register 1 (ADAnM1) The ADAnM1 register is an 8-bit register that specifies the number of conversion clocks. The number of conversion clocks includes the number of sampling clocks. This register can be read or written in 8-bit or 1-bit units.
Page 436 CHAPTER 11 A/D CONVERTERS 0 AND 1 (3) A/D converter n channel specification register (ADAnS) The ADAnS register is an 8-bit register that specifies the analog input pin. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 437 CHAPTER 11 A/D CONVERTERS 0 AND 1 (4) A/D converter n mode register 2 (ADAnM2) The ADAnM2 register is an 8-bit register that specifies the buffer mode and hardware trigger mode. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 438 CHAPTER 11 A/D CONVERTERS 0 AND 1 (5) A/Dn conversion result registers 0 to 3, 0H to 3H (ADAnCR0 to ADAnCR3, ADAnCR0H to ADAnCR3H) The ADAnCRm and ADAnCRH registers are registers that hold the A/D conversion results. Four of these registers are provided per circuit, and two circuits are available.
Page 439 CHAPTER 11 A/D CONVERTERS 0 AND 1 The relationship between the analog voltage input to the analog input pin (ANInm) and the A/D conversion result (of A/Dn conversion result register m (ADAnCRm)) is as follows: × 1,024 + 0.5) SAR = INT ( = SAR ×...
Page 440: Operation
CHAPTER 11 A/D CONVERTERS 0 AND 1 11.4 Operation Caution A/D converters 0 and 1 are capable of simultaneous sampling of two circuits. 11.4.1 Basic operation A/D conversion is executed by the following procedure. (1) Select an analog input pin, operation mode, and trigger mode, by using the ADAnM0, ADAnM1, ADAnM2, and Note ADAnS registers (n = 0, 1).
Page 441: Operation Mode And Trigger Mode
CHAPTER 11 A/D CONVERTERS 0 AND 1 (8) When comparison of 10 bits has been completed, the valid digital value result remains in the successive approximation register (SAR). This value is transferred to A/Dn conversion result register m (ADAnCRm) and the conversion result is stored in this register (n = 0, 1, m = 0 to 3).
Page 442 CHAPTER 11 A/D CONVERTERS 0 AND 1 (1) Trigger mode There are two types of trigger modes that serve as the start timing of an A/D conversion operation: software trigger mode and hardware trigger mode. There are two types of hardware trigger modes: external trigger mode and timer trigger mode.
Page 443 CHAPTER 11 A/D CONVERTERS 0 AND 1 (b) Timer trigger mode Of the ANIn0 to ANIn3 pins, the analog input pin specified by the ADAnS.ADAnS1 and ADAnS.ADAnS0 bits is used for A/D conversion in this mode. The timer (motor control function) is used for the A/D conversion start timing.
Page 444 CHAPTER 11 A/D CONVERTERS 0 AND 1 (c) External trigger mode Of the ANIn0 to ANIn3 pins, the analog input pin specified by the ADAnS.ADAnS1 and ADAnS.ADAnS0 bits is used for A/D conversion in this mode. The ADTRGn pin is used for the A/D conversion start timing. The ADTRG0 pin alternates as the P04/INTP4 pin, and the ADTRG1 pin as the P05/INTP5 pin.
Page 445 CHAPTER 11 A/D CONVERTERS 0 AND 1 (2) Operation mode There are four operation modes in which the ANIn0 to ANIn3 pins are set: continuous select mode, continuous scan mode, one-shot select mode, and one-shot scan mode. The continuous select mode and one-shot select mode have sub-modes that consist of 1-buffer mode and 4-buffer mode.
Page 446 CHAPTER 11 A/D CONVERTERS 0 AND 1 Figure 11-4. Continuous Select 1-Buffer Mode Operation Timing (When ADA0M0.ADA0MD1 and ADA0M0.ADA0MD0 Bits = 00, ADA0M2.ADA0BS Bit = 0, ADA0S.ADA0S1 and ADA0S.ADA0S0 Bits = 01) Data 4 Data 3 Data 2 ANI01 (input) Data 1 Data 5 Data 6...
Page 447 CHAPTER 11 A/D CONVERTERS 0 AND 1 • 4-buffer mode In this mode, the voltage of one analog input pin (ANInm) is A/D converted four times and the results are stored in the ADAnCRm register. The A/Dn conversion end interrupt request signal (INTADn) is generated when the four A/D conversions end.
Page 448 CHAPTER 11 A/D CONVERTERS 0 AND 1 (b) Continuous scan mode In this mode, the analog input pins (ANInm) specified by the ADAnS register are selected sequentially from the ANIn0 pin, and A/D conversion is executed continuously. The A/D conversion results are stored in the ADAnCRm register corresponding to the analog input pin.
Page 449 CHAPTER 11 A/D CONVERTERS 0 AND 1 (c) One-shot select mode In this mode, the analog input pin (ANInm) specified by the ADAnS register is A/D converted once. The conversion results are stored in the A/Dn conversion result register (ADAnCRm) corresponding to the ANInm pin.
Page 450 CHAPTER 11 A/D CONVERTERS 0 AND 1 • 4-buffer mode In this mode the voltage of one analog input pin (ANInm) is A/D converted four times and the results are stored in the ADAnCRm register. The A/Dn conversion end interrupt request signal (INTADn) is generated when the four A/D conversions end.
Page 451 CHAPTER 11 A/D CONVERTERS 0 AND 1 (d) One-shot scan mode In this mode, the analog input pins (ANInm) specified by the ADAnS register are selected sequentially from the ANIn0 pin, and A/D conversion is executed. The A/D conversion results are stored in the ADAnCRm register corresponding to the analog input pin.
Page 452: Operation In Software Trigger Mode
CHAPTER 11 A/D CONVERTERS 0 AND 1 11.5 Operation in Software Trigger Mode When the ADAnM0.ADAnCE bit is set (1), A/D conversion is started. When A/D conversion is started, the ADAnM0.ADAnEF bit = 1 (conversion in progress). If the ADAnM0, ADAnM2, and ADAnS registers are written during A/D conversion, the conversion is stopped and executed again from the beginning.
Page 453 CHAPTER 11 A/D CONVERTERS 0 AND 1 (1) 1-buffer mode (software trigger continuous select: 1 buffer) In this mode, the voltage of one analog input pin (ANInm) is A/D converted once. The conversion results are stored in one ADAnCRm register. The ANInm pin and ADAnCRm register correspond one to one. Each time an A/D conversion is executed, an A/Dn conversion end interrupt request signal (INTADn) is generated and A/D conversion ends.
Page 454 CHAPTER 11 A/D CONVERTERS 0 AND 1 (2) 4-buffer mode (software trigger continuous select: 4 buffers) In this mode, the voltage of one analog input pin (ANInm) is A/D converted four times and the results are stored in the ADAnCRm register. When the 4th A/D conversion ends, an A/Dn conversion end interrupt request signal (INTADn) is generated.
Page 455: Continuous Scan Mode Operations
CHAPTER 11 A/D CONVERTERS 0 AND 1 11.5.2 Continuous scan mode operations In this mode, the analog input pins (ANInm) specified by the ADAnS register are selected sequentially from the ANIn0 pin, and A/D conversion is executed continuously. The A/D conversion results are stored in the ADAnCRm register corresponding to the analog input pin.
Page 456: One-Shot Select Mode Operations
CHAPTER 11 A/D CONVERTERS 0 AND 1 11.5.3 One-shot select mode operations In this mode, the analog input pin (ANInm) specified by the ADAnS register is A/D converted continuously. The conversion results are stored in the ADAnCRm register. In the one-shot select mode, the 1-buffer mode and 4-buffer mode are supported according to the method of storing the A/D conversion results.
Page 457 CHAPTER 11 A/D CONVERTERS 0 AND 1 (2) 4-buffer mode (software trigger one-shot select: 4 buffers) In this mode, the voltage of one analog input pin (ANInm) is A/D converted four times and the results are stored in the ADAnCRm register. When the 4th A/D conversion ends, an A/Dn conversion end interrupt request signal (INTADn) is generated.
Page 458: One-Shot Scan Mode Operations
CHAPTER 11 A/D CONVERTERS 0 AND 1 11.5.4 One-shot scan mode operations In this mode, the analog input pins (ANInm) specified by the ADAnS register are selected sequentially from the ANIn0 pin, and A/D conversion is executed continuously. The A/D conversion results are stored in the ADAnCRm register corresponding to the analog input pin.
Page 459: Operation In Timer Trigger Mode
CHAPTER 11 A/D CONVERTERS 0 AND 1 11.6 Operation in Timer Trigger Mode With A/D converter n, the conversion timing is specified by using the A/D conversion start trigger signal (TQTADT1n) from the timer (motor control function) (see Figure 11-2). •...
Page 460: Continuous Select Mode/One-Shot Select Mode Operations
CHAPTER 11 A/D CONVERTERS 0 AND 1 11.6.1 Continuous select mode/one-shot select mode operations In this mode, the voltage of the analog input pin (ANInm) specified by the ADAnS register is A/D converted. The conversion results are stored in the ADAnCRm register. In the continuous select mode or one-shot select mode, the 1-buffer mode and 4-buffer mode are supported according to the method of storing the A/D conversion results.
Page 461 CHAPTER 11 A/D CONVERTERS 0 AND 1 (2) 4-buffer mode operation (4 buffers of continuous select/one-shot select by timer trigger) In this mode, the voltage of one analog input pin (ANInm) is A/D converted four times using the A/D conversion start trigger signal from the timer (motor control function) as a trigger, and the results are stored in the ADAnCRm register.
Page 462: Continuous Scan Mode/One-Shot Scan Mode Operations
CHAPTER 11 A/D CONVERTERS 0 AND 1 11.6.2 Continuous scan mode/one-shot scan mode operations In this mode, the analog input pins (ANInm) specified by the ADAnS register are selected sequentially from the ANIn0 pin using the A/D conversion start trigger signal from the timer (motor control function) as a trigger and A/D conversion is performed continuously.
Page 463: Operation In External Trigger Mode
CHAPTER 11 A/D CONVERTERS 0 AND 1 11.7 Operation in External Trigger Mode In the external trigger mode, the analog input pins (ANIn0 to ANIn3) are A/D converted at the ADTRGn pin input timing. The ADTRG0 pin has an alternate function as the P04/INTP4 pin and the ADTRG1 pin has an alternate function as the P05/INTP5 pin.
Page 464: Continuous Select Mode/One-Shot Select Mode Operations
CHAPTER 11 A/D CONVERTERS 0 AND 1 11.7.1 Continuous select mode/one-shot select mode operations In this mode, the analog input pin (ANInm) specified by the ADAnS register is A/D converted. The conversion results are stored in the ADAnCRm register. In the continuous select mode or one-shot select mode, there are two select modes: 1-buffer mode and 4-buffer mode, according to the method of storing the A/D conversion results.
Page 465 CHAPTER 11 A/D CONVERTERS 0 AND 1 (2) 4-buffer mode (4 buffers of continuous select/one-shot select by external trigger) In this mode, the voltage of one analog input pin (ANInm) is A/D converted four times using the ADTRGn signal as a trigger and the results are stored in the ADAnCRm register (n = 0, 1, m = 0 to 3). The A/Dn conversion end interrupt request signal (INTADn) is generated when the four A/D conversions end.
Page 466: Continuous Scan Mode/One-Shot Scan Mode Operations
CHAPTER 11 A/D CONVERTERS 0 AND 1 11.7.2 Continuous scan mode/one-shot scan mode operations In this mode, the analog input pins (ANInm) specified by the ADAnS register are selected sequentially from the ANIn0 pin using the ADTRGn signal as a trigger, and A/D converted continuously. The A/D conversion results are stored in the ADAnCRm register corresponding to the analog input pin.
Page 467: Internal Equivalent Circuit
CHAPTER 11 A/D CONVERTERS 0 AND 1 11.8 Internal Equivalent Circuit The following figure shows the equivalent circuit of the analog input block. Figure 11-22. ANInm Pin Internal Equivalent Circuit ANInm 4.0 kΩ 15 pF 4.2 pF Remarks 1. The maximum values are shown (reference values). 2.
Page 468 CHAPTER 11 A/D CONVERTERS 0 AND 1 An example of calculating an overall error of A/D converters 0 and 1 is shown below. Figure 11-23. Example of Calculating Overall Error of A/D Converters 0 and 1 V850ES/IE2 ANInm Conversion A/D Initialization...
Page 469: Notes On Operation
CHAPTER 11 A/D CONVERTERS 0 AND 1 11.9 Notes on Operation 11.9.1 Stopping conversion operation When the ADAnM0.ADAnCE bit is cleared to 0 during a conversion operation, the conversion operation stops and the conversion results are not stored in A/Dn conversion result register m (ADAnCRm). The ADAnCE bit is not cleared to 0 even after the A/Dn conversion end interrupt request signal (INTADn) has been generated in all modes.
Page 470: Timer Interrupt Request Signal In Timer Trigger Mode
CHAPTER 11 A/D CONVERTERS 0 AND 1 11.9.4 Timer interrupt request signal in timer trigger mode The timer interrupt request signal (TQTADT1n) becomes an A/D conversion start trigger and starts the conversion operation. When this happens, the timer interrupt request signal also functions as an interrupt for the CPU. In order to prevent the generation of interrupts for the CPU, disable interrupts using the mask bits of the interrupt control register.
Page 471: Restrictions On Setting One-Shot Mode And Software Trigger Mode
CHAPTER 11 A/D CONVERTERS 0 AND 1 11.9.8 Restrictions on setting one-shot mode and software trigger mode If the A/D converters 0 and 1 are set in the one-shot select mode and software trigger mode (ADAnM0 register = 1010XX0XB) or one-shot scan mode and software trigger mode (ADAnM0 register = 1011XX0XB), a re-conversion operation should be performed in a new condition when data is written to any of the ADAnM0, ADAnM2, and ADAnS registers upon completion of an A/D conversion operation.
Page 472: How To Read A/D Converter Characteristics Table
CHAPTER 11 A/D CONVERTERS 0 AND 1 11.10 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1 LSB (Least Significant Bit).
Page 473 CHAPTER 11 A/D CONVERTERS 0 AND 1 (3) Quantization error When analog values are converted to digital values, a ±1/2 LSB error naturally occurs. In an A/D converter, an analog input voltage in a range of ±1/2 LSB is converted to the same digital code, so a quantization error cannot be avoided.
Page 474 CHAPTER 11 A/D CONVERTERS 0 AND 1 (5) Full-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (full-scale value − 3/2 LSB) when the digital output changes from 1……110 to 1……111. Figure 11-27.
Page 475 CHAPTER 11 A/D CONVERTERS 0 AND 1 (7) Integral linearity error This shows the degree to which the conversion characteristics deviate from the ideal linear relationship. It expresses the maximum value of the difference between the actual measurement value and the ideal straight line when the zero-scale error and full-scale error are 0.
Page 476: Chapter 12 Asynchronous Serial Interface A (Uarta)
CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) The V850ES/IE2 incorporates UARTA0 and UARTA1. 12.1 Features Transfer rate: 300 bps to 1.25 Mbps (using peripheral clock (f ) of 20 MHz and dedicated baud rate generator) Full-duplex communication: Internal UARTA receive data register n (UAnRX)
Page 477: Configuration
CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 12.2 Configuration The block diagram of the UARTAn is shown below. <R> Figure 12-1. Block Diagram of UARTAn Internal bus INTUAnT INTUAnR Reception unit Transmission UAnRX UAnTX unit Receive Transmit Reception Transmission shift register shift register controller controller...
Page 478 CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (1) UARTAn control register 0 (UAnCTL0) The UAnCTL0 register is an 8-bit register used to specify the UARTAn operation. (2) UARTAn control register 1 (UAnCTL1) The UAnCTL1 register is an 8-bit register used to select the base clock (f ) for the UARTAn.
Page 479: Control Registers
CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 12.3 Control Registers (1) UARTAn control register 0 (UAnCTL0) The UAnCTL0 register is an 8-bit register that controls the UARTAn serial transfer operation. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 10H.
Page 480 CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (2/2) Note UAnDIR Transfer direction selection MSB-first transfer LSB-first transfer Note Note UAnPS1 UAnPS0 Parity selection during transmission Parity selection during reception No parity output Reception with no parity 0 parity output Reception with 0 parity Odd parity output Odd parity check Even parity output...
Page 481 CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (4) UARTAn option control register 0 (UAnOPT0) The UAnOPT0 register is an 8-bit register that controls the serial transfer operation of UARTAn. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 14H.
Page 482 CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) After reset: 00H Address: UA0STR FFFFFA04H, UA1STR FFFFFA14H <2> <1> <7> <0> UAnSTR UAnTSF UAnPE UAnFE UAnOVE (n = 0, 1) UAnTSF Transfer status flag • When the UAnPWR bit = 0 or the UAnTXE bit = 0 has been set. •...
Page 483 CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (6) UARTAn receive data register (UAnRX) The UAnRX register is an 8-bit buffer register that stores parallel data converted by the UARTAn receive shift register. The data stored in the UARTAn receive shift register is transferred to the UAnRX register upon end of reception of 1 byte of data.
Page 484: Interrupt Request Signals
CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 12.4 Interrupt Request Signals The following three interrupt request signals are generated from UARTAn. • Reception error interrupt request signal (INTUAnRE) • Reception end interrupt request signal (INTUAnR) • Transmission enable interrupt request signal (INTUAnT) Among these three interrupt signals, the reception error interrupt signal has the highest default priority, and the reception end interrupt request signal and transmission enable interrupt request signal follow in this order.
Page 485: Operation
CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 12.5 Operation 12.5.1 Data format Full-duplex serial data reception and transmission is performed. As shown in Figure 12-2, one data frame of transmit/receive data consists of a start bit, character bits, parity bit, and stop bit(s).
Page 486 CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) Figure 12-2. UARTA Transmit/Receive Data Format (a) 8-bit data length, LSB first, even parity, 1 stop bit, transfer data: 55H 1 data frame Start Parity Stop (b) 8-bit data length, MSB first, even parity, 1 stop bit, transfer data: 55H 1 data frame Start Parity...
Page 487: Uart Transmission
CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 12.5.2 UART transmission A high level is output to the TXDAn pin by setting the UAnCTL0.UAnPWR bit to 1. Next, the transmission enabled status is set by setting the UAnCTL0.UAnTXE bit to 1, and transmission is started by writing transmit data to the UAnTX register.
Page 488: Continuous Transmission Procedure
CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 12.5.3 Continuous transmission procedure UARTAn can write the next transmit data to the UAnTX register when the UARTAn transmit shift register starts the shift operation. The transmit timing of the UARTAn transmit shift register can be judged from the transmission enable interrupt request signal (INTUAnT).
Page 489 CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) Figure 12-5. Continuous Transmission Operation Timing (a) Transmission start Start Data (1) Parity Stop Start Data (2) Parity Stop Start TXDAn pin UAnTX register Data (1) Data (2) Data (3) Transmission Data (2) Data (1) shift register <R>...
Page 490: Uart Reception
CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 12.5.4 UART reception The reception wait status is set by setting the UAnCTL0.UAnPWR bit to 1 and then setting the UAnCTL0.UAnRXE bit to 1. In the reception wait status, the RXDAn pin is monitored and start bit detection is performed. Start bit detection is performed using a two-step detection routine.
Page 491: Reception Errors
CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 12.5.5 Reception errors Errors during a receive operation are of three types: parity errors, framing errors, and overrun errors. Data reception result error flags are set in the UAnSTR register and a reception error interrupt request signal (INTUAnRE) is output when an error occurs.
Page 492: Parity Types And Operations
CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 12.5.6 Parity types and operations The parity bit is used to detect bit errors in the communication data. Normally the same parity is used on the transmission side and the reception side. In the case of even parity and odd parity, it is possible to detect odd-count bit errors. In the case of 0 parity and no parity, errors cannot be detected.
Page 493: Receive Data Noise Filter
CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 12.5.7 Receive data noise filter This filter samples the RXDAn pin using the base clock (f ) of the prescaler output. UCLK When the same sampling value is read twice, the match detector output changes and the RXDAn signal is sampled as the input data.
Page 494: Dedicated Baud Rate Generator
CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 12.6 Dedicated Baud Rate Generator The dedicated baud rate generator consists of a source clock selector block and an 8-bit programmable counter, and generates a serial clock during transmission and reception with UARTAn. Regarding the serial clock, a dedicated baud rate generator output can be selected for each channel.
Page 495 CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (2) UARTAn control register 1 (UAnCTL1) The UAnCTL1 register is an 8-bit register that selects the UARTAn base clock. This register can be read or written in 8-bit units. Reset sets this register to 00H. Caution Clear the UAnCTL0.UAnPWR bit to 0 before rewriting the UAnCTL1 register.
Page 496 CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (3) UARTAn control register 2 (UAnCTL2) The UAnCTL2 register is an 8-bit register that selects the baud rate (serial transfer speed) clock of UARTAn. This register can be read or written in 8-bit units. Reset sets this register to FFH.
Page 497 CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (4) Baud rate The baud rate is obtained by the following equation. UCLK Baud rate = [bps] 2 × k : Frequency of base clock selected by the UAnCTL1.UAnCKS3 to UAnCTL1.UAnCKS0 bits UCLK Value set using the UAnCTL2.UAnBRS7 to UAnCTL2.UAnBRS0 bits (k = 4, 5, 6, ..., 255) (5) Baud rate error The baud rate error is obtained by the following equation.
Page 498 CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (6) Baud rate setting example Table 12-3. Baud Rate Generator Setting Data Baud Rate = 20 MHz (bps) UAnCTL1 UAnCTL2 ERR (%) 0.16 0.16 1,200 0.16 2,400 0.16 4,800 0.16 9,600 0.16 19,200 0.16 31,250 38,400...
Page 499 CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (7) Allowable baud rate range during reception The baud rate error range at the destination that is allowable during reception is shown below. Caution The baud rate error during reception must be set within the allowable error range using the following equation.
Page 500 CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) Therefore, the maximum baud rate that can be received by the destination is as follows. − BRmax = (FLmin/11) Brate 21k + 2 Similarly, obtaining the following maximum allowable transfer rate yields the following. 21k −...
Page 501: Cautions
CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (8) Transfer rate during continuous transmission During continuous transmission, the transfer rate from the stop bit to the next start bit is usually 2 base clocks longer. However, timing initialization is performed via start bit detection by the receiving side, so this has no influence on the transfer result.
Page 502: Chapter 13 3-Wire Variable-Length Serial I/O (Csib)
CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) The V850ES/IE2 incorporates CSIB0. 13.1 Features Transfer rate: 8 Mbps (using internal clock) Master mode and slave mode selectable 8-bit to 16-bit transfer, 3-wire serial interface Interrupt request signals (INTCB0RE, INTCB0T, INTCB0R) Serial clock and data phase switchable...
Page 503: Configuration
CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 13.2 Configuration The following shows the block diagram of CSIB0. Figure 13-1. Block Diagram of CSIB0 Internal bus CB0CTL1 CB0CTL0 CB0CTL2 CB0STR INTCB0T Controller INTCB0R INTCB0RE Phase control CCLK /128 CB0TX SCKB0 Phase SO latch SOB0 control...
Page 504 CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (1) CSIB0 receive data register (CB0RX) The CB0RX register is a 16-bit buffer register that holds receive data. This register is read-only, in 16-bit units. The receive operation is started by reading the CB0RX register in the reception enabled status. If the transfer data length is 8 bits, the lower 8 bits of this register are read-only in 8-bit units as the CB0RXL register.
Page 505: Control Registers
CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 13.3 Control Registers The following registers are used to control CSIB0. • CSIB0 control register 0 (CB0CTL0) • CSIB0 control register 1 (CB0CTL1) • CSIB0 control register 2 (CB0CTL2) • CSIB0 status register (CB0STR) (1) CSIB0 control register 0 (CB0CTL0) CB0CTL0 is a register that controls the CSIB0 serial transfer operation.
Page 506 CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2/2) Note 1 CB0DIR Specification of transfer direction mode (MSB/LSB) MSB first LSB first Note 1 CB0TMS Transfer mode specification Single transfer mode Continuous transfer mode • When using single transmission or transmission/reception mode with communication type 2 or 4 (CB0CTL1.CB0DAP bit = 1), write the transfer data to the CB0TX register after checking that the CB0STR.CB0TSF bit is 0.
Page 507 CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (a) How to use CB0SCE bit (i) In single reception mode <1> When the reception of the last data is completed with INTCB0R interrupt servicing, clear the CB0SCE bit to 0, and then read the CB0RX register. <2>...
Page 508 CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) CSIB0 control register 1 (CB0CTL1) CB0CTL1 is an 8-bit register that controls the CSIB0 serial transfer operation. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. Caution The CB0CTL1 register can be rewritten only when the CB0CTL0.CB0PWR bit = 0.
Page 509 CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (3) CSIB0 control register 2 (CB0CTL2) CB0CTL2 is an 8-bit register that controls the number of CSIB0 serial transfer bits. This register can be read or written in 8-bit units. Reset sets this register to 00H. Caution The CB0CTL2 register can be rewritten only when the CB0CTL0.CB0PWR bit = 0 or when both the CB0TXE and CB0RXE bits = 0.
Page 510 CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (a) Transfer data length change function The CSIB0 transfer data length can be set in 1-bit units between 8 and 16 bits using the CB0CTL2.CB0CL3 to CB0CTL2.CB0CL0 bits. When the transfer bit length is set to a value other than 16 bits, set the data to the CB0TX or CB0RX register starting from the LSB, regardless of whether the transfer start bit is the MSB or LSB.
Page 511 CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (4) CSIB0 status register (CB0STR) CB0STR is an 8-bit register that displays the CSIB0 status. This register can be read or written in 8-bit or 1-bit units, but the CB0TSF flag is read-only. Reset sets this register to 00H.
Page 512: Operation
CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 13.4 Operation 13.4.1 Single transfer mode (master mode, transmission mode) MSB first (CB0CTL0.CB0DIR bit = 0), communication type 1 (CB0CTL1.CB0CKP and CB0CTL1.CB0DAP bits = 00), communication clock (f ) = f /2 (CB0CTL1.CB0CKS2 to CB0CTL1.CB0CKS0 bits = 000), transfer data length CCLK = 8 bits (CB0CTL2.CB0CL3 to CB0CTL2.CB0CL0 bits = 0000) (1) Operation flow...
Page 513 CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing CB0TSF bit INTCB0R signal SCKB0 pin SOB0 pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1...
Page 514: Single Transfer Mode (Master Mode, Reception Mode)
CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 13.4.2 Single transfer mode (master mode, reception mode) MSB first (CB0CTL0.CB0DIR bit = 0), communication type 1 (CB0CTL1.CB0CKP and CB0CTL1.CB0DAP bits = 00), communication clock (f ) = f /2 (CB0CTL1.CB0CKS2 to CB0CTL1.CB0CKS0 bits = 000), transfer data length CCLK = 8 bits (CB0CTL2.CB0CL3 to CB0CTL2.CB0CL0 bits = 0000) (1) Operation flow...
Page 515 CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing CB0TSF bit INTCB0R signal SCKB0 pin SIB0 pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2...
Page 516: Single Transfer Mode (Master Mode, Transmission/Reception Mode)
CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 13.4.3 Single transfer mode (master mode, transmission/reception mode) MSB first (CB0CTL0.CB0DIR bit = 0), communication type 1 (CB0CTL1.CB0CKP and CB0CTL1.CB0DAP bits = 00), communication clock (f ) = f /2 (CB0CTL1.CB0CKS2 to CB0CTL1.CB0CKS0 bits = 000), transfer data length CCLK = 8 bits (CB0CTL2.CB0CL3 to CB0CTL2.CB0CL0 bits = 0000) (1) Operation flow...
Page 517 CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing CB0TSF bit INTCB0R signal SCKB0 pin SOB0 pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1...
Page 518: Single Transfer Mode (Slave Mode, Transmission Mode)
CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 13.4.4 Single transfer mode (slave mode, transmission mode) MSB first (CB0CTL0.CB0DIR bit = 0), communication type 1 (CB0CTL1.CB0CKP and CB0CTL1.CB0DAP bits = 00), communication clock (f ) = external clock (SCKB0) (CB0CTL1.CB0CKS2 to CB0CTL1.CB0CKS0 bits = 111), CCLK transfer data length = 8 bits (CB0CTL2.CB0CL3 to CB0CTL2.CB0CL0 bits = 0000) (1) Operation flow...
Page 519 CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing CB0TSF bit INTCB0R signal SCKB0 pin SOB0 pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1...
Page 520: Single Transfer Mode (Slave Mode, Reception Mode)
CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 13.4.5 Single transfer mode (slave mode, reception mode) MSB first (CB0CTL0.CB0DIR bit = 0), communication type 1 (CB0CTL1.CB0CKP and CB0CTL1.CB0DAP bits = 00), communication clock (f ) = external clock (SCKB0) (CB0CTL1.CB0CKS2 to CB0CTL1.CB0CKS0 bits = 111), CCLK transfer data length = 8 bits (CB0CTL2.CB0CL3 to CB0CTL2.CB0CL0 bits = 0000) (1) Operation flow...
Page 521 CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing CB0TSF bit INTCB0R signal SCKB0 pin SIB0 pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0...
Page 522: Single Transfer Mode (Slave Mode, Transmission/Reception Mode)
CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 13.4.6 Single transfer mode (slave mode, transmission/reception mode) MSB first (CB0CTL0.CB0DIR bit = 0), communication type 1 (CB0CTL1.CB0CKP and CB0CTL1.CB0DAP bits = 00), communication clock (f ) = external clock (SCKB0) (CB0CTL1.CB0CKS2 to CB0CTL1.CB0CKS0 bits = 111), CCLK transfer data length = 8 bits (CB0CTL2.CB0CL3 to CB0CTL2.CB0CL0 bits = 0000) (1) Operation flow...
Page 523 CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing CB0TSF bit INTCB0R signal SCKB0 pin SOB0 pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0...
Page 524: Continuous Transfer Mode (Master Mode, Transmission Mode)
CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 13.4.7 Continuous transfer mode (master mode, transmission mode) MSB first (CB0CTL0.CB0DIR bit = 0), communication type 1 (CB0CTL1.CB0CKP and CB0CTL1.CB0DAP bits = 00), communication clock (f ) = f /2 (CB0CTL1.CB0CKS2 to CB0CTL1.CB0CKS0 bits = 000), transfer data length CCLK = 8 bits (CB0CTL2.CB0CL3 to CB0CTL2.CB0CL0 bits = 0000) (1) Operation flow...
Page 525 CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing CB0TSF bit <R> INTCB0T signal INTCB0R signal SCKB0 pin SOB0 pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2...
Page 526: Continuous Transfer Mode (Master Mode, Reception Mode)
CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 13.4.8 Continuous transfer mode (master mode, reception mode) MSB first (CB0CTL0.CB0DIR bit = 0), communication type 1 (CB0CTL1.CB0CKP and CB0CTL1.CB0DAP bits = 00), communication clock (f ) = f /2 (CB0CTL1.CB0CKS2 to CB0CTL1.CB0CKS0 bits = 000), transfer data length CCLK = 8 bits (CB0CTL2.CB0CL3 to CB0CTL2.CB0CL0 bits = 0000) User’s Manual U17716EJ2V0UD...
Page 527 CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (1) Operation flow START CB0CTL1 register ← 00H CB0CTL2 register ← 00H (1), (2), (3) CB0CTL0 register ← A3H CB0RX register dummy read Start reception INTCB0R interrupt generated? INTCB0RE interrupt Is data being received generated? last data? CB0SCE bit = 0...
Page 528 CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing CB0TSF bit INTCB0R signal CB0SCE bit SCKB0 pin SOB0 pin SIB0 pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1...
Page 529: Continuous Transfer Mode (Master Mode, Transmission/Reception Mode)
CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 13.4.9 Continuous transfer mode (master mode, transmission/reception mode) MSB first (CB0CTL0.CB0DIR bit = 0), communication type 1 (CB0CTL1.CB0CKP and CB0CTL1.CB0DAP bits = 00), communication clock (f ) = f /2 (CB0CTL1.CB0CKS2 to CB0CTL1.CB0CKS0 bits = 000), transfer data length CCLK = 8 bits (CB0CTL2.CB0CL3 to CB0CTL2.CB0CL0 bits = 0000) User’s Manual U17716EJ2V0UD...
Page 530 CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (1) Operation flow START CB0CTL1 register ← 00H CB0CTL2 register ← 00H (1), (2), (3) CB0CTL0 register ← E3H Write CB0TX register Start transmission/reception INTCB0T interrupt (6), (11) generated? (11) Is data being transmitted last data? Write CB0TX register INTCB0R interrupt...
Page 531 CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing (1/2) CB0TSF bit INTCB0T signal INTCB0R signal SCKB0 pin SOB0 pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1...
Page 532 CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2/2) (11) The transfer of the transmit data from the CB0TX register to the shift register is completed and the INTCB0T signal is generated. To end continuous transmission/reception with the current transmission/reception, do not write to the CB0TX register. (12) When the next transmit data is not written to the CB0TX register before transfer completion, stop the serial clock output to the SCKB0 pin after transfer completion, and clear the CB0TSF bit to 0.
Page 533: Continuous Transfer Mode (Slave Mode, Transmission Mode)
CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 13.4.10 Continuous transfer mode (slave mode, transmission mode) MSB first (CB0CTL0.CB0DIR bit = 0), communication type 1 (CB0CTL1.CB0CKP and CB0CTL1.CB0DAP bits = 00), communication clock (f ) = external clock (SCKB0) (CB0CTL1.CB0CKS2 to CB0CTL1.CB0CKS0 bits = 111), CCLK transfer data length = 8 bits (CB0CTL2.CB0CL3 to CB0CTL2.CB0CL0 bits = 0000) (1) Operation flow...
Page 534 CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing CB0TSF bit INTCB0T signal SCKB0 pin SOB0 pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1...
Page 535: Continuous Transfer Mode (Slave Mode, Reception Mode)
CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 13.4.11 Continuous transfer mode (slave mode, reception mode) MSB first (CB0CTL0.CB0DIR bit = 0), communication type 1 (CB0CTL1.CB0CKP and CB0CTL1.CB0DAP bits = 00), communication clock (f ) = external clock (SCKB0) (CB0CTL1.CB0CKS2 to CB0CTL1.CB0CKS0 bits = 111), CCLK transfer data length = 8 bits (CB0CTL2.CB0CL3 to CB0CTL2.CB0CL0 bits = 0000) User’s Manual U17716EJ2V0UD...
Page 536 CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (1) Operation flow START CB0CTL1 register ← 07H CB0CTL2 register ← 00H (1), (2), (3) CB0CTL0 register ← A3H CB0RX register dummy read SCKB0 pin input started? Start reception INTCB0R interrupt generated? INTCB0RE interrupt Is data being received generated? last data?
Page 537 CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing CB0TSF bit INTCB0R signal CB0SCE bit SCKB0 pin SIB0 pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2...
Page 538: Continuous Transfer Mode (Slave Mode, Transmission/Reception Mode)
CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 13.4.12 Continuous transfer mode (slave mode, transmission/reception mode) MSB first (CB0CTL0.CB0DIR bit = 0), communication type 1 (CB0CTL1.CB0CKP and CB0CTL1.CB0DAP bits = 00), communication clock (f ) = external clock (SCKB0) (CB0CTL1.CB0CKS2 to CB0CTL1.CB0CKS0 bits = 111), CCLK transfer data length = 8 bits (CB0CTL2.CB0CL3 to CB0CTL2.CB0CL0 bits = 0000) User’s Manual U17716EJ2V0UD...
Page 539 CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (1) Operation flow START CB0CTL1 register ← 07H CB0CTL2 register ← 00H (1), (2), (3) CB0CTL0 register ← E3H Write CB0TX register SCKB0 pin input started? Start transmission/reception INTCB0T interrupt (6), (11) generated? (11) Is data being transmitted last data?
Page 540 CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing (1/2) CB0TSF bit INTCB0T signal INTCB0R signal SCKB0 pin SOB0 pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2...
Page 541 CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2/2) (12) When the clock of the transfer data length set with the CB0CTL2 register is input without writing to the CB0TX register, the INTCB0R signal is generated. Clear the CB0TSF bit to 0 to end transmission/reception.
Page 542: Reception Error
CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 13.4.13 Reception error When transfer is performed with reception enabled (CB0CTL0.CB0RXE bit = 1) in the continuous transfer mode, the reception error interrupt request signal (INTCB0RE) is generated when the next receive operation is completed before the CB0RX register is read after the reception end interrupt request signal (INTCB0R) is generated, and the overrun error flag (CB0STR.CB0OVE) is set to 1.
Page 543: Clock Timing
CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 13.4.14 Clock timing (1/2) (i) Communication type 1 (CB0CKP and CB0DAP bits = 00) SCKB0 pin SIB0 pin capture SOB0 pin Reg-R/W INTCB0T Note 1 interrupt INTCB0R Note 2 interrupt CB0TSF bit (ii) Communication type 3 (CB0CKP and CB0DAP bits = 10) SCKB0 pin SIB0 pin capture...
Page 544 CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2/2) (iii) Communication type 2 (CB0CKP and CB0DAP bits = 01) SCKB0 pin SIB0 pin capture SOB0 pin Reg-R/W INTCB0T Note 1 interrupt INTCB0R Note 2 interrupt CB0TSF bit (iv) Communication type 4 (CB0CKP and CB0DAP bits = 11) SCKB0 pin SIB0 pin capture...
Page 545: Output Pins
CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 13.5 Output Pins (1) SCKB0 pin When CSIB0 operation is disabled (CB0CTL0.CB0PWR bit = 0), the SCKB0 pin output status is as follows. CB0CKP CB0CKS2 CB0CKS1 CB0CKS0 SCKB0 Pin Output High impedance Other than above Fixed to high level High impedance Other than above...
Page 546: Chapter 14 Interrupt/Exception Processing Function
CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION The V850ES/IE2 is provided with a dedicated interrupt controller (INTC) for interrupt servicing and can process a total of 43 interrupt requests. An interrupt is an event that occurs independently of program execution, and an exception is an event whose occurrence is dependent on program execution.
Page 547 CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 14-1. Interrupt Source List (1/3) Type Classification Default Name Generating Source Generating Exception Handler Restored Interrupt Priority Unit Code Address Control Register − − Reset Interrupt RESET RESET pin input 0000H 00000000H Undefined WDT overflow (WDTRES) Low-voltage detection (LVIRES) POC/LVI −...
Page 548 CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 14-1. Interrupt Source List (2/3) Type Classification Default Name Generating Source Generating Exception Handler Restored Interrupt Priority Unit Code Address Control Register − − − − − − Maskable Interrupt Not used 000001E0H − −...
Page 549 CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 14-1. Interrupt Source List (3/3) Type Classification Default Name Generating Source Generating Exception Handler Restored Interrupt Priority Unit Code Address Control Register − − − − − − Maskable Interrupt Not used 000003D0H − −...
Page 550: Non-Maskable Interrupts
(DI) status. An NMI is not subject to priority control and takes precedence over all the other interrupt request signals. The non-maskable interrupt signal of the V850ES/IE2 is the non-maskable interrupt request signal generated by the overflow of the watchdog timer (INTWDT).
Page 551: Operation
CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION 14.2.1 Operation If a non-maskable interrupt request signal (INTWDT) is generated, the CPU performs the following processing, and transfers control to the handler routine. (1) Saves the restored PC to FEPC. (2) Saves the current PSW to FEPSW. (3) Writes the exception code (0010H) to the higher halfword (FECC) of ECR.
Page 552: Restore
CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION 14.2.2 Restore Execution is restored from non-maskable interrupt servicing by the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the address of the restored PC. <1>...
Page 553: Non-Maskable Interrupt Status Flag (Np)
CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION 14.2.3 Non-maskable interrupt status flag (NP) The NP flag is a status flag that indicates that non-maskable interrupt (INTWDT) servicing is in progress. The NP flag is allocated to the PSW. This flag is set when an INTWDT interrupt signal has been acknowledged, and masks all interrupt requests and exceptions to prohibit multiple interrupts from being acknowledged.
Page 554: Maskable Interrupts
CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION 14.3 Maskable Interrupts Maskable interrupt request signals can be masked by interrupt control registers. The V850ES/IE2 has 42 maskable interrupt sources. If two or more maskable interrupt request signals are generated at the same time, they are acknowledged according to the default priority.
Page 555 CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 14-3. Maskable Interrupt Servicing INT input INTC accepted xxIF = 1 Interrupt requested? xxMK = 0 Is the interrupt mask released? Priority higher than that of interrupt currently being serviced? Priority higher than that of other interrupt request? Highest default priority of interrupt requests...
Page 556: Restore
CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION 14.3.2 Restore Recovery from maskable interrupt servicing is carried out by the RETI instruction. When the RETI instruction is executed, the CPU performs the following steps, and transfers control to the address of the restored PC. <1>...
Page 557: Priorities Of Maskable Interrupts
CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION 14.3.3 Priorities of maskable interrupts The INTC provides multiple interrupt servicing in which an interrupt is acknowledged while another interrupt is being serviced. Multiple interrupts can be controlled by priority levels. There are two types of priority level control: control based on the default priority levels, and control based on the programmable priority levels that are specified by the interrupt priority level specification bit (xxPRn) of the interrupt control register (xxICn).
Page 558 CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 14-5. Example of Processing in Which Another Interrupt Request Signal Is Issued While an Interrupt Is Being Serviced (1/2) Main routine Servicing of a Servicing of b Interrupt Interrupt request a request b (level 3) Interrupt request b is acknowledged because the (level 2) priority of b is higher than that of a and interrupts are...
Page 559 CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 14-5. Example of Processing in Which Another Interrupt Request Signal Is Issued While an Interrupt Is Being Serviced (2/2) Main routine Servicing of i Servicing of k Interrupt request j Interrupt request i (level 3) (level 2) Interrupt request j is held pending because its Interrupt request k...
Page 560 CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 14-6. Example of Servicing Interrupt Request Signals Generated Simultaneously Main routine Interrupt request a (level 2) Interrupt request b (level 1) Servicing of interrupt request b Interrupt request b and c are Interrupt request c (level 1) acknowledged first according to their priorities.
Page 561: Interrupt Control Registers (Xxicn)
CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION 14.3.4 Interrupt control registers (xxICn) An xxICn register is assigned to each interrupt request signal (maskable interrupt) and sets the control conditions for each maskable interrupt request. These registers can be read or written in 8-bit or 1-bit units. Reset sets these registers to 47H.
Page 562 CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 14-2. Addresses and Bits of Interrupt Control Registers (1/2) Address Register <7> <6> FFFFF110H PIC0 PIF0 PMK0 PPR02 PPR01 PPR00 FFFFF112H PIC1 PIF1 PMK1 PPR12 PPR11 PPR10 FFFFF114H PIC2 PIF2 PMK2 PPR22 PPR21 PPR20 FFFFF116H PIC3 PIF3...
Page 563 CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 14-2. Addresses and Bits of Interrupt Control Registers (2/2) Address Register <7> <6> − − − − − − − − FFFFF162H Not used − − − − − − − − FFFFF164H Not used −...
Page 564: Interrupt Mask Registers 0 To 3 (Imr0 To Imr3)
CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION 14.3.5 Interrupt mask registers 0 to 3 (IMR0 to IMR3) The IMR0 to IMR3 registers set the interrupt mask state for the maskable interrupts. The IMR0.xxMKn to IMR3.xxMKn bits are equivalent to the xxICn.xxMKn bit. The IMRm register (m = 0 to 3) can be read or written in 16-bit units.
Page 565 CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION After reset: FFFFH Address: IMR3 FFFFF106H IMR3L FFFFF106H, IMR3H FFFFF107H Note IMR3 (IMR3H TM0EQMK0 AD1MK AD0MK UA1TMK UA1RMK UA1REMK CB0TMK CB0RMK (IMR3L) After reset: FFFFH Address: IMR2 FFFFF104H IMR2L FFFFF104H, IMR2H FFFFF105H Note IMR2 (IMR2H CB0REMK UA0TMK UA0RMK...
Page 566: In-Service Priority Register (Ispr)
CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION 14.3.6 In-service priority register (ISPR) The ISPR register holds the priority level of the maskable interrupt currently acknowledged. When an interrupt request signal is acknowledged, the bit of this register corresponding to the priority level of that interrupt signal request is set to 1 and remains set while the interrupt is serviced.
Page 567: Maskable Interrupt Status Flag (Id)
CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION 14.3.7 Maskable interrupt status flag (ID) The ID flag controls the maskable interrupt’s operating state, and stores control information regarding enabling or disabling of interrupt requests. The ID flag is allocated to the PSW. This flag is set to 00000020H after reset. After reset: 00000020H NP EP ID SAT CY OV...
Page 568: External Interrupt Request Input Pins (Intp0 To Intp6)
CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION 14.4 External Interrupt Request Input Pins (INTP0 to INTP6) 14.4.1 Noise elimination (1) Noise elimination of INTP0 to INTP5 pins The INTP0 to INTP5 pins incorporate a noise eliminator that uses analog delay. Unless, therefore, the input level of each pin is held for a certain time, an edge cannot be detected.
Page 569: Edge Detection
CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION 14.4.2 Edge detection The valid edges of the INTP0 to INTP6 pins can be selected by program. The edge that can be selected as the valid edge is one of the following. • Rising edge •...
Page 570: Software Exception
CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION 14.5 Software Exception A software exception is generated when the CPU executes the TRAP instruction, and can always be acknowledged. 14.5.1 Operation If a software exception occurs, the CPU performs the following processing, and transfers control to the handler routine.
Page 571: Restore
CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION 14.5.2 Restore Recovery from software exception processing is carried out by the RETI instruction. By executing the RETI instruction, the CPU carries out the following processing and shifts control to the restored PC’s address. <1> Loads the restored PC and PSW from EIPC and EIPSW because the PSW.EP bit is 1. <2>...
Page 572: Exception Status Flag (Ep)
CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION 14.5.3 Exception status flag (EP) The EP flag is a status flag used to indicate that exception processing is in progress. This flag is set when an exception occurs. The EP flag is allocated to the PSW. This flag is set to 00000020H after reset.
Page 573: Exception Trap
14.6 Exception Trap An exception trap is an interrupt that is requested when the illegal execution of an instruction takes place. In the V850ES/IE2, an illegal opcode trap (ILGOP: Illegal Opcode Trap) is considered as an exception trap. 14.6.1 Illegal opcode definition The illegal instruction has an opcode (bits 10 to 5) of 111111B, a sub-opcode (bits 26 to 23) of 0111B to 1111B, and a sub-opcode (bit 16) of 0B.
Page 574 CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 14-9. Exception Trap Processing Exception trap (ILGOP) occurs CPU processing DBPC Restored PC DBPSW PSW.NP PSW.EP PSW.ID 00000060H Exception processing (2) Restore Recovery from an exception trap is carried out by the DBRET instruction. By executing the DBRET instruction, the CPU carries out the following processing and controls the address of the restored PC.
Page 575: Debug Trap
CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION 14.6.2 Debug trap The debug trap is an exception that can be acknowledged anytime and is generated by execution of the DBTRAP instruction. When the debug trap is generated, the CPU performs the following processing. (1) Operation <1>...
Page 576 CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) Restore Recovery from a debug trap is carried out by the DBRET instruction. By executing the DBRET instruction, the CPU carries out the following processing and controls the address of the restored PC. <1> Loads the restored PC and PSW from DBPC and DBPSW. <2>...
Page 577: Multiple Interrupt Servicing Control
CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION 14.7 Multiple Interrupt Servicing Control Multiple interrupt servicing control is a process by which an interrupt request that is currently being serviced can be interrupted during servicing if there is an interrupt request signal with a higher priority level, and the higher priority interrupt request signal is acknowledged and serviced first.
Page 578 CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) Generation of exception in servicing program Servicing program of maskable interrupt or exception • EIPC saved to memory or register • EIPSW saved to memory or register • TRAP instruction ← Exception such as TRAP instruction acknowledged. •...
Page 579: Interrupt Response Time Of Cpu
CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION 14.8 Interrupt Response Time of CPU Except the following cases, the interrupt response time of the CPU is 4 clocks minimum. To input interrupt request signals successively, input the next interrupt request signal at least 4 clocks after the preceding interrupt. •...
Page 580: Periods In Which Cpu Does Not Acknowledge Interrupts
CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION 14.9 Periods in Which CPU Does Not Acknowledge Interrupts The CPU acknowledges an interrupt while an instruction is being executed. However, no interrupt will be acknowledged between an interrupt request non-sample instruction and the next instruction (interrupt is held pending). The interrupt request non-sample instructions are as follows.
Page 581: Chapter 15 Standby Function
CHAPTER 15 STANDBY FUNCTION 15.1 Overview The power consumption of the system can be effectively reduced by using the standby modes in combination and selecting the appropriate mode for the application. The available standby modes are listed in Table 15-1. Table 15-1.
Page 582 CHAPTER 15 STANDBY FUNCTION Figure 15-1. Status Transition Normal operation mode Note 5 Note 6 Note 5 Note 5 Setting of STOP mode Setting of HALT mode Setting of IDLE mode Note 1 Note 3 Interrupt request Interrupt request Wait for stabilization of Wait for stabilization of Wait for stabilization of (oscillation) and PLL...
Page 583: Control Registers
CHAPTER 15 STANDBY FUNCTION 15.2 Control Registers (1) Power save control register (PSC) The PSC register is an 8-bit register that controls the standby function. The STB bit of this register is used to specify the standby mode. This register is a special register (see 3.4.7 Special registers). This register can be written only by a combination of specific sequences.
Page 584 CHAPTER 15 STANDBY FUNCTION (2) Power save mode register (PSMR) The PSMR register is an 8-bit register that controls the operation in the software standby mode. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H Address: FFFFF820H <...
Page 585: Halt Mode
CHAPTER 15 STANDBY FUNCTION 15.3 HALT Mode 15.3.1 Setting and operation status The HALT mode is set when a dedicated instruction (HALT) is executed in the normal operation mode. When HALT mode is set, clock supply is stopped to the CPU only. The clock generator and PLL continue operating.
Page 586 CHAPTER 15 STANDBY FUNCTION (2) Releasing HALT mode by RESET pin input, WDTRES signal generation, LVIRES signal generation, or POCRES signal generation The same operation as the normal reset operation is performed. Table 15-3. Operation Status in HALT Mode Setting of HALT Mode Operation Status Item Clock generator, PLL...
Page 587: Idle Mode
CHAPTER 15 STANDBY FUNCTION 15.4 IDLE Mode 15.4.1 Setting and operation status The IDLE mode is set by clearing (0) the PSMR.PSM0 bit and setting (1) the PSC.STB bit in the normal operation mode. In the IDLE mode, the clock generator and PLL continue operation but clock supply to the CPU and other on-chip peripheral functions stops.
Page 588 CHAPTER 15 STANDBY FUNCTION (2) Releasing IDLE mode by RESET pin input, LVIRES signal generation, and POCRES signal generation The same operation as the normal reset operation is performed. Table 15-5. Operation Status in IDLE Mode Setting of IDLE Mode Operation Status Item Clock generator, PLL...
Page 589: Stop Mode
CHAPTER 15 STANDBY FUNCTION 15.5 STOP Mode 15.5.1 Setting and operation status The STOP mode is set by setting (1) the PSMR.PSM0 bit and setting (1) the PSC.STB bit in the normal operation mode. In the STOP mode, the clock generator stops operation. Clock supply to the CPU and the on-chip peripheral functions is stopped.
Page 590 CHAPTER 15 STANDBY FUNCTION Table 15-6. Operation After Releasing STOP Mode by Interrupt Request Signal Release Source Interrupt Enabled (EI) Status Interrupt Disabled (DI) Status Unmasked maskable interrupt request Execution branches to the handler The next instruction is executed after signal address or the next instruction is securing oscillation stabilization time...
Page 591: Securing Oscillation Stabilization Time
CHAPTER 15 STANDBY FUNCTION 15.6 Securing Oscillation Stabilization Time When the STOP mode is released, the oscillation stabilization time set by the OSTS register elapses. The oscillation stabilization time is the reset value of the OSTS register, 2 (26.2 ms at f = 2.5 MHz), if the STOP mode is released by reset signal (RESET pin input, reset signal generation by low-voltage detection (LVIRES), and reset signal generation by power-on clear (POCRES)).
Page 592: Chapter 16 Reset Functions
CHAPTER 16 RESET FUNCTIONS 16.1 Overview The following reset functions are available. • Reset by RESET pin input • Reset by watchdog timer overflow (WDTRES) • System reset by low-voltage detector (LVI) (LVIRES) • System reset by power-on-clear circuit (POC) (POCRES) 16.2 Registers to Check Reset Source (1) Reset source flag register (RESF) The RESF register is a special register that can be written only by a combination of specific sequences (see...
Page 593 CHAPTER 16 RESET FUNCTIONS (2) Reset source flag register 2 (RESF2) The RESF2 register indicates that a reset signal is generated by the low-voltage detector (LVI). This register is read-only, in 8-bit units. This register is cleared to 00H or set to 10H by RESET pin input and the power-on-clear circuit (POC). The default values are different when a reset is executed by other than these.
Page 594: Operation
CHAPTER 16 RESET FUNCTIONS 16.3 Operation 16.3.1 Reset operation via RESET pin When a low level is input to the RESET pin, the system is reset, and each hardware unit is initialized. When the level of the RESET pin is changed from low to high, the reset status is released. If the reset status is released by RESET pin input, the oscillation stabilization time of the oscillator elapses (reset value of OSTS register: 2 ) and then the CPU starts program execution.
Page 595 CHAPTER 16 RESET FUNCTIONS Figure 16-1. Timing of Reset Operation by RESET Pin Input Start operation at f RESET Analog delay Analog Analog delay Analog (eliminated delay (eliminated delay Counting of oscillation as noise) as noise) stabilization time Oscillation stabilization timer overflow Figure 16-2.
Page 596: Reset Operation By Watchdog Timer (Wdt) Overflow (Wdtres)
CHAPTER 16 RESET FUNCTIONS 16.3.2 Reset operation by watchdog timer (WDT) overflow (WDTRES) When the watchdog timer is set to the reset operation mode due to overflow, upon watchdog timer overflow (WDTRES signal generation), a system reset is executed and the hardware is initialized to the initial status. Following watchdog timer overflow, the reset status is entered and lasts the predetermined time (analog delay), and the reset status is then automatically released.
Page 597: Low-Voltage Detector (Lvi)
CHAPTER 16 RESET FUNCTIONS 16.3.3 Low-voltage detector (LVI) (1) Functions The low-voltage detector (LVI) has the following functions. • Compares the supply voltage (V ) and detection voltage (V ) and generates an interrupt request signal or internal reset signal when V <...
Page 598 CHAPTER 16 RESET FUNCTIONS (3) Control registers (a) Low-voltage detection register (LVIM) The LVIM register is used to enable or disable low voltage detection, and to set the operation mode of the low-voltage detector. The LVIM register is a special register. It can be written only by a combination of specific sequences (see 3.4.7 Special registers).
Page 599 CHAPTER 16 RESET FUNCTIONS (b) Low-voltage detection level select register (LVIS) The LVIS register is used to select the level of low voltage to be detected. This register can be read or written in 8-bit or 1-bit units. This register is cleared to 00H by a reset via RESET pin input, power-on-clear circuit (POC), and watchdog timer overflow.
Page 600 CHAPTER 16 RESET FUNCTIONS (c) Internal RAM data status register (RAMS) The RAMS register is a flag register that indicates whether the internal RAM is valid or not. The RAMS register is a special register. It can be written only by a combination of specific sequences (see 3.4.7 Special registers).
Page 601 CHAPTER 16 RESET FUNCTIONS (4) Operation Depending on the setting of the LVIM.LVIMD bit, an interrupt request signal (INTLVI) or an internal reset signal is generated. (a) To use for internal reset signal If the supply voltage falls below the voltage detected by the low-voltage detector when LVI operation is enabled, a system reset is executed (when the LVIM.LVIMD bit is set to 1), and the hardware is initialized to the initial status.
Page 602 CHAPTER 16 RESET FUNCTIONS Figure 16-5. Operation Timing of Low-Voltage Detector (LVIMD Bit = 1) Supply voltage (V LVI detection voltage POC detection voltage Time Set (by instruction, refer to <3> above) Clear (by POC reset request signal) LVION bit Delay Delay Delay...
Page 603 CHAPTER 16 RESET FUNCTIONS (b) To use for interrupt When the operation of LVI is enabled, the supply voltage and detection voltage are compared. If the supply voltage is lower than the detection voltage, an interrupt request signal (INTLVI) is generated (when the LVIM.LVIMD bit is cleared to 0).
Page 604 CHAPTER 16 RESET FUNCTIONS (5) RAM retention voltage detection operation = 2.0 V ±0.1 V) are compared. When the supply voltage The supply voltage and detection voltage (V RAMH drops below the detection voltage (including on power application), the RAMS.RAMF bit is set (1). Figure 16-7.
Page 605: Power-On-Clear Circuit (Poc)
CHAPTER 16 RESET FUNCTIONS 16.3.4 Power-on-clear circuit (POC) (1) Overview An overview of the power-on-clear (POC) circuit is shown below. • Generates a reset signal upon power application. • Compares the supply voltage (V ) and detection voltage (V ), and generates a reset signal when V <...
Page 606 CHAPTER 16 RESET FUNCTIONS (3) Operation When the supply voltage and detection voltage are compared and if the supply voltage is lower than the detection voltage (including at power application), the system is reset and each hardware is returned to the specific status.
Page 607: Chapter 17 Regulator
CHAPTER 17 REGULATOR 17.1 Overview The V850ES/IE2 includes a regulator to reduce power consumption and noise. This regulator supplies a stepped-down V power supply voltage to the oscillation block and internal logic circuits (except the A/D converter and I/O buffers). The regulator output voltage (REGC pin) is set to 2.5 V (TYP.).
Page 608: Operation
CHAPTER 17 REGULATOR 17.2 Operation The regulator of this product always operates in any mode (normal operation mode, HALT mode, IDLE mode, STOP mode, or during reset). μ Be sure to connect a capacitor (4.7 F (recommended value)) to the REGC pin to stabilize the regulator output. A diagram of the regulator pin connection method is shown below.
Page 609: Chapter 18 Flash Memory
Caution For the electrical specifications related to the flash memory rewriting, refer to CHAPTER 19 ELECTRICAL SPECIFICATIONS. The V850ES/IE2 is commonly used in the following development environments and mass production applications. For altering software after the V850ES/IE2 is soldered onto the target system.
Page 610: Memory Configuration
CHAPTER 18 FLASH MEMORY 18.2 Memory Configuration The 128 KB/64 KB internal flash memory area is divided into 4/2 blocks and can be programmed/erased in block units. All the blocks can also be erased at once. Figure 18-1. Flash Memory Mapping 3FFFFFFH Use prohibited (program fetch disabled area)
Page 611: Functional Overview
CHAPTER 18 FLASH MEMORY 18.3 Functional Overview The internal flash memory of the V850ES/IE2 can be rewritten by using the rewrite function of the dedicated flash memory programmer, regardless of whether the V850ES/IE2 has already been mounted on the target system or not (on-board/off-board programming).
Page 612 CHAPTER 18 FLASH MEMORY Table 18-2. Basic Functions Support (√: Supported, ×: Not supported) Function Functional Outline On-Board/Off-Board Self Programming Programming √ √ Block erasure The contents of specified memory blocks are erased. √ × Chip erasure The contents of the entire memory area are erased all at once.
Page 613 CHAPTER 18 FLASH MEMORY Table 18-4. Security Setting <R> Function Erase, Write, Read Operations When Each Security Is Set Notes on Security Setting (√: Executable, ×: Not Executable, −: Not Supported) On-Board/ Self Programming On-Board/ Self Off-Board Programming Programming Off-Board Programming Block erase command: ×...
Page 614 CHAPTER 18 FLASH MEMORY (1) Security setting by PG-FP4 and PG-FP5 (Security flag settings) <R> When disabling the read command (Disable Read), to raise the security level, it is recommended to also disable the block erase command (Disable Block Erase) and program command (Disable Program). Furthermore, when rewriting program is not necessary similarly to the mask ROM versions, additionally disable the chip erase command (Disable Chip Erase).
Page 615: Rewriting By Dedicated Flash Memory Programmer
18.4 Rewriting by Dedicated Flash Memory Programmer The flash memory can be rewritten by using a dedicated flash memory programmer after the V850ES/IE2 is mounted on the target system (on-board programming). The flash memory can also be rewritten before the device is mounted on the target system (off-board programming) by using a dedicated program adapter (FA series).
Page 616: Communication Mode
CHAPTER 18 FLASH MEMORY 18.4.2 Communication mode Communication between the dedicated flash memory programmer and the V850ES/IE2 is performed by serial communication using the UARTA0 or CSIB0 interfaces of the V850ES/IE2. (1) UARTA0 Transfer rate: 9,600 to 153,600 bps Figure 18-3. Communication with Dedicated Flash Memory Programmer (UARTA0)
Page 617 2. Connect this pin when power is supplied from PG-FP4 and PG-FP5. It does not have to be connected if an on-board power supply is used. 3. In the V850ES/IE2, external clock input is prohibited. Create an oscillator on board and supply the clock via that oscillator.
Page 618 CHAPTER 18 FLASH MEMORY Table 18-6. Wiring of V850ES/IE2 Flash Writing Adapters (FA-64GC-8BS-A) Flash Memory Programmer Name of FA CSIB0 + HS Used CSIB0 Used UARTA0 Used <R> (PG-FP4 and PG-FP5) Board Pin Connection Pin Signal Pin Function Pin Name Pin No.
Page 619 CHAPTER 18 FLASH MEMORY Figure 18-6. Wiring Example of V850ES/IE2 Flash Writing Adapter (FA-64GC-8BS-A) (1/2) Note 1 Note 2 μ PD70F3713, μ PD70F3714 Connect to GND. Connect to VDD. Note 3 μ 4.7 F VDD2 CLKIN X2 /RESET VPP RESERVE/HS...
Page 620 CHAPTER 18 FLASH MEMORY Figure 18-6. Wiring Example of V850ES/IE2 Flash Writing Adapter (FA-64GC-8BS-A) (2/2) Notes 1. Corresponding pins when UARTA0 is used. 2. Wire the FLMD1 pin as shown below, or connect it to GND on board via a pull-down resistor.
Page 621: Flash Memory Control
CHAPTER 18 FLASH MEMORY 18.4.3 Flash memory control The following shows the procedure for manipulating the flash memory. <R> Figure 18-7. Procedure for Manipulating Flash Memory Start Switch to flash memory programming mode Select communication system Supplies FLMD0 pulse Manipulate flash memory End? User’s Manual U17716EJ2V0UD...
Page 622: Selection Of Communication Mode
18.4.4 Selection of communication mode In the V850ES/IE2, the communication mode is selected by inputting pulses (11 pulses max.) to the FLMD0 pin after switching to the flash memory programming mode. The FLMD0 pulse is generated by the dedicated flash memory programmer.
Page 623: Communication Commands
Dedicated flash V850ES/IE2 memory programmer The following shows the commands for flash memory control in the V850ES/IE2. All of these commands are issued from the dedicated flash memory programmer, and the V850ES/IE2 performs the processing corresponding to the commands. Table 18-7. Flash Memory Control Commands...
Page 624: Pin Connection
FLMD0 pin via port control, etc., before writing to the flash memory. For details, see 18.5.5 (1) FLMD0 pin. Figure 18-10. FLMD0 Pin Connection Example V850ES/IE2 Dedicated flash memory programmer connection pin FLMD0 Pull-down resistor (R FLMD0 User’s Manual U17716EJ2V0UD...
Page 625 0 V must be input to the FLMD1 pin. The following shows an example of the connection of the FLMD1 pin. Figure 18-11. FLMD1 Pin Connection Example V850ES/IE2 FLMD1 Other device...
Page 626 (output), a conflict of signals occurs. To avoid the conflict of signals, isolate the connection to the other device or set the other device to the output high-impedance status. Figure 18-12. Conflict of Signals (Serial Interface Input Pin) V850ES/IE2 Dedicated flash memory programmer connection pins...
Page 627 Dedicated flash memory programmer connection pin Other device Input pin In the flash memory programming mode, if the signal the V850ES/IE2 outputs affects the other device, isolate the signal on the other device side. V850ES/IE2 Dedicated flash memory programmer connection pin...
Page 628 When a reset signal is input from the user system in the flash memory programming mode, the programming operation will not be performed correctly. Therefore, do not input signals other than the reset signals from the dedicated flash memory programmer. Figure 18-14. Conflict of Signals (RESET Pin) V850ES/IE2 Dedicated flash memory programmer connection pin Conflict of signals...
Page 629: Rewriting By Self Programming ( Μ Pd70F3714 Only)
18.5.1 Overview The V850ES/IE2 supports a flash macro service that allows the user program to rewrite the internal flash memory by itself. By using this interface and a self programming library that is used to rewrite the flash memory with a user application program, the flash memory can be rewritten by a user application transferred in advance to the internal RAM or external memory.
Page 630: Features
Instructions cannot be fetched from the flash memory during self programming. Conventionally, therefore, a user handler written to the flash memory could not be used even if an interrupt occurred. With the V850ES/IE2, a user handler can be registered to an entry RAM area by using a library function, so that interrupt servicing can be performed by internal RAM or external memory execution.
Page 631: Standard Self Programming Flow
CHAPTER 18 FLASH MEMORY 18.5.3 Standard self programming flow The entire processing to rewrite the flash memory by flash self programming is illustrated below. <R> Figure 18-17. Standard Self Programming Flow (a) When rewriting at once (b) When rewriting in block units Flash memory manipulation Flash memory manipulation Flash environment...
Page 632: Flash Functions
CHAPTER 18 FLASH MEMORY 18.5.4 Flash functions <R> Table 18-10. Flash Function List Function Name Outline Support √ FlashEnv Initialization of flash control macro √ FlashBlockErase Erasure of only specified one block √ FlashWordWrite Writing from specified address √ FlashBlockIVerify Internal verification of specified block √...
Page 633: Internal Resources Used
CHAPTER 18 FLASH MEMORY 18.5.6 Internal resources used The following table lists the internal resources used for self programming. These internal resources can also be used freely for purposes other than self programming. Table 18-11. Internal Resources Used Resource Name Description Entry RAM area Routines and parameters used for the flash macro service are located in this area.
Page 634: Chapter 19 Electrical Specifications
CHAPTER 19 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (T = 25°C) Parameter Symbol Conditions Ratings Unit −0.5 to +6.5 Supply voltage = EV −0.5 to +0.5 = EV = AV = AV −0.5 to +6.5 = EV −0.5 to +0.5 = EV = AV = AV −0.5 to +6.5...
Page 635 CHAPTER 19 ELECTRICAL SPECIFICATIONS Cautions 1. Do not directly connect the output (or I/O) pins of IC products to each other, or to V , EV and GND. Open-drain pins or open-collector pins, however, can be directly connected to each other.
Page 636 2. Do not route signal lines through the area enclosed by broken lines. 3. The duty factor of the oscillation waveform must be within 45% to 55%. 4. Inputting an external clock to the V850ES/IE2 is prohibited. = −40 to +85°C) <R>...
Page 637 CHAPTER 19 ELECTRICAL SPECIFICATIONS DC Characteristics = −40 to +85°C, V = EV = 3.5 to 5.5 V, AV = AV = 4.5 to 5.5 V, V = EV = AV = AV = 0 V) (1/2) Parameter Symbol Conditions MIN.
Page 638 CHAPTER 19 ELECTRICAL SPECIFICATIONS DC Characteristics = −40 to +85°C, V = EV = 3.5 to 5.5 V, AV = AV = 4.5 to 5.5 V, V = EV = AV = AV = 0 V) (2/2) Note 2 Parameter Symbol Conditions MIN.
Page 639 CHAPTER 19 ELECTRICAL SPECIFICATIONS Data Retention Characteristics = −40 to +85°C, V STOP Mode (T = EV = AV = AV = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Data retention voltage In STOP mode , EV Note DDDR After reset other , EV...
Page 640 CHAPTER 19 ELECTRICAL SPECIFICATIONS AC Characteristics AC Test Input Measurement Points Measurement points AC Test Output Measurement Points Measurement points Load Conditions (device under measurement) = 50 pF Caution If the load capacitance exceeds 50 pF due to the circuit configuration, bring the load capacitance of the device to 50 pF or less by inserting a buffer or by some other means.
Page 641 CHAPTER 19 ELECTRICAL SPECIFICATIONS Output Signal Timing = −40 to +85°C, V = EV = 3.5 to 5.5 V, V = EV = 0 V, C = 50 pF) Parameter Symbol Conditions MIN. MAX. Unit Output rise time <1> Output fall time <2>...
Page 642 CHAPTER 19 ELECTRICAL SPECIFICATIONS Reset, External Interrupt Timing = −40 to +85°C, V = EV = 3.5 to 5.5 V, V = EV = 0 V, C = 50 pF) Parameter Symbol Conditions MIN. MAX. Unit RESET low-level width <3> WRSL RESET high-level width <4>...
Page 643 CHAPTER 19 ELECTRICAL SPECIFICATIONS Timer Timing = −40 to +85°C, V = EV = 3.5 to 5.5 V, V = EV = 0 V, C = 50 pF) Parameter Symbol Conditions MIN. MAX. Unit Note 1 TIn high-level width <7> 10T + 10 WTIHn Note 1...
Page 644 CHAPTER 19 ELECTRICAL SPECIFICATIONS CSIB Timing (1) Master mode = −40 to +85°C, V = EV = 3.5 to 5.5 V, V = EV = 0 V, C = 50 pF) Parameter Symbol Conditions MIN. MAX. Unit SCKB0 cycle <11> KCYM /2 −...
Page 645 CHAPTER 19 ELECTRICAL SPECIFICATIONS CSIB Timing: CB0CTL1.CB0CKP, CB0CTL1.CB0DAP Bits = 00 <11>, <17> <12>, <18> <12>, <18> SCKB0 (I/O) <13>, <14>, <19> <20> SIB0 (input) Input data <15>, <21> <16>, <22> SOB0 (output) Output data Remark The broken lines indicate high impedance. CSIB Timing: CB0CTL1.CB0CKP, CB0CTL1.CB0DAP Bits = 01 <11>, <17>...
Page 646 CHAPTER 19 ELECTRICAL SPECIFICATIONS CSIB Timing: CB0CTL1.CB0CKP, CB0CTL1.CB0DAP Bits = 10 <11>, <17> <12>, <18> <12>, <18> SCKB0 (I/O) <13>, <14>, <19> <20> SIB0 (input) Input data <15>, <21> <16>, <22> SOB0 (output) Output data Remark The broken lines indicate high impedance. CSIB Timing: CB0CTL1.CB0CKP, CB0CTL1.CB0DAP Bits = 11 <11>, <17>...
Page 647 CHAPTER 19 ELECTRICAL SPECIFICATIONS Characteristics of A/D Converters 0, 1 = −40 to +85°C, V = EV = 4.5 to 5.5 V, AV = AV = 4.5 to 5.5 V, V = EV = AV = AV = 0 V, C 50 pF) Parameter Symbol...
Page 648 CHAPTER 19 ELECTRICAL SPECIFICATIONS Power-on-Clear Circuit (POC) = −40 to +85°C, V = EV = 3.5 to 5.5 V, V = EV = 0 V, C = 50 pF) Parameter Symbol Conditions MIN. TYP. MAX. Unit POC detection voltage POC0 Supply voltage rise time <23>...
Page 649 CHAPTER 19 ELECTRICAL SPECIFICATIONS Low-Voltage Detector (LVI) = −40 to +85°C, V = EV = 3.5 to 5.5 V, V = EV = 0 V, C = 50 pF) Parameter Symbol Conditions MIN. TYP. MAX. Unit LVI detection voltage LVIS.LVIS0 bit = 0 LVI0 LVIS.LVIS0 bit = 1 LVI1...
Page 650 CHAPTER 19 ELECTRICAL SPECIFICATIONS RAM Retention Voltage Detection = −40 to +85°C, V = EV = 3.5 to 5.5 V, V = EV = 0 V, C = 50 pF) Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage RAMH Supply voltage rise time <30>...
Page 651 CHAPTER 19 ELECTRICAL SPECIFICATIONS Flash Memory Programming Characteristics = −40 to +85°C, V = EV = 3.5 to 5.5 V, V = EV = 0 V, C = 50 pF) (1) Basic characteristics Parameter Symbol Conditions MIN. TYP. MAX. Unit Operating frequency Supply voltage Rewrite time...
Page 652 CHAPTER 19 ELECTRICAL SPECIFICATIONS <R> (3) Programming characteristics Parameter Symbol Conditions TYP. TYP.-Worst MAX. Unit Block erase = 20 MHz, 8 KB 0.78 5.78 = 20 MHz, 56 KB 35.0 Write (128 bytes) = 20 MHz 43.1 Block internal verify = 20 MHz, 8 KB 80.3 3000...
Page 653: Chapter 20 Package Drawing
CHAPTER 20 PACKAGE DRAWING 64-PIN PLASTIC LQFP (14x14) detail of lead end ITEM MILLIMETERS 17.2±0.2 14.0±0.2 14.0±0.2 17.2±0.2 0.37 +0.08 −0.07 0.20 0.8 (T.P.) 1.6±0.2 NOTE 0.17 +0.03 Each lead centerline is located within 0.20 mm of −0.06 its true position (T.P.) at maximum material condition. 0.10 1.4±0.1 0.127±0.075...
Page 654: Chapter 21 Recommended Soldering Conditions
<R> CHAPTER 21 RECOMMENDED SOLDERING CONDITIONS These products should be soldered and mounted under the following recommended conditions. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) Table 21-1. Surface Mounting Type Soldering Conditions μ 64-pin plastic LQFP (14 × 14) PD70F3713GC-8BS-A: μ...
Page 655: Appendix A Cautions
APPENDIX A CAUTIONS A.1 Restriction on Conflict Between sld Instruction and Interrupt Request A.1.1 Description If a conflict occurs between the decode operation of an instruction in <2> immediately before the sld instruction following an instruction in <1> and an interrupt request before the instruction in <1> is complete, the execution result of the instruction in <1>...
Page 656: Appendix B Register Index
APPENDIX B REGISTER INDEX (1/5) Symbol Name Unit Page AD0IC Interrupt control register INTC AD1IC Interrupt control register INTC ADA0CR0 A/D0 conversion result register 0 ADC0 ADA0CR0H A/D0 conversion result register 0H ADC0 ADA0CR1 A/D0 conversion result register 1 ADC0 ADA0CR1H A/D0 conversion result register 1H ADC0...
Page 657 APPENDIX B REGISTER INDEX (2/5) Symbol Name Unit Page HZA1CTL0 High-impedance output control register 10 Timer HZA1CTL1 High-impedance output control register 11 Timer IMR0 Interrupt mask register 0 INTC IMR0H Interrupt mask register 0H INTC IMR0L Interrupt mask register 0L INTC IMR1 Interrupt mask register 1...
Page 658 APPENDIX B REGISTER INDEX (3/5) Symbol Name Unit Page Port 1 mode register Port Port 2 mode register Port Port 3 mode register Port Port 4 mode register Port PMC0 Port 0 mode control register Port PMC1 Port 1 mode control register Port PMC2 Port 2 mode control register...
Page 659 APPENDIX B REGISTER INDEX (4/5) Symbol Name Unit Page TP1CCR1 TMP1 capture/compare register 1 Timer TP1CNT TMP1 counter read buffer register Timer TP1CTL0 TMP1 control register 0 Timer TP1CTL1 TMP1 control register 1 Timer TP1OPT0 TMP1 option register 0 Timer TP1OVIC Interrupt control register INTC...
Page 660 APPENDIX B REGISTER INDEX (5/5) Symbol Name Unit Page TQ0OVIC Interrupt control register INTC TQ1CCIC0 Interrupt control register INTC TQ1CCIC1 Interrupt control register INTC TQ1CCIC2 Interrupt control register INTC TQ1CCIC3 Interrupt control register INTC TQ1CCR0 TMQ1 capture/compare register 0 Timer TQ1CCR1 TMQ1 capture/compare register 1 Timer...
Page 661: Appendix C Instruction Set List
APPENDIX C INSTRUCTION SET LIST C.1 Conventions (1) Register symbols used to describe operands Register Symbol Explanation reg1 General-purpose registers: Used as source registers. reg2 General-purpose registers: Used mainly as destination registers. Also used as source register in some instructions. reg3 General-purpose registers: Used mainly to store the remainders of division results and the higher 32 bits of multiplication results.
Page 662 APPENDIX C INSTRUCTION SET LIST (3) Register symbols used in operations Register Symbol Explanation ← Input for GR [ ] General-purpose register SR [ ] System register zero-extend (n) Expand n with zeros until word length. sign-extend (n) Expand n with signs until word length. load-memory (a, b) Read size b data from address a.
Page 663 APPENDIX C INSTRUCTION SET LIST (5) Register symbols used in flag operations Identifier Explanation (Blank) No change Clear to 0 × Set or cleared in accordance with the results. Previously saved values are restored. (6) Condition codes Condition Name Condition Code Condition Formula Explanation (cond)
Page 664: Instruction Set (In Alphabetical Order)
APPENDIX C INSTRUCTION SET LIST C.2 Instruction Set (in Alphabetical Order) (1/6) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV S Z SAT × × × × reg1,reg2 r r rr r0 01 11 0 RRRRR GR[reg2]←GR[reg2]+GR[reg1] × × ×...
Page 665 APPENDIX C INSTRUCTION SET LIST (2/6) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV S Z SAT DBTRAP 1111100001000000 DBPC←PC+2 (restored PC) DBPSW←PSW PSW.NP←1 PSW.EP←1 PSW.ID←1 PC←00000060H 0000011111100000 PSW.ID←1 0000000101100000 DISPOSE imm5,list12 0 0 0 0 0 1 1 0 0 1 i i i i i L sp←sp+zero-extend(imm5 logically shift left by 2) LLLLLLLLLLL00000 GR[reg in list12]←Load-memory(sp,Word)
Page 666 APPENDIX C INSTRUCTION SET LIST (3/6) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV S Z SAT LD.H disp16[reg1],reg2 rrrrr111001RRRRR adr←GR[reg1]+sign-extend(disp16) Note ddddddddddddddd0 GR[reg2]←sign-extend(Load-memory(adr,Halfword)) Note 8 LDSR reg2,regID rrrrr111111RRRRR SR[regID]←GR[reg2] Other than regID = PSW 0000000000100000 × × × ×...
Page 667 APPENDIX C INSTRUCTION SET LIST (4/6) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV S Z SAT × × reg1,reg2 r r rr r0 01 00 0 RRRRR GR[reg2]←GR[reg2]OR GR[reg1] × × imm16,reg1,reg2 r r rr r1 10 10 0 RRRRR GR[reg2]←GR[reg1]OR zero-extend(imm16) i i i i i i i i i i i i i i i i PREPARE...
Page 668 APPENDIX C INSTRUCTION SET LIST (5/6) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV S Z SAT × SET1 bit#3,disp16[reg1] 00bbb111110RRRRR adr←GR[reg1]+sign-extend(disp16) dddddddddddddddd Z flag←Not (Load-memory-bit(adr,bit#3)) Note 3 Note 3 Note 3 Store-memory-bit(adr,bit#3,1) × reg2,[reg1] r r rr r1 11 11 1 RRRRR adr←GR[reg1] Z flag←Not(Load-memory-bit(adr,reg2)) 0000000011100000...
Page 669 APPENDIX C INSTRUCTION SET LIST (6/6) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV S Z SAT × × × × reg1,reg2 r r rr r0 01 10 1 RRRRR GR[reg2]←GR[reg2]–GR[reg1] × × × × SUBR reg1,reg2 r r rr r0 01 10 0 RRRRR GR[reg2]←GR[reg1]–GR[reg2] SWITCH reg1 00000000010RRRRR adr←(PC+2) + (GR [reg1] logically shift left by 1)
Page 670 APPENDIX C INSTRUCTION SET LIST Notes 12. In this instruction, for convenience of mnemonic description, the source register is made reg2, but the reg1 field is used in the opcode. Therefore, the meaning of register specification in the mnemonic description and in the opcode differs from other instructions. r r r r r = regID specification RRRRR = reg2 specification...
Page 671: Appendix D Revision History
<R> APPENDIX D REVISION HISTORY D.1 Major Revisions in This Edition (1/3) Page Description • Change of under development state of all products → Development completed Throughout • Addition of PG-FP5 p. 23 Addition of description to 2.1 (1) Port pins p.
Page 672 APPENDIX D REVISION HISTORY (2/3) Page Description p. 213 Modification of description in 6.6.5 (2) (b) 0%/100% output of PWM waveform p. 232 Modification of description in Figure 6-41 Configuration in Pulse Width Measurement Mode p. 233 Modification of description in 6.6.7 Pulse width measurement mode (TPkMD2 to TPkMD0 bits = 110) pp.
Page 673 APPENDIX D REVISION HISTORY (3/3) Page Description p. 581 Addition of description to 15.2 (1) Power save control register (PSC) p. 587 Addition of description to 15.5.1 Setting and operation status p. 590 Addition of description to 16.2 (1) Reset source flag register (RESF) p.
Page 674 For further information, please contact: NEC Electronics Corporation 1753, Shimonumabe, Nakahara-ku, Kawasaki, Kanagawa 211-8668, Japan Tel: 044-435-5111 http://www.necel.com/ [Asia & Oceania] [America] [Europe] NEC Electronics (China) Co., Ltd NEC Electronics America, Inc. NEC Electronics (Europe) GmbH 7th Floor, Quantum Plaza, No. 27 ZhiChunLu Haidian 2880 Scott Blvd.

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