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M16C/64A Group
25.4
Interrupts
2
The I
C interface generates interrupt requests. Figure 25.21 shows I
2
25.16 lists I
C-bus Interrupts.
2
I
C-bus Interrupt
ACKCLK bit in the S20 register
Falling edge of the last bit clock
of transmit/receive data detected
Falling edge of the ACK
clock detected
WIT bit in the S3D0 register
Falling edge of the last bit clock
of received data detected
TRX bit in the S10 register
MST bit in the S10 register
ASL bit in the S1D0 register
AAS bit in the S10 register
ADR0 bit in the S10 register
Slave address reception
completed
Slave address transmission
completed
SIM bit in the S3D0 register
Stop condition detected
TOE bit in the S4D0 register
Timeout detected
SCL/SDA Interrupt
SCLMM
SDAMM
2
Figure 25.21 I
C Interface Interrupts
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
(Data transmit/receive
completed)
(Data received)
S2D0 register
SIS = 1
SIS = 0
2
C Interface Interrupts, and Table
(Slave address match
detected)
(General call detected)
(Slave address reception
completed with free data
format)
SCPIN bit in the S4D0 register
(Stop condition detected)
TOF bit in the S4D0 register
(Timeout detected)
SIP bit in the
S2D0 register
Edge selector
2
25. Multi-master I
C-bus Interface
PIN
2
I
C-bus interrupt
request (to the IR bit
in the IICIC register)
SCL/SDA interrupt
request (to IR bit in the
SCLDAIC register)
Page 576 of 800
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