Saving Registers - Renesas M16C/64A Series User Manual

M16C/64A Group
14.7.5

Saving Registers

In the interrupt sequence, the FLG register and PC are saved on the stack.
At this time, the 4 upper bits of the PC and the 4 upper (IPL) and 8 lower bits in the FLG register, 16 bits
in total, are saved on the stack first. Next, the 16 lower bits of the PC are saved. Figure 14.5 shows the
Stack Status Before and After Acceptance of Interrupt Request.
The other necessary registers must be saved by a program at the beginning of the interrupt routine.
Use the PUSHM instruction, and all registers except SP can be saved with a single instruction.
Address Stack
MSB
m - 4
m - 3
m - 2
m - 1
m Contents of previous stack
Contents of previous stack
m + 1
Stack status
before interrupt request is acknowledged
Figure 14.5 Stack Status Before and After Acceptance of Interrupt Request
The register save operation carried out in the interrupt sequence is dependent on whether the SP
the time of acceptance of an interrupt request, is even or odd. If the SP
the PC are saved 16 bits at a time. If odd, they are saved in two steps, 8 bits at a time. Figure 14.6
shows the Register Save Operation.
Note:
1. When an INT instruction with software numbers 32 to 63 has been executed, it is the SP indicated
by the U flag. Otherwise, it is the ISP.
(1) SP contains even number
Address Stack
[SP] - 5 (Odd)
[SP] - 4 (Even)
[SP] - 3 (Odd)
[SP] - 2 (Even)
[SP] - 1 (Odd)
FLGH
[SP] (Even)
Note:
1. [SP] denotes the initial value of the SP when an interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4.
Figure 14.6 Register Save Operation
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
LSB
[SP]
SP value before
interrupt request is accepted.
Sequence in which
registers are saved
PCL
(2) All 16 bits saved
simultaneously
PCM
FLGL
(1) All 16 bits saved
simultaneously
PCH
Completed saving registers
in two operations.
Address
Stack
MSB
m - 4
PCL
m - 3
PCM
m - 2
FLGL
m - 1
FLGH PCH
m Contents of previous stack
Contents of previous stack
m + 1
Stack status
after interrupt request is acknowledged
(1)
(2) SP contains odd number
Address Stack
[SP] - 5 (Even)
[SP] - 4 (Odd)
PCL
[SP] - 3 (Even)
PCM
[SP] - 2 (Odd)
FLGL
[SP] - 1 (Even)
FLGH
[SP] (Odd)
14. Interrupts
LSB
[SP]
New SP value
PCL: 8 lower bits of PC
PCM: 8 middle bits of PC
PCH: 4 upper bits of PC
FLGL: 8 lower bits of FLG
FLGH : 4 upper bits of FLG
is even, the FLG register and
Sequence in which
registers are saved
(3)
(4)
Saved 8 bits
at a time
(1)
PCH
(2)
Completed saving registers
in four operations.
PCL: 8 lower bits of PC
PCM: 8 middle bits of PC
PCH: 4 upper bits of PC
FLGL : 8 lower bits of FLG
FLGH: 4 upper bits of FLG
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