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M16C/64A Group
11.3.5.9
Software Wait States
The PM17 bit in the PM1 register, which is a software-wait-related bit, affects both the internal
memory and the external area.
Software wait states can be inserted to the external area by setting the PM17 bit, setting the CSiW bit
in the CSR register, and bits CSEi1W to CSEi0W in the CSE register for each CSi (i = 0 to 3). To use
the RDY signal, set the corresponding CSiW bit to 0 (wait state). See Table 11.10 "Bits and Bus
Cycles Related to Software Wait States (External Area)" for details.
Table 11.10
Bits and Bus Cycles Related to Software Wait States (External Area)
Area
Bus Mode
External
Separate
area
bus
Multiplexed
bus
i = 0 to 3
− indicates that either 0 or 1 can be set.
PM17: Bit in the PM1 register
CSiW: Bits in the CSR register
CSEi1W, CSEi0W: Bits in the CSE register
Notes:
To use the RDY signal, set the CSiW bit to 0 (wait state).
1.
2.
To access in multiplexed bus mode, set the CSiW bit to 0 (wait state).
3.
To access an external area when the PM17 bit is 1, set the CSiW bit to 0 (wait state).
4.
After reset, the PM17 bit is set to 0 (no wait state), bits CS0W to CS3W are set to 0 (wait
state), and the CSE register is set to 00h (one wait state for CS0 to CS3 ). Therefore, all
external areas are accessed with one wait state.
5.
When setting one wait in multiplexed bus, the bus cycle is the same as two waits.
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
Setting of Software-Wait-Related Bits Software
PM17
CSiW
0
1
-
0
-
0
-
0
1
(3)
0
-
(2)
0
-
(2)
0
-
(2)
0
1
(2), (3)
0
(1)
Wait
CSEi1W to
Cycles
CSEi0W
00b
None
1 (1 φ + 1 φ )
00b
2 (1 φ + 2 φ )
01b
3 (1 φ + 3 φ )
10b
1 (1 φ + 1 φ )
00b
00b
(5)
1
01b
2
10b
3
00b
(5)
1
11. Bus
Bus Cycles
1 BCLK cycle
(read)
2 BCLK cycles
(write)
(4)
2 BCLK cycles
3 BCLK cycles
4 BCLK cycles
2 BCLK cycles
3 BCLK cycles
3 BCLK cycles
4 BCLK cycles
3 BCLK cycles
Page 150 of 800
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