Renesas M16C/64A Series User Manual page 834

1. Items revised or added in this version
REVISION HISTORY
Rev. Date
Page
2.10 Jul 31, 2012 Resets
46
54
54
59
59
Clock Generator
84
86
98
Processor Mode
132
133
Bus
148
Programmable I/O Ports
173, 174 Figure 13.8 I/O Ports (N-channel Open Drain Output), Figure 13.9 I/O Ports (NMI):
Three-Phase Motor Control Timer Function
327, 347,
352
Remote Control Signal Receiver
417
432
447
Serial Interface UARTi (i = 0 to 2, 5 to 7)
456
457, 461
487
Multi-master I
579
CRC Calculator
654
656
Flash Memory
661
688
Usage Notes
753
753
779
M16C/64A Group User's Manual: Hardware
6.2.1 Processor Mode Register 0 (PM0):
Added the description regarding PM02, PM04 to PM07 to the register explanation.
6.4.3 Power-On Reset Function: Changed "the rise gradient is trth or more" to "the rise gradient is
trth" in the second line of the first paragraph.
Figure 6.5 Power-On Reset Circuit and Operation Example: Changed tw(por1) to tw(por).
6.5.4 Hardware Reset when VCC1 < Vdet0: Rewritten.
Figure 6.9 Hardware Reset when VCC1 < Vdet0: Added.
Figure 8.1 System Clock Generator:
Changed a part of the configuration in the PLL frequency synthesizer.
8.2.1 Processor Mode Register 0 (PM0):
Added the description regarding PM02, PM04 to PM07 to the register explanation.
8.3.4 Sub Clock (fC): Deleted P8_5 in the parenthesis in step (1).
10.2.1 Processor Mode Register 0 (PM0):
Added the description regarding PM02, PM04 to PM07 to the register explanation.
10.2.2 Processor Mode Register 1 (PM1):
Added the description regarding PM11, PM14 and PM15 to the register explanation.
Table 11.8 Pin Functions for Each Processor Mode:
• Added note 7.
• Changed the Memory Expansion Mode column for P3_0.
Partially modified.
Table 19.2 Three-Phase Motor Control Timer Function Specifications (2/2), Table 19.9 Three-
Phase Mode 0 Specifications, and Table 19.12 Three-Phase Mode 1 Specifications:
Modified the Specification column of the Three-phase PWM output width.
Figure 22.4 Setting Values of the Header Pattern and Data Patterns: Added the explanation.
Table 22.12 Registers and Setting Values in Pattern Match Mode (Combined Operation) (1/2)
Changed the PMC1 column of the PMCiCON1 register for bits TYP0 and TYP1.
22.5.4 Combined Operation: Added.
23.2.2 UARTi Transmit/Receive Mode Register (UiMR) (i = 0 to 2, 5 to 7):
Added the description regarding I
23.2.4 UARTi Transmit Buffer Register (UiTB) (i = 0 to 2, 5 to 7), 23.2.7 UARTi Receive Buffer
Register (UiRB) (i = 0 to 2, 5 to 7): Modified the Reset Value.
Table 23.15 I/O Pin Functions in I
2
C-bus Interface
25.5.3 Low/High-level Input Voltage and Low-level Output Voltage: Added.
29.2.3 CRC Data Register (CRCD): Added the explanation.
Figure 29.2 CRC Calculation When Using CRC-CCITT and Figure 29.3 CRC Calculation When
Using CRC-16: Changed.
30.3.1 Flash Memory Control Register 0 (FMR0):
Changed the description of steps in the FMSTP bit explanation.
30.8.6.2 Handling Procedure for Errors: Added note 1 for (2) in the Erase error and Program error.
32.4.4 Hardware Reset when VCC1 < Vdet0: Rewritten.
Figure 32.4 Hardware Reset when VCC1 < Vdet0: Added.
32.16.4 Combined Operation: Added.
Description
Summary
2
C mode.
2
C Mode: Added note 1.
C - 1
(1)
: