Table of Contents
Advertisement
M16C/64A Group
TBiIN input
Count operations
0000h
TBiS bit in the
TABSR register or
TBSR register
IR bit
in the TBiIC register
i = 0 to 5
The above assumes the following:
•
Bits MR1 to MR0 in the TBiMR register = 10b (the falling edge and rising edge of an external signal).
•
The TCK1 bit in the TBiMR register = 0 (input signals from the TBiIN pin counted).
•
The value in the TBi register (n) = 0004h.
Figure 18.5
Operation Example in Event Counter Mode
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
Count start
n
Underflow
and reload
n+1
Set to 0 by accepting an interrupt request, or by a program.
18. Timer B
Count stop
by TBiS bit
Page 317 of 800
Advertisement
Table of Contents
