Renesas M16C/64A Series User Manual page 508

M16C/64A Group
23.3.1.4 Serial Data Logic Switching Function
When the UiLCH bit in the UiC1 register (i = 0 to 2, 5 to 7) is 1 (inverted), the data written to the UiTB
register has its logic inverted before being transmitted. Similarly, the inverted data has its logic inverted
when read from the UiRB register. Figure 23.9 shows Serial Data Logic.
(1) UiLCH bit in the UiC1 register is 0 (not inverted)
Transmit/receive clock
(2) UiLCH bit in the UiC1 register is 1 (inverted)
Transmit/receive clock
i = 0 to 2, 5 to 7
The above assumes the following:
• The CKPOL bit in the UiC0 register is 0 (transmit data output at the falling edge of the
transmit/receive clock).
• The UFORM bit in the UiC0 register is 0 (LSB first).
Figure 23.9 Serial Data Logic
23.3.1.5 Transmit/Receive Clock Output from Multiple Pins (UART1)
Use bits CLKMD1 to CLKMD0 in the UCON register to select one of the two transmit/receive clock
output pins (see Figure 23.10). This function can be used when the selected transmit/receive clock
for UART1 is an internal clock.
MCU
TXD1 (P6_7)
CLKS1 (P6_4)
CLK1 (P6_5)
The above diagram assumes the following:
The CKDIR bit in the U1MR register is 0 (internal clock).
The CLKMD1 bit in the UCON register is 1 (transmit/receive clock output from multiple pins).
Figure 23.10 Transmit/Receive Clock Output from Multiple Pins
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
High
Low
High
TXDi
(not inverted)
Low
High
Low
High
TXDi
(inverted)
Low
IN
CLK
Transmit/receive enabled when the
CLKMD0 bit in the UCON register is 0
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
D0 D1 D2 D3 D4
D0 D1 D2 D3 D4
IN
CLK
Transmit/receive enabled when the
CLKMD0 bit in the UCON register is 1
D5 D6 D7
D5 D6 D7
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