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M16C/64A Group
(1) Separate Bus, Three Wait States (1φ + 3φ)
BCLK
Address
CSi
Data
RD
WR , WRL , WRH
(2) Multiplexed Bus, One or Two Wait States (1φ + 2φ)
BCLK
Address
Address/Data
ALE
CSi
RD
WR , WRL , WRH
(3) Multiplexed Bus, Three Wait States (1φ + 3φ)
BCLK
Address
Address/Data
ALE
CSi
RD
WR , WRL , WRH
i = 0 to 3
A: Address
Note:
1. When consecutively accessing the same chip-select area, CSi continues outputting a low level.
Figure 11.7
Typical Bus Timings Using Software Wait States (2/2)
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
Bus cycle = 4φ
A
WD
Bus cycle = 3φ
A
A
WD
Bus cycle = 4φ
A
A
WD
RD: Read data (input)
WD: Write data (output)
Bus cycle = 4φ
A
Bus cycle = 3φ
A
A
RD
(Note 1)
Bus cycle = 4φ
A
A
11. Bus
(Note 1)
RD
RD
(Note 1)
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