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M16C/64A Group
25.3.1.2
Bit Rate and Duty Cycle
Bit rate is determined by a combination of fVIIC, the FASTMODE bit in the S20 register, and bits
CCR4 to CCR0 in the S20 register.
Table 25.11 lists the Bit Rate of Internal SCL Output and Duty Cycle. When the change in the internal
SCL output high level is a negative value, although the low period increases the amount that the high
periods decreases, the bit rate does not increase. The values described is the following table are the
values of the internal SCL output before being effected by the SCL output of an external device.
Table 25.11
Bit Rate of Internal SCL Output and Duty Cycle
Item
-------------------------------------- -
Bit rate (bps)
8 CCR value
50%
Duty cycle
Fluctuation of high level:
-4 to +2 fVIIC cycles
CCR value: Value set to bits CCR4 to CCR0
When the CCR value (setting value of bits CCR4 to CCR0) is 5 (00101b) in fast-mode, the bit rate is
assumed to reach 400 kbps, the maximum bit rate in fast-mode.
The bit rate and duty cycle are as follows.
•
Bit rate:
VIIC
f
-------------------------------------- -
×
2
CCR value
When fVIIC is 4 MHz, the bit rate is 400 kbps.
•
Duty cycle is 35 to 45%
Even if the bit rate is 400 kbps, the 1.3 μ s minimum low period of the SCLMM clock (I
is allocated. Table 25.12 lists the Bit Setting for Bits CCR4 to CCR0 and Bit Rate (fVIIC = 4 MHz).
Table 25.12
Bit Setting for Bits CCR4 to CCR0 and Bit Rate (fVIIC = 4 MHz)
Bits CCR4 to CCR0 in the S20 Register
CCR4
CCR3
CCR2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
:
:
:
1
1
1
1
1
1
1
1
1
Notes:
1.
Do not set bits CCR4 to CCR0 to 0 to 2 regardless of the fVIIC frequency.
2.
Do not exceed the maximum bit rates of 100 kbps in standard clock mode and 400 kbps in fast-
mode.
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
Standard Clock Mode
(FASTMODE = 0)
fVIIC
×
fVIIC
=
-------------- -
10
CCR1
CCR0
0
0
0
1
1
0
1
1
0
0
0
1
1
0
:
:
0
1
1
0
1
1
Fast-mode
(FASTMODE = 1)
(CCR value = other than 5)
fVIIC
-------------------------------------- -
×
4 CCR value
50%
Fluctuation of high level:
-2 to +2 fVIIC cycles
Bit Rate (kbps)
Standard Clock Mode
(1)
Do not set
(1)
Do not set
(1)
Do not set
(2)
Do not set
(2)
Do not set
100
83.3
:
17.2
16.6
16.1
2
25. Multi-master I
C-bus Interface
Fast-mode
(FASTMODE = 1)
(CCR value = 5)
fVIIC
fVIIC
--------------
------------------------------------- -
=
×
2 CCRvalue
10
35 to 45%
2
C-bus standard)
Fast-mode
(1)
Do not set
(1)
Do not set
(1)
Do not set
333
250
400
166
:
34.5
33.3
32.3
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