Operations; Count Source Protection Mode Disabled - Renesas M16C/64A Series User Manual

M16C/64A Group
15.4

Operations

15.4.1

Count Source Protection Mode Disabled

The CPU clock is used as the watchdog timer count source when count source protection mode is
disabled.
Table 15.3 lists Watchdog Timer Specifications (Count Source Protection Mode Disabled).
Table 15.3 Watchdog Timer Specifications (Count Source Protection Mode Disabled)
Item
Count source
Count operation
Cycles
Watchdog timer
counter refresh
timing
Count start
conditions
Count stop
conditions
Operation when
timer underflows
Note:
1. When writing 00h and then FFh to the WDTR register, the watchdog timer is refreshed, but the
prescaler is not initialized. Thus, some errors in the watchdog timer period may be caused by the
prescaler. The prescaler is initialized after reset.
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
CPU clock
Decrement
When the CM07 bit in the CM0 register is 0 (main clock, PLL clock, fOCO-S):
Prescaler divide value (n) watchdog timer count value (32768)
------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -
n: 16 or 128 (selected by the WDC7 bit in the WDC register)
Example: When CPU clock frequency is 16 MHz and the prescaler division rate is
16, the watchdog timer cycle is approximately 32.8 ms.
When the CM07 bit is 1 (sub clock):
Prescaler divide value (2) watchdog timer count value (32768)
------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -
•
Reset (refer to 6. "Resets")
•
Write 00h, and then FFh to the WDTR register.
•
Underflow
Set the WDTON bit in the OFS1 address to select the watchdog timer operation
after reset.
•
WDTON bit is 1 (watchdog timer is in stop state after reset)
The watchdog timer counter and prescaler stop after reset and count starts by
writing to the WDTS register.
•
WDTON bit is 0 (watchdog timer starts automatically after reset)
The watchdog timer counter and prescaler start counting automatically after reset.
•
Stop mode
•
Wait mode
•
Bus hold
(Count resumes from the hold value after exiting.)
•
PM12 bit in the PM1 register is 0
Watchdog timer interrupt
•
PM12 bit in the PM1 register is 1
Watchdog timer reset (Refer to 6.4.8 "Watchdog Timer Reset".)
Specification
×
CPU clock
×
CPU clock
15. Watchdog Timer
(1)
(1)
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