Internal Clock - Renesas M16C/64A Series User Manual

M16C/64A Group
24.3.4

Internal Clock

When the SMi6 bit in the SiC register is 1, data is transmitted/received using the internal clock. The
internal clock is selected by setting the PCLK1 bit in the PCLKR register and bits SMi1 to SMi0 in the
SiC register.
When the internal clock is used as the transmit/receive clock, the SOUTi pin becomes high-impedance
from when the SMi3 bit in the SiC register is set to 1 (SI/Oi enabled) and the SMi2 bit is set to 0 (SOUTi
output enabled) to when the first data is output.
When writing transmit data to the SiTRR register, data transmission/reception starts by outputting the
transmit/receive clock from the CLKi pin after waiting between 0.5 to 1.0 cycles of the transmit/receive
clock. After 8 bits of data have been transmitted/received, the transmit/receive clock from the CLKi pin
stops.
Figure 24.4 shows SI/Oi Operation Timing (Internal Clock).
SI/Oi internal clock
CLKi output
Write signal to the
SiTRR register
SOUTi output
SINi input
IR bit in the SiIC
register
i = 3, 4
The above diagram assumes the following:
In the SiC register, SMi2 = 0 (SOUTi output), SMi3 = 1 (SOUTi output, CLKi function), SMi4 = 0 (transmit data is output at
a falling edge of the transmit/receive clock, and receive data is input at a rising edge), SMi5 = 0 (LSB first), SMi6 = 1
(internal clock).
In the S34C2 register, the SM26 bit (SOUT3) or SM27 bit (SOUT4) = 0 (high-impedance after transmission).
Figure 24.4 SI/Oi Operation Timing (Internal Clock)
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
Transmission/reception starts after waiting between 0.5 to 1.0 cycles of
transmit/receive clock by writing to the SiTRR register.
Hi-Z
D0 D1
D0 D1
24. Serial Interface SI/O3 and SI/O4
D2 D3 D4
D3 D4
D2
Hi-Z
D5 D6 D7
D5 D6 D7
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