Renesas M16C/64A Series User Manual page 278

M16C/64A Group
(1) Transfers are performed in 8-bit or 16-bit units, and the transfer source is an even address.
BCLK
Address
CPU use
bus
RD signal
WR signal
Data bus
(2) Transfers are performed in 16-bit units, and the transfer source is an odd address.
BCLK
Address
CPU used
bus
RD signal
WR signal
Data bus
(3) Conditions listed in (1) with one wait inserted in the source read cycle.
BCLK
Address
CPU used
bus
RD signal
WR signal
Data bus
(4) Conditions listed in (2) with one wait inserted in the source read cycle.
BCLK
Address
CPU use
bus
RD signal
WR signal
Data bus
Note:
1. The same timing changes occur with the respective conditions at the destination as at the source.
Figure 16.2 Source Read Cycle Example
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
Source
CPU use Source
Source Source + 1
Source
CPU used
Source
CPU used
Source
Source
CPU used Source
Dummy
Destination
cycle
Dummy
Destination
cycle
Dummy
Destination
cycle
Source + 1
Destination
Dummy
Destination
cycle
Destination
Source + 1
Source + 1
CPU use
CPU use
CPU used
Dummy
CPU used
cycle
CPU used
Dummy
CPU used
cycle
Dummy
Destination
cycle
Dummy
Destination
cycle
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16. DMAC
CPU use
CPU used