Renesas M16C/64A Series User Manual page 446

M16C/64A Group
CPFLG (Compare match flag) (b0)
This bit is enabled when the CPEN bit in the PMC0CPC register is set to 1 (compare enabled).
Conditions to become 0:
•
When the EN bit in the PMCiCON0 register is 0 (PMCi operation disabled).
•
When the DRFLG bit in the PMC0STS register changes from 0 to 1 (next frame reception starts).
•
When the 48th bit is received after the CPFLG bit becomes 1, and then (the DRFLG bit remains 1
(receiving)) no compare match occurs after receiving bit n (n = value set by bits CPN2 to CPN0 in
the PMC0CPC register).
Condition to become 1:
•
The PMC0CPD register matches the PMC0DAT0 register (when the setting value of bits CPN2 to
CPN0 in the PMC0CPC register is n, bits n to 0 in the PMC0CPD register match bits n to 0 in the
PMC0DAT0 register).
REFLG (Receive error flag) (b1)
The REFLG bit is a flag indicating a receive error. Conditions for changing the REFLG bit are affected
by the HDEN bit in the PMCiCON0 register and bits EHOLD and SDEN in the PMC0CON0 register.
Table 22.5 lists Conditions for Changing the REFLG Bit.
Table 22.5 Conditions for Changing the REFLG Bit
(1)
Bit Setting
EHOLD HDEN
0 0
0 1
1 0
1 1
EHOLD: Bit in the PMC0CON0 register
HDEN: Bit in the PMCiCON0 register (i = 0, 1)
Notes:
1. For the REFLG bit of PMC1, refer to settings where the EHOLD bit is 0.
2. Special data is added to the conditions when the SDEN bit in the PMC0CON0 register is 1
(special data pattern enabled).
3. The REFLG bit becomes 0 regardless of bits HDEN and EHOLD under the following conditions:
•
The EN bit in the PMCiCON0 register is 0 (PMCi stops).
•
The DRFLG bit in the PMCiSTS register changes from 0 to 1.
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
Conditions for Changing the REFLG Bit
(2)
to 1
Input signal width is not data 0 or data 1
(or special data)
•
Input signal width is not the header,
data 0, or data 1 (or special data)
•
Detect data 0 or data 1 (or special
data) prior to header
Input signal width is not data 0 or data 1
(or special data)
•
Input signal width is not the header,
data 0, or data 1 (or special data)
•
Detect data 0 or data 1 (or special
data) prior to header
22. Remote Control Signal Receiver
Conditions for Changing the REFLG bit
(2, 3)
to 0
Receive data 0 or data 1 (or special
data)
•
Receive header
•
Receive header prior to data 0 or data
1 (or special data)
-
•
Receive header
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