Renesas M16C/64A Series User Manual page 532

M16C/64A Group
23.3.3.7 SDA Digital Delay
When transferring data with the I 2 C-bus, change the data while the SCL clock is low. When SDA is
changed while the SCL clock is a high, the change is recognized as one of the corresponding
conditions (see 23.5.3.4 "Setup and Hold Times When Generating a Start/Stop Condition").
This function delays output from the SDAi pin. By delaying the change of the SDA, the data can be
changed while the SCL clock is low. This function is enabled by setting bits DL2 to DL0 in the UiSMR3
register to 001b to 111b, and disabled by setting them to 000b.
SCL
UiBRG
count source
When DL2 to DL0 are 000b (no delay)
SDA
When DL2 to DL0 are 001b (1 to 2 cycles of UiBRG count source)
SDA
When DL2 to DL0 are 111b (7 to 8 cycles of UiBRG count source)
SDA
DL2 to DL0: Bits in the UiSMR3 register
Figure 23.29 SDA Output Selection by Setting Bits DL2 to DL0
23.3.3.8 SDA Input
When the IICM2 bit in the UiSMR2 register (i = 0 to 2, 5 to 7) is set to 0, the first 8 bits of received data
(D7 to D0) are stored in bits 7 to 0 in the UiRB register and the ninth bit (ACK/NACK) is stored in bit 8.
When the IICM2 bit is 1, the first to seventh bits (D7 to D1) of the received data are stored in bits 6 to 0
in the UiRB register and the eighth bit (D0) is stored in bit 8 in the UiRB register. Even when the IICM2
bit is 1, if the CKPH bit in the UiSMR3 register is 1, the same data as when the IICM2 bit is 0 can be
read. To read the data, read the UiRB register after the rising edge of ninth bit of the corresponding
clock pulse.
When receiving byte data, the SDAi pin is released for the first to eighth bits to receive data, and an
acknowledgment is generated for the ninth bit. NACK is generated when the last byte data is received
in master mode, or when the slave address does not match in slave mode. In all other cases, ACK is
generated.
2
In I C mode, set 9-bit data to the UiTB register. In 9-bit data, set FFh to b7 to b0 to release the SDAi pin
and set b8 to 0 to generate ACK or 1 to generate NACK.
By setting 00FFh or 01FFh as 9-bit data to the UiTB register, the SDAi pin becomes high-impedance for
the first to eighth bits, and data can be received. ACK or NACK is generated at the ninth bit.
Read the received data from the UiRB register. When the clock delay function is used, data transfer to
the UiRB register occurs twice and each UiRB register value is different. Refer to Figure 23.20
"Transfer to UiRB Register and Interrupt Timing" for details.
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
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23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
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