Renesas M16C/64A Series User Manual page 578

M16C/64A Group
WIT (Data receive interrupt enable bit) (b1)
The WIT bit is enabled in master reception or slave reception.
The WIT bit has two functions:
•
Selects the I
•
Monitors the state of the internal WAIT flag. (read)
The WIT bit can select whether to generate an I
clock) during the data reception.
When the ACKCLK bit in the S20 register is 1 (ACK clock presents) and the WIT bit is set to 1 (enable
2
I C-bus interrupt at 8th clock), an I
ACK clock). Then, the PIN bit in the S10 register becomes 0 (interrupt requested).
When the ACKCLK bit in the S20 register is 0 (no ACK clock presents), write 0 to the WIT bit to disable
2
the I C-bus interrupt by data reception.
When transmitting data and receiving a slave address, no interrupt requests are generated at the eighth
clock (before the ACK clock) regardless of the value written to the WIT bit.
Reading the WIT bit returns the internal WAIT flag status.
2
An I C-bus interrupt request is generated at the falling edge of the ninth clock (ACK clock) regardless of
the value written to the WIT bit. Then, the PIN bit in the S10 register becomes 0 (interrupt requested).
Therefore, read the internal WAIT flag status to determine whether the I
generated at the eighth clock (before the ACK clock) or at the falling edge of the ACK clock.
When the WIT bit is set to 1 (I
changes under the following conditions:
Condition to become 0:
•
The S20 register (ACKBIT bit) is written.
Condition to become 1:
•
The S00 register is written during data reception.
When transmitting data and receiving a slave address, the internal WAIT flag is 0 and the I
interrupt request will be generated only at the falling edge of the ninth clock (ACK clock), regardless of
the value written to the WIT bit.
Table 25.6 lists interrupt request generation timing and the conditions to restart transmission/reception
when receiving data. Figure 25.4 shows Interrupt Request Generation Timing in Receive Mode.
Table 25.6 Generating an Interrupt Request and Restarting Transmission/Reception When
Receiving Data
2
I C-bus Interrupt Request Generation Timing
At the falling edge of the eighth clock
(before the ACK clock)
At the falling edge of the ninth clock
(2)
(ACK clock)
Notes:
1. See the timing of (1) on the IR bit in the IICIC register in Figure 25.4.
2. See the timing of (2) on the IR bit in the IICIC register in Figure 25.4.
3. When setting the ACKBIT bit, do not rewrite any other bits and do not set the S00 register.
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
2
C-bus interrupt timing when data is received. (write)
2
C-bus interrupt request is generated at the eighth clock (before the
2
C-bus interrupt enabled by receiving data), the internal WAIT flag
(1)
25. Multi-master I
2
C-bus interrupt request at eighth clock (before ACK
Internal WAIT
Flag Status
Write to the ACKBIT bit in the S20
1
register
0 Write to the S00 register
2
C-bus Interface
2
C-bus interrupt request is
Conditions to Restart
Transmission/Reception
(3)
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C-bus