Renesas M16C/64A Series User Manual

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RENESAS MCU

M16C Family / M16C/60 Series

All information contained in these materials, including products and product specifications, represents

information on the product at the time of publication and is subject to change by Renesas Electronics

Corp. without notice. Please review the latest information published by Renesas Electronics Corp.

through various means, including the Renesas Electronics Corp. website (http://www.renesas.com).

www.renesas.com

User's Manual: Hardware

M16C/64A Group

User's Manual: Hardware

Rev.2.10

Jul 2012

Table of Contents

Summary of Contents for Renesas M16C/64A Series

Page 1 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp.
Page 2 Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures.
Page 3 General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence.
Page 4 For details, please refer to the relative chapters or sections of this manual. The M16C/64A Group includes the documents listed below. Verify this manual is the latest version by visiting the Renesas Electronics website. Type of Document Contents...
Page 5 Numbers and Symbols The following explains the denotations used in this manual for registers, bits, pins and various numbers. (1) Registers, bits, and pins Registers, bits, and pins are indicated by symbols. Each symbol has a register/bit/pin identifier after the symbol. Example: PM03 bit in the PM0 register P3_5 pin, VCC pin (2) Numbers...
Page 6 Registers The following illustration describes registers used throughout this manual. See Note 1 Example Register See Note 2 b7 b6 b5 b4 b3 b2 b1 Symbol Address Reset Value EXAMPLE 9999h 000X 1X00b Bit Symbol Bit Name Description b2 b1 AAAA0 0 0 : XX function Example bit 0...
Page 7 Abbreviations and Acronyms The following acronyms and terms are used throughout this manual. Abbreviation/Acronym Meaning ACIA Asynchronous Communication Interface Adapter bits per second Cyclic Redundancy Check Direct Memory Access DMAC Direct Memory Access Controller Global System for Mobile Communications Hi-Z High Impedance IEBus Inter Equipment Bus...
Page 8: Table Of Contents
Table of Contents Quick Reference .......................B-1 Overview........................1 Features............................1 1.1.1 Applications ......................... 1 Specifications..........................2 Product List..........................4 Block Diagram ..........................6 Pin Assignments ........................... 7 Pin Functions ..........................11 Central Processing Unit (CPU) .................. 14 Data Registers (R0, R1, R2, and R3) ..................15 Address Registers (A0 and A1) ....................
Page 9 Register ............................40 5.2.1 Protect Register (PRCR) ....................40 Notes on Protection ........................42 Resets........................43 Introduction ..........................43 Registers............................. 45 6.2.1 Processor Mode Register 0 (PM0) ..................46 6.2.2 Reset Source Determine Register (RSTFR) ..............47 Optional Function Select Area ....................48 6.3.1 Optional Function Select Address 1 (OFS1) ..............
Page 10 7.4.2 Voltage Detector 0 ......................74 7.4.3 Voltage Detector 1 ......................76 7.4.4 Voltage Detector 2 ......................79 Interrupts............................. 82 Clock Generator......................83 Introduction ..........................83 Registers............................. 85 8.2.1 Processor Mode Register 0 (PM0) ..................86 8.2.2 System Clock Control Register 0 (CM0) ................87 8.2.3 System Clock Control Register 1 (CM1) ................
Page 11 9.2.2 Flash Memory Control Register 2 (FMR2) ...............112 Clock............................114 9.3.1 Normal Operating Mode ....................114 9.3.2 Clock Mode Transition Procedure ..................118 9.3.3 Wait Mode ........................121 9.3.4 Stop Mode ........................123 Power Control in Flash Memory ....................125 9.4.1 Stopping Flash Memory ....................125 9.4.2 Reading Flash Memory ....................
Page 12 11.4 Notes on Bus ..........................153 11.4.1 Reading Data Flash ......................153 11.4.2 External Bus ........................153 11.4.3 External Access Immediately after Writing to the SFRs ..........153 HOLD ..........................153 11.4.4 12. Memory Space Expansion Function ................ 154 12.1 Introduction ..........................
Page 13 14.2.3 Interrupt Control Register 2 (INT7IC, INT6IC, INT3IC, S4IC/INT5IC, S3IC/INT4IC, INT0IC to INT2IC) ..... 196 14.2.4 Interrupt Source Select Register 3 (IFSR3A) ..............197 14.2.5 Interrupt Source Select Register 2 (IFSR2A) ..............198 14.2.6 Interrupt Source Select Register (IFSR) ................199 14.2.7 Address Match Interrupt Enable Register (AIER) ............
Page 14 14.13.4 Changing an Interrupt Source ..................221 14.13.5 Rewriting the Interrupt Control Register ................222 14.13.6 Instruction to Rewrite the Interrupt Control Register ............222 INT Interrupt ........................223 14.13.7 15. Watchdog Timer....................... 224 15.1 Introduction ..........................224 15.2 Registers........................... 225 15.2.1 Voltage Monitor 2 Control Register (VW2C) ..............
Page 15 17. Timer A ........................252 17.1 Introduction ..........................252 17.2 Registers........................... 255 17.2.1 Peripheral Clock Select Register (PCLKR) ..............256 17.2.2 Clock Prescaler Reset Flag (CPSRF) ................256 17.2.3 Timer A Count Source Select Register i (TACSi) (i = 0 to 2) ........... 257 17.2.4 16-bit Pulse Width Modulation Mode Function Select Register (PWMFS) ......
Page 16 18.2.6 Timer B Count Source Select Register i (TBCSi) (i = 0 to 3) ........... 308 18.2.7 Count Start Flag (TABSR) Timer B3/B4/B5 Count Start Flag (TBSR) ............... 309 18.2.8 Timer Bi Mode Register (TBiMR) (i = 0 to 5) ..............310 18.3 Operations ..........................311 18.3.1...
Page 17 20. Real-Time Clock ...................... 366 20.1 Introduction ..........................366 20.2 Registers........................... 368 20.2.1 Real-Time Clock Second Data Register (RTCSEC) ............369 20.2.2 Real-Time Clock Minute Data Register (RTCMIN) ............370 20.2.3 Real-Time Clock Hour Data Register (RTCHR) .............. 371 20.2.4 Real-Time Clock Day Data Register (RTCWK) ...............
Page 18 22.2.6 PMCi Interrupt Source Register (PMCiINT) (i = 0, 1) ............415 22.2.7 PMCi Header Pattern Set Register (MIN) (PMCiHDPMIN) (i = 0, 1) PMCi Header Pattern Set Register (MAX) (PMCiHDPMAX) (i = 0, 1) ......416 22.2.8 PMCi Data 0 Pattern Set Register (MIN) (PMCiD0PMIN) (i = 0, 1) PMCi Data 0 Pattern Set Register (MAX) (PMCiD0PMAX) (i = 0, 1) PMCi Data 1 Pattern Set Register (MIN) (PMCiD1PMIN) (i = 0, 1) PMCi Data 1 Pattern Set Register (MAX) (PMCiD1PMAX) (i = 0, 1) ......
Page 19 23.3.3 Special Mode 1 (I C Mode) ..................... 486 23.3.4 Special Mode 2 ....................... 501 23.3.5 Special Mode 3 (IE Mode) ....................505 23.3.6 Special Mode 4 (SIM Mode) (UART2) ................507 23.4 Interrupts........................... 512 23.4.1 Interrupt Related Registers ..................... 512 23.4.2 Reception Interrupt ......................
Page 20 25.2.1 Peripheral Clock Select Register (PCLKR) ..............536 25.2.2 I2C0 Data Shift Register (S00) ..................537 25.2.3 I2C0 Address Register i (S0Di) (i = 0 to 2) ..............538 25.2.4 I2C0 Control Register 0 (S1D0) ..................539 25.2.5 I2C0 Clock Control Register (S20) .................. 541 25.2.6 I2C0 Start/Stop Condition Control Register (S2D0) ............
Page 21 26.2.11 CEC Receive Follower Address Set Register 1 (CRADRI1), CEC Receive Follower Address Set Register 2 (CRADRI2) ........... 596 26.2.12 Port Control Register (PCR) .................... 597 26.3 Operations ..........................598 26.3.1 Standard Value and I/O Timing ..................598 26.3.2 Count Source ........................598 26.3.3 CEC Input/Output ......................
Page 22 27.7.3 Pin Configuration ......................645 27.7.4 Register Access ......................645 27.7.5 A/D Conversion Start ....................... 645 27.7.6 A/D Operation Mode Change ..................645 27.7.7 State When Forcibly Terminated ..................646 27.7.8 A/D Open-Circuit Detection Assist Function ..............646 27.7.9 Detecting Completion of A/D Conversion ................ 646 27.7.10 Repeat Mode, Repeat Sweep Mode 0, and Repeat Sweep Mode 1 .......
Page 23 30.7.1 User Boot Function ......................669 30.8 CPU Rewrite Mode ........................673 30.8.1 EW0 Mode ........................674 30.8.2 EW1 Mode ........................676 30.8.3 Operating Speed ......................678 30.8.4 Data Protect Function ...................... 678 30.8.5 Software Commands ....................... 679 30.8.6 Status Register ........................ 686 30.9 Standard Serial I/O Mode ......................
Page 24 31.3.4 Switching Characteristics (Memory Expansion Mode and Microprocessor Mode) ..741 32. Usage Notes ......................748 32.1 Notes on Noise ......................... 748 32.2 Notes on SFRs ......................... 749 32.2.1 Register Settings ......................749 32.3 Notes on Protection ........................751 32.4 Notes on Resets ........................
Page 25 32.10 Notes on the Watchdog Timer ....................767 32.11 Notes on DMAC........................768 32.11.1 Write to the DMAE Bit in the DMiCON Register (i = 0 to 3) ..........768 32.11.2 Changing the DMA Request Source ................768 32.12 Notes on Timer A........................769 32.12.1 Common Notes on Multiple Modes .................
Page 26 32.19 Notes on Multi-master I C-bus Interface .................. 785 32.19.1 Limitation on CPU Clock ....................785 32.19.2 Register Access ......................785 32.19.3 Low/High-level Input Voltage and Low-level Output Voltage ........... 785 32.19.4 Generating Stop Condition ....................786 32.20 Notes on CEC........................... 788 32.20.1 Registers and Bit Operation ....................
Page 27: Quick Reference
Quick Reference Only one page number is listed for each register. Refer to the REGISTER INDEX for more details. Address Register Symbol Page Address Register Symbol Page SI/O3 Interrupt Control Register S3IC 0000h 0049h INT4 Interrupt Control Register INT4IC 0001h UART2 Bus Collision Detection Interrupt 004Ah BCNIC...
Page 28 Address Register Symbol Page Address Register Symbol Page 01C0h 0080h Timer B0-1 Register TB01 01C1h 017Fh 01C2h 0180h Timer B1-1 Register TB11 01C3h 0181h DMA0 Source Pointer SAR0 01C4h 0182h Timer B2-1 Register TB21 01C5h 0183h Pulse Period/Pulse Width Measurement 01C6h PPWFS1 0184h...
Page 29 Address Register Symbol Page Address Register Symbol Page 0200h 0244h UART0 Special Mode Register 4 U0SMR4 0201h 0245h UART0 Special Mode Register 3 U0SMR3 0202h 0246h UART0 Special Mode Register 2 U0SMR2 0203h 0247h UART0 Special Mode Register U0SMR 0204h 0248h UART0 Transmit/Receive Mode Register U0MR...
Page 30 Address Register Symbol Page Address Register Symbol Page 0288h UART5 Transmit/Receive Mode Register U5MR 0300h Timer B3/B4/B5 Count Start Flag TBSR 0289h UART5 Bit Rate Register U5BRG 0301h 028Ah 0302h UART5 Transmit Buffer Register U5TB Timer A1-1 Register TA11 028Bh 0303h 028Ch UART5 Transmit/Receive Control Register 0...
Page 31 Address Register Symbol Page Address Register Symbol Page 033Bh Timer B0 Mode Register TB0MR 0377h 033Ch Timer B1 Mode Register TB1MR 0378h 033Dh Timer B2 Mode Register TB2MR 0379h 033Eh Timer B2 Special Mode Register TB2SC 037Ah 033Fh 037Bh 0340h Real-Time Clock Second Data Register RTCSEC 037Ch...
Page 32 Address Register Symbol Page Address Register Symbol Page 03B3h 03F0h Port P8 Register 03B4h 03F1h Port P9 Register SFR Snoop Address Register CRCSAR 03B5h 03F2h Port P8 Direction Register 03B6h CRC Mode Register CRCMR 03F3h Port P9 Direction Register 03B7h 03F4h Port P10 Register 03B8h...
Page 33 Address Register Symbol Page D080h PMC0 Header Pattern Set Register (Min) PMC0HDPMIN D081h D082h PMC0 Header Pattern Set Register (Max) PMC0HDPMAX D083h D084h PMC0 Data 0 Pattern Set Register (Min) PMC0D0PMIN D085h PMC0 Data 0 Pattern Set Register (Max) PMC0D0PMAX D086h PMC0 Data 1 Pattern Set Register (Min) PMC0D1PMIN...
Page 34: Overview
M16C/64A Group R01UH0136EJ0210 RENESAS MCU Rev.2.10 Jul 31, 2012 Overview Features The M16C/64A Group microcomputer (MCU) incorporates the M16C/60 Series CPU core and flash memory, employing sophisticated instructions for a high level of efficiency. This MCU has 1 MB of address space (expandable to 4 MB), and it is capable of executing instructions at high speed.
Page 35: Specifications
M16C/64A Group 1. Overview Specifications The M16C/64A Group includes 100-pin package. Table 1.1 and Table 1.2 list specifications. Table 1.1 Specifications for the 100-Pin Package (1/2) Item Function Description M16C/60 Series core (multiplier: 16 bit × 16 bit 32 bit, multiply and accumulate instruction: 16 bit ×...
Page 36 M16C/64A Group 1. Overview Table 1.2 Specifications for the 100-Pin Package (2/2) Item Function Description 16-bit timer × 5 Timer mode, event counter mode, one-shot timer mode, pulse width modulation (PWM) mode Timer A Event counter two-phase pulse signal processing (two-phase encoder input) ×...
Page 37: Product List
M16C/64A Group 1. Overview Product List Table 1.3 lists product information. Figure 1.1 shows the Part No., with Memory Size and Package, and Figure 1.2 shows the Marking Diagram (Top View). Table 1.3 Product List As of July 2012 ROM Capacity Part No.
Page 38 M: 512 KB/31 KB M16C/64A Group (100 pins) 16-bit MCU Memory type F: Flash memory Renesas MCU Renesas semiconductor Figure 1.1 Part No., with Memory Size and Package M 1 6 C R 5 F 3 6 4 A 6 D F A (See Figure 1.1 “Part No., with Memory Size and Package”)
Page 39: Block Diagram
M16C/64A Group 1. Overview Block Diagram Figure 1.3 shows block diagram. Port P0 Port P1 Port P2 Port P3 Port P4 Port P5 VCC2 ports Internal peripheral functions System clock generator UART or clock synchronous serial I/O Timer (16 bit) XIN-XOUT (6 channels) XCIN-XCOUT...
Page 40: Pin Assignments
M16C/64A Group 1. Overview Pin Assignments Figure 1.4 and Figure 1.5 show pin assignments. Table 1.4 and Table 1.5 list pin names. See Note 3 P4_4/CTS7/RTS7/CS0 P0_7/AN0_7/D7 VCC2 ports P4_5/CLK7/CS1 P0_6/AN0_6/D6 P4_6/PWM0/RXD7/SCL7/CS2 P0_5/AN0_5/D5 P4_7/PWM1/TXD7/SDA7/CS3 P0_4/AN0_4/D4 P5_0/WRL/WR P0_3/AN0_3/D3 M16C/64A Group P5_1/WRH/BHE P0_2/AN0_2/D2 P5_2/RD P0_1/AN0_1/D1...
Page 41 M16C/64A Group 1. Overview See Note 3 P1_2/RXD6/SCL6/D10 P4_2/A18 P1_1/CLK6/D9 P4_3/A19 P1_0/CTS6/RTS6/D8 VCC2 ports P4_4/CTS7/RTS7/CS0 P0_7/AN0_7/D7 P4_5/CLK7/CS1 P0_6/AN0_6/D6 P4_6/PWM0/RXD7/SCL7/CS2 P0_5/AN0_5/D5 P4_7/PWM1/TXD7/SDA7/CS3 P0_4/AN0_4/D4 P5_0/WRL/WR P0_3/AN0_3/D3 P5_1/WRH/BHE M16C/64A Group P0_2/AN0_2/D2 P5_2/RD P0_1/AN0_1/D1 P5_3/BCLK P0_0/AN0_0/D0 P5_4/HLDA P10_7/AN7/KI3 P5_5/HOLD PLQP0100KB-A P10_6/AN6/KI2 P5_6/ALE P10_5/AN5/KI1 P5_7/RDY/CLKOUT (100P6Q-A) P10_4/AN4/KI0 P6_0/RTCOUT/CTS0/RTS0...
Page 42 M16C/64A Group 1. Overview Table 1.4 Pin Names for the 100-Pin Package (1/2) Pin No. I/O Pin for Peripheral Function Bus Control Control Pin Port A/D converter, Interrupt Timer Serial interface D/A converter P9_6 SOUT4 ANEX1 P9_5 CLK4 ANEX0 P9_4 TB4IN/PWM1 P9_3 TB3IN/PWM0...
Page 43 M16C/64A Group 1. Overview Table 1.5 Pin Names for the 100-Pin Package (2/2) Pin No. I/O Pin for Peripheral Function Control Port A/D converter, Bus Control Pin Interrupt Timer Serial interface D/A converter P4_3 P4_2 P4_1 P4_0 P3_7 P3_6 P3_5 P3_4 P3_3 P3_2...
Page 44: Pin Functions
M16C/64A Group 1. Overview Pin Functions Table 1.6 Pin Functions for the 100-Pin Package (1/3) Signal Name Pin Name Power Supply Description Apply 2.7 to 5.5 V to pins VCC1 and VCC2 (VCC1 ≥ VCC2) Power supply VCC1, input VCC2, VSS and 0 V to the VSS pin.
Page 45 M16C/64A Group 1. Overview Table 1.7 Pin Functions for the 100-Pin Package (2/3) Power Signal Name Pin Name Description Supply Main clock input VCC1 I/O for the main clock oscillator. Connect a ceramic resonator or crystal between pins XIN and XOUT. Input an external clock to XIN pin and leave XOUT pin open.
Page 46 M16C/64A Group 1. Overview Table 1.8 Pin Functions for the 100-Pin Package (3/3) Power Signal Name Pin Name Description Supply SDA0 to SDA2, VCC1 UART0 to SDA5 Serial data I/O. UART2, SDA6, SDA7 VCC2 UART5 to SCL0 to SCL2, UART7 VCC1 SCL5 Transmit/receive clock I/O.
Page 47: Central Processing Unit (Cpu)
M16C/64A Group 2. Central Processing Unit (CPU) Central Processing Unit (CPU) Figure 2.1 shows the CPU registers. Seven registers (R0, R1, R2, R3, A0, A1, and FB) out of 13 compose a register bank, and there are two register banks. b8 b7 R0H (upper bits of R0) R0L (lower bits of R0)
Page 48: Data Registers (R0, R1, R2, And R3)
M16C/64A Group 2. Central Processing Unit (CPU) Data Registers (R0, R1, R2, and R3) R0, R1, R2, and R3 are 16-bit registers used for transfer, arithmetic, and logic operations. R0 and R1 can be split into upper (R0H/R1H) and lower (R0L/R1L) bits to be used separately as 8-bit data registers. R0 can be combined with R2, and R3 can be combined with R1 and be used as 32-bit data registers R2R0 and R3R1, respectively.
Page 49: Interrupt Enable Flag (I Flag)
M16C/64A Group 2. Central Processing Unit (CPU) 2.8.7 Interrupt Enable Flag (I Flag) The I flag enables maskable interrupts. Maskable interrupts are disabled when the I flag is 0, and enabled when it is 1. The I flag becomes 0 when an interrupt request is accepted.
Page 50: Address Space
M16C/64A Group 3. Address Space Address Space Address Space The M16C/64A Group has a 1 MB address space from 00000h to FFFFFh. Address space is expandable to 4 MB with the memory area expansion function. Addresses 40000h to BFFFFh can be used as external areas from bank 0 to bank 7.
Page 51: Memory Map
M16C/64A Group 3. Address Space Memory Map Special function registers (SFRs) are allocated from address 00000h to 003FFh and from 0D000h to 0D7FFh. Peripheral function control registers are located here. All blank areas within SFRs are reserved. Do not access these areas. Internal RAM is allocated from address 00400h and higher, with 10 KB of internal RAM allocated from 00400h to 02BFFh.
Page 52: Accessible Area In Each Mode
M16C/64A Group 3. Address Space Accessible Area in Each Mode Areas that can be accessed vary depending on processor mode and the status of each control bit. Figure 3.3 shows the Accessible Area in Each Mode. In single-chip mode, the SFRs, internal RAM, and internal ROM can be accessed. In memory expansion mode, the SFRs, internal RAM, internal ROM, and external areas can be accessed.
Page 53: Special Function Registers (Sfrs)
M16C/64A Group 4. Special Function Registers (SFRs) Special Function Registers (SFRs) SFRs An SFR is a control register for a peripheral function. Table 4.1 SFR Information (1) Address Register Symbol Reset Value 0000h 0001h 0002h 0003h 0000 0000b (CNVSS pin is low) 0004h Processor Mode Register 0 0000 0011b...
Page 54 M16C/64A Group 4. Special Function Registers (SFRs) Table 4.2 SFR Information (2) Address Register Symbol Reset Value 0020h 0021h 0022h 0023h 0024h 0025h 0026h Voltage Monitor Function Select Register VWCE 0027h 0028h Voltage Detector 1 Level Select Register VD1LS 0000 1010b 0029h 002Ah Voltage Monitor 0 Control Register...
Page 55 M16C/64A Group 4. Special Function Registers (SFRs) Table 4.3 SFR Information (3) Address Register Symbol Reset Value 0040h 0041h INT7 Interrupt Control Register 0042h INT7IC XX00 X000b INT6 Interrupt Control Register 0043h INT6IC XX00 X000b INT3 Interrupt Control Register 0044h INT3IC XX00 X000b 0045h...
Page 56 M16C/64A Group 4. Special Function Registers (SFRs) Table 4.4 SFR Information (4) Address Register Symbol Reset Value 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h DMA2 Interrupt Control Register DM2IC XXXX X000b 006Ah DMA3 Interrupt Control Register DM3IC XXXX X000b UART5 Bus Collision Detection Interrupt Control Register U5BCNIC...
Page 57 M16C/64A Group 4. Special Function Registers (SFRs) Table 4.5 SFR Information (5) Address Register Symbol Reset Value 0180h 0181h DMA0 Source Pointer SAR0 0182h 0183h 0184h 0185h DMA0 Destination Pointer DAR0 0186h 0187h 0188h DMA0 Transfer Counter TCR0 0189h 018Ah 018Bh 018Ch DMA0 Control Register...
Page 58 M16C/64A Group 4. Special Function Registers (SFRs) Table 4.6 SFR Information (6) Address Register Symbol Reset Value 01B0h 01B1h DMA3 Source Pointer SAR3 01B2h 01B3h 01B4h 01B5h DMA3 Destination Pointer DAR3 01B6h 01B7h 01B8h DMA3 Transfer Counter TCR3 01B9h 01BAh 01BBh 01BCh DMA3 Control Register...
Page 59 M16C/64A Group 4. Special Function Registers (SFRs) Table 4.7 SFR Information (7) Address Register Symbol Reset Value 01E0h Timer B3-1 Register TB31 01E1h 01E2h Timer B4-1 Register TB41 01E3h 01E4h Timer B5-1 Register TB51 01E5h Pulse Period/Pulse Width Measurement Mode Function Select Reg- 01E6h PPWFS2 XXXX X000b...
Page 60 M16C/64A Group 4. Special Function Registers (SFRs) Table 4.8 SFR Information (8) Address Register Symbol Reset Value 0210h 0211h Address Match Interrupt Register 0 RMAD0 0212h 0213h 0214h 0215h Address Match Interrupt Register 1 RMAD1 0216h 0217h 0218h 0219h Address Match Interrupt Register 2 RMAD2 021Ah 021Bh...
Page 61 M16C/64A Group 4. Special Function Registers (SFRs) Table 4.9 SFR Information (9) Address Register Symbol Reset Value 0240h 0241h 0242h 0243h 0244h UART0 Special Mode Register 4 U0SMR4 0245h UART0 Special Mode Register 3 U0SMR3 000X 0X0Xb 0246h UART0 Special Mode Register 2 U0SMR2 X000 0000b 0247h...
Page 62 M16C/64A Group 4. Special Function Registers (SFRs) Table 4.10 SFR Information (10) Address Register Symbol Reset Value 0270h SI/O3 Transmit/Receive Register S3TRR 0271h 0272h SI/O3 Control Register 0100 0000b 0273h SI/O3 Bit Rate Register S3BRG 0274h SI/O4 Transmit/Receive Register S4TRR 0275h 0276h SI/O4 Control Register...
Page 63 M16C/64A Group 4. Special Function Registers (SFRs) Table 4.11 SFR Information (11) Address Register Symbol Reset Value 02A0h 02A1h 02A2h 02A3h 02A4h UART7 Special Mode Register 4 U7SMR4 02A5h UART7 Special Mode Register 3 U7SMR3 000X 0X0Xb 02A6h UART7 Special Mode Register 2 U7SMR2 X000 0000b 02A7h...
Page 64 M16C/64A Group 4. Special Function Registers (SFRs) Table 4.12 SFR Information (12) Address Register Symbol Reset Value 0300h Timer B3/B4/B5 Count Start Flag TBSR 000X XXXXb 0301h 0302h Timer A1-1 Register TA11 0303h 0304h Timer A2-1 Register TA21 0305h 0306h Timer A4-1 Register TA41 0307h...
Page 65 M16C/64A Group 4. Special Function Registers (SFRs) Table 4.13 SFR Information (13) Address Register Symbol Reset Value 0330h Timer B0 Register 0331h 0332h Timer B1 Register 0333h 0334h Timer B2 Register 0335h 0336h Timer A0 Mode Register TA0MR 0337h Timer A1 Mode Register TA1MR 0338h Timer A2 Mode Register...
Page 66 M16C/64A Group 4. Special Function Registers (SFRs) Table 4.14 SFR Information (14) Address Register Symbol Reset Value 0360h Pull-Up Control Register 0 PUR0 0361h Pull-Up Control Register 1 PUR1 0000 0000b 0000 0010b 0362h Pull-Up Control Register 2 PUR2 0363h 0364h 0365h 0366h...
Page 67 M16C/64A Group 4. Special Function Registers (SFRs) Table 4.15 SFR Information (15) Address Register Symbol Reset Value 0390h DMA2 Source Select Register DM2SL 0391h 0392h DMA3 Source Select Register DM3SL 0393h 0394h 0395h 0396h 0397h 0398h DMA0 Source Select Register DM0SL 0399h 039Ah...
Page 68 M16C/64A Group 4. Special Function Registers (SFRs) Table 4.16 SFR Information (16) Address Register Symbol Reset Value 03C0h XXXX XXXXb A/D Register 0 03C1h 0000 00XXb 03C2h XXXX XXXXb A/D Register 1 03C3h 0000 00XXb 03C4h XXXX XXXXb A/D Register 2 03C5h 0000 00XXb 03C6h...
Page 69 M16C/64A Group 4. Special Function Registers (SFRs) Table 4.17 SFR Information (17) Address Register Symbol Reset Value 03F0h Port P8 Register 03F1h Port P9 Register 03F2h Port P8 Direction Register 03F3h Port P9 Direction Register 03F4h Port P10 Register 03F5h 03F6h Port P10 Direction Register PD10...
Page 70 M16C/64A Group 4. Special Function Registers (SFRs) Table 4.18 SFR Information (18) Address Register Symbol Reset Value D080h 0000 0000b PMC0 Header Pattern Set Register (Min) PMC0HDPMIN D081h XXXX X000b D082h 0000 0000b PMC0 Header Pattern Set Register (Max) PMC0HDPMAX D083h XXXX X000b D084h...
Page 71: Notes On Sfrs
M16C/64A Group 4. Special Function Registers (SFRs) Notes on SFRs 4.2.1 Register Settings Table 4.19 lists Registers with Write-Only Bits and registers whose function differs between reading and writing. Set these registers with immediate values. Do not use read-modify-write instructions. When establishing the next value by altering the existing value, write the existing value to the RAM as well as to the register.
Page 72 M16C/64A Group 4. Special Function Registers (SFRs) Table 4.20 Read-Modify-Write Instructions Function Mnemonic Transfer MOV Dir Bit processing BCLR, BM Cnd , BNOT, BSET, BTSTC, and BTSTS Shifting ROLC, RORC, ROT, SHA, and SHL ABS, ADC, ADCF, ADD, DEC, DIV, DIVU, DIVX, EXTS, INC, MUL, MULU, NEG, Arithmetic operation SBB, and SUB Decimal operation...
Page 73: Protection
M16C/64A Group 5. Protection Protection Introduction In the event that a program runs out of control, this function protects the important registers so that they will not be rewritten easily. Register Table 5.1 Registers Address Register Symbol Reset Value 000Ah Protect Register PRCR 5.2.1...
Page 74 M16C/64A Group 5. Protection PRC6, PRC3, PRC1, PRC0 (Protect bits 6, 3, 1, 0) (b6, b3, b1, b0) When setting bits PRC6, PRC3, PRC1, and PRC0 to 1 (write enabled), these bits remain 1 (write enabled). To change registers protected by these bits, follow these steps: Set the PRCi bit to 1.
Page 75: Notes On Protection
M16C/64A Group 5. Protection Notes on Protection After setting the PRC2 bit to 1 (write enabled), by writing to a given SFR, the PRC2 bit becomes 0 (write disabled). Change the registers protected by the PRC2 bit in the next instruction after setting the PRC2 bit to 1.
Page 76: Resets
M16C/64A Group 6. Resets Resets Introduction The following resets can be used to reset the MCU: hardware reset, power-on reset, voltage monitor 0 reset, voltage monitor 1 reset, voltage monitor 2 reset, oscillator stop detect reset, watchdog timer reset, and software reset. Table 6.1 lists the Types of Resets and Figure 6.1 shows the Reset Circuit Block Diagram.
Page 77 M16C/64A Group 6. Resets Table 6.2 Classification of SFRs Which are Reset Register and Bit SFR (A) Bits OSDR and CWR in the RSTFR register CWR bit in the RSTFR register Registers VCR1, VCR2, and VW0C SFR (B) Bits VW1C2 and VW1C3 in the VW1C register Bits VW2C2 and VW2C3 in the VW2C register Bits PM00 and PM01 in the PM0 register SFR (C)
Page 78: Registers
M16C/64A Group 6. Resets Registers Refer to 7. “Voltage Detector” for registers used with the voltage monitor 0 reset, voltage monitor 1 reset, and voltage monitor 2 reset. Refer to 15. “Watchdog Timer” for registers used with the watchdog timer reset.
Page 79: Processor Mode Register 0 (Pm0)
M16C/64A Group 6. Resets 6.2.1 Processor Mode Register 0 (PM0) Processor Mode Register 0 b7 b6 b5 b4 Reset Value Symbol Address 0000 0000b (CNVSS pin is low) 0004h 0000 0011b (CNVSS pin is high) Bit Symbol Bit Name Function PM00 0 : Single-chip mode Processor mode bit...
Page 80: Reset Source Determine Register (Rstfr)
M16C/64A Group 6. Resets 6.2.2 Reset Source Determine Register (RSTFR) Reset Source Determine Register b6 b5 b4 Reset Value Symbol Address See Table 6.5. RSTFR 0018h Bit Symbol Bit Name Function Cold start/warm start 0 : Cold start 1 : Warm start discrimination flag 0 : Not detected Hardware reset detection flag...
Page 81: Optional Function Select Area
M16C/64A Group 6. Resets Optional Function Select Area In the optional function select area, the MCU state after reset and the function to prevent rewrite in parallel I/O mode are selected. The optional function select area is not an SFR, and therefore cannot be rewritten by a program. Set an appropriate value when writing a program to flash memory.
Page 82 M16C/64A Group 6. Resets ROMCR (ROM code protect cancel bit) (b2) ROMCP1 (ROM code protect bit) (b3) These bits prevent the flash memory from being read or changed in parallel I/O mode. Table 6.6 ROM Code Protection Bit Setting ROM Code Protection ROMCR bit ROMCP1 bit Cancelled...
Page 83: Operations
M16C/64A Group 6. Resets Operations 6.4.1 Status after Reset The status of SFRs after reset depends on the reset type. See the Reset Value column in 4. “Special Function Registers (SFRs)”. Table 6.7 lists Pin Status When RESET Pin Level is Low, Figure 6.2 shows CPU Register Status after Reset, and Figure 6.3 shows Reset Sequence.
Page 84 M16C/64A Group 6. Resets 0000h Data register (R0) 0000h Data register (R1) 0000h Data register (R2) 0000h Data register (R3) 0000h Address register (A0) 0000h Address register (A1) 0000h Frame base register (FB) 00000h Interrupt table register (INTB) Content of addresses FFFFEh to FFFFCh Program counter (PC) User stack pointer (USP) 0000h...
Page 85 M16C/64A Group 6. Resets VCC1, VCC2 Must be equal to or td(P-R) Microprocessor mode × 20 cycles more than fOCO-S BYTE = high RESET tps + × 60 cycles (max.) fOCO-S BCLK Content of FFFFCh FFFFDh FFFFEh Address reset vector Microprocessor mode BYTE = low Content of...
Page 86: Hardware Reset
M16C/64A Group 6. Resets 6.4.2 Hardware Reset This reset is triggered by the RESET pin. When the power supply voltage meets the recommended operating conditions, the MCU resets the pins, CPU, and SFRs when a low-level signal is applied to the RESET pin.
Page 87: Power-On Reset Function
M16C/64A Group 6. Resets 6.4.3 Power-On Reset Function The power-on reset function can be used on the system in which VCC1 is Vdet0 or higher. When the RESET pin is connected to VCC1 via a pull-up resistor, and the VCC1 voltage level rises while the rise gradient is trth, the power-on reset function is enabled and the MCU resets the pins, CPU, and SFRs.
Page 88: Voltage Monitor 0 Reset
M16C/64A Group 6. Resets 6.4.4 Voltage Monitor 0 Reset This reset is triggered by the MCU's on-chip voltage detector 0. The voltage detector 0 monitors the voltage applied to the VCC1 pin (Vdet0). The MCU resets the pins, CPU, and SFRs when the voltage applied to the VCC1 pin drops to Vdet0 or below.
Page 89: Oscillator Stop Detect Reset
M16C/64A Group 6. Resets 6.4.7 Oscillator Stop Detect Reset The MCU resets and stops the pins, CPU, and SFRs when the CM27 bit in the CM2 register is 0 (reset when oscillator stop detected), if it detects that the main clock oscillator has stopped. The OSDR bit in the RSTFR register becomes 1 (oscillator stop detect reset detected) after oscillator stop detect reset.
Page 90: Cold/Warm Start Discrimination
M16C/64A Group 6. Resets 6.4.10 Cold/Warm Start Discrimination The cold/warm start discrimination detects whether or not voltage applied to the VCC1 pin drops to the RAM hold voltage or below. The reference voltage is Vdet0. Therefore, the voltage monitor 0 reset is used for cold/warm start discrimination.
Page 91: Notes On Resets
M16C/64A Group 6. Resets Notes on Resets 6.5.1 Power Supply Rising Gradient When supplying power to the MCU, make sure that the power supply voltage applied to the VCC1 pin meets the SVCC conditions. Standard Symbol Parameter Unit Min. Typ. Max.
Page 92: Osdr Bit (Oscillation Stop Detect Reset Detect Flag)
M16C/64A Group 6. Resets 6.5.3 OSDR Bit (Oscillation Stop Detect Reset Detect Flag) When an oscillator stop detect reset is generated, the MCU is reset and then stopped. This state is canceled by hardware reset or voltage monitor 0 reset. Note that the OSDR bit in the RSTFR register is not affected by a hardware reset, but becomes 0 (not detected) from a voltage monitor 0 reset.
Page 93: Voltage Detector
M16C/64A Group 7. Voltage Detector Voltage Detector Introduction The voltage detector monitors the voltage applied to the VCC1 pin. This circuit can be programmed to monitor the VCC1 input voltage. Voltage monitor 0 reset, voltage monitor 1 interrupt, voltage monitor 1 reset, voltage monitor 2 interrupt, and voltage monitor 2 reset can also be used.
Page 94 M16C/64A Group 7. Voltage Detector VC25 VCC1 Level Voltage detector 0 signal selector ≥ Vdet0 VDSEL1 VC26 Level Voltage detector 1 signal selector VW1C3 bit in ≥ Vdet1 the VW1C register VD1LS3 to VD1LS0 VC27 Voltage detector 2 signal VC13 bit in ≥...
Page 95: Registers
M16C/64A Group 7. Voltage Detector Registers Table 7.2 shows the registers of the voltage detector. The reset value shows the values after hardware reset. Refer to the each register explanation for details. Table 7.2 Registers Address Register Name Register Symbol Reset Value Voltage Detector 2 Flag Register 0019h...
Page 96: Voltage Detector 2 Flag Register (Vcr1)
M16C/64A Group 7. Voltage Detector 7.2.1 Voltage Detector 2 Flag Register (VCR1) Voltage Detector 2 Flag Register b6 b5 b4 Reset Value Symbol Address VCR1 0019h 0000 1000b (hardware reset, power-on reset, voltage monitor 0 reset) Bit Symbol Bit Name Function —...
Page 97: Voltage Detector Operation Enable Register (Vcr2)
M16C/64A Group 7. Voltage Detector 7.2.2 Voltage Detector Operation Enable Register (VCR2) Voltage Detector Operation Enable Register b6 b5 b4 Reset Value Symbol Address 0000 0000b 001Ah VCR2 0010 0000b Bit Symbol Bit Name Function — Reserved bits Set to 0 (b3-b0) —...
Page 98: Voltage Monitor Function Select Register (Vwce)
M16C/64A Group 7. Voltage Detector 7.2.3 Voltage Monitor Function Select Register (VWCE) Voltage Monitor Function Select Register b6 b5 b4 Symbol Address Reset Value VWCE 0026h Bit Symbol Bit Name Function 0: Voltage monitors 1 and 2 disabled Voltage monitors 1 and 2 VW12E 1: Voltage monitors 1 and 2 enabled enable bit...
Page 99: Voltage Detector 1 Level Select Register (Vd1Ls)
M16C/64A Group 7. Voltage Detector 7.2.4 Voltage Detector 1 Level Select Register (VD1LS) Voltage Detector 1 Level Select Register b6 b5 b4 Symbol Address Reset Value 0000 1010b (Hardware reset, power-on reset, voltage VD1LS 0028h monitor 0 reset, voltage monitor 1 reset, voltage monitor 2 reset) Bit Symbol Bit Name...
Page 100: Voltage Monitor 0 Control Register (Vw0C)
M16C/64A Group 7. Voltage Detector 7.2.5 Voltage Monitor 0 Control Register (VW0C) Voltage Monitor 0 Control Register b6 b5 b4 Reset Value Symbol Address 1000 XX10b VW0C 002Ah 1100 XX11b Bit Symbol Bit Name Function Voltage monitor 0 reset 0 : Disabled VW0C0 enable bit 1 : Enabled...
Page 101: Voltage Monitor 1 Control Register (Vw1C)
M16C/64A Group 7. Voltage Detector 7.2.6 Voltage Monitor 1 Control Register (VW1C) Voltage Monitor 1 Control Register b7 b6 b5 b4 Symbol Address Reset Value VW1C 002Bh 1000 1010b Bit Symbol Bit Name Function Voltage monitor 1 interrupt/ 0 : Disabled VW1C0 reset enable bit 1 : Enabled...
Page 102 M16C/64A Group 7. Voltage Detector VW1C2 (Voltage change detection flag) (b2) The VW1C2 bit is enabled when the VC26 bit in the VCR2 register is 1 (voltage detector 1 enabled). This bit does not change even if set to 1. Condition to become 0: •...
Page 103: Voltage Monitor 2 Control Register (Vw2C)
M16C/64A Group 7. Voltage Detector 7.2.7 Voltage Monitor 2 Control Register (VW2C) Voltage Monitor 2 Control Register b7 b6 b5 b4 Symbol Address Reset Value 1000 0X10b VW2C 002Ch Bit Symbol Bit Name Function Voltage monitor 2 interrupt/ 0 : Disabled VW2C0 reset enable bit 1 : Enabled...
Page 104 M16C/64A Group 7. Voltage Detector VW2C2 (Voltage change detection flag) (b2) The VW2C2 bit is enabled when the VC27 bit in the VCR2 register is 1 (voltage detector 2 enabled). This bit does not change even if set to 1. Condition to become 0: •...
Page 105: Optional Function Select Area
M16C/64A Group 7. Voltage Detector Optional Function Select Area In the optional function select area, the MCU state after reset and the function to prevent rewrite in parallel I/O mode are selected. The optional function select area is not an SFR, and therefore cannot be rewritten by a program. Set an appropriate value when writing a program to flash memory.
Page 106: Operations
M16C/64A Group 7. Voltage Detector Operations 7.4.1 Digital Filter A digital filter can be used to monitor VCC1 input voltage. For the voltage detector i (i = 1 to 2), the digital filter is enabled when the VWiC1 bit in the VWiC register is set to 0 (digital filter enabled). fOCO-S divided by 1, 2, 4, or 8 is selected as a sampling clock.
Page 107: Voltage Detector 0
M16C/64A Group 7. Voltage Detector 7.4.2 Voltage Detector 0 When the VC25 bit in the VCR2 register is 1 (voltage detector 0 enabled), voltage detector 0 monitors the voltage applied to the VCC1 pin and detects whether the voltage rises through or falls through Vdet0.
Page 108 M16C/64A Group 7. Voltage Detector 7.4.2.1 Voltage Monitor 0 Reset When using voltage monitor 0 reset, set the VDSEL1 bit in the OFS1 address to 0 (Vdet0_2). When the LVDAS bit in the OFS1 address is 1 (voltage monitor 0 reset disabled after hardware reset), set the related bits according to the procedure listed in Table 7.6.
Page 109: Voltage Detector 1
M16C/64A Group 7. Voltage Detector 7.4.3 Voltage Detector 1 When the VW12E bit in the VWCE register is 1 (voltage monitors 1 and 2 enabled) and the VC26 bit in the VCR2 register is 1 (voltage detector 1 enabled), voltage detector 1 monitors the voltage applied to the VCC1 pin and detects whether the voltage rises through or falls through Vdet1.
Page 110 M16C/64A Group 7. Voltage Detector 7.4.3.2 Voltage Monitor 1 Interrupt and Voltage Monitor 1 Reset Table 7.7 lists Procedures for Setting Voltage Monitor 1 Interrupt/Reset Related Bits. Table 7.7 Procedures for Setting Voltage Monitor 1 Interrupt/Reset Related Bits When Using the Digital Filter When Not Using the Digital Filter Step Voltage monitor 1...
Page 111 M16C/64A Group 7. Voltage Detector VCC1 Vdet1 VW1C3 bit Digital filter sampling clock × 3 cycles Digital filter sampling clock × 3 cycles VW1C2 bit Set to 0 When the VW1C1 bit Becomes 0 by accepting is 0 (digital filter Voltage monitor 1 an interrupt request enabled)
Page 112: Voltage Detector 2
M16C/64A Group 7. Voltage Detector 7.4.4 Voltage Detector 2 When the VW12E bit in the VWCE register is 1 (voltage monitors 1 and 2 enabled) and the VC27 bit in the VCR2 register is 1 (voltage detector 2 enabled), voltage detector 2 monitors the voltage applied to the VCC1 pin and detects whether the voltage rises through or falls through Vdet2.
Page 113 M16C/64A Group 7. Voltage Detector 7.4.4.2 Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset Table 7.8 lists Procedure for Setting Voltage Monitor 2 Interrupt/Reset Related Bits. Table 7.8 Procedure for Setting Voltage Monitor 2 Interrupt/Reset Related Bits When Using the Digital Filter When Not Using the Digital Filter Step Voltage monitor 2...
Page 114 M16C/64A Group 7. Voltage Detector VCC1 Vdet2 VC13 bit Digital filter sampling clock × 3 cycles Digital filter sampling clock × 3 cycles VW2C2 bit Set to 0 When the VW2C1 bit Becomes 0 by accepting is 0 (digital filter Voltage monitor 2 an interrupt request enabled)
Page 115: Interrupts
M16C/64A Group 7. Voltage Detector Interrupts The voltage monitor 1 interrupt and voltage monitor 2 interrupt is a non-maskable interrupt. The watchdog timer interrupt, oscillator stop/restart detect interrupt, voltage monitor 1 interrupt, and voltage monitor 2 interrupt share the same vector. When using some functions together, read the detect flags of the events in an interrupt processing program, and determine the source of the interrupt.
Page 116: Clock Generator
M16C/64A Group 8. Clock Generator Clock Generator Introduction The clock generator generates operating clocks for the CPU and peripheral functions. The following circuits are incorporated to generate the system clock signals. • Main clock oscillator • PLL frequency synthesizer • 125 kHz on-chip oscillator •...
Page 117 M16C/64A Group 8. Clock Generator CM01 to CM00 = 00b, PCLK5 = 0 I/O ports PM01 to PM00 = 00b, CM01 to CM00 = 01b, PCLK5 = 0 Sub clock oscillator PM01 to PM00 = 00b, CM01 to CM00 = 10b, PCLK5 = 0 XCIN XCOUT CLKOUT...
Page 118: Registers
M16C/64A Group 8. Clock Generator Table 8.2 I/O Pins Pin Name Function Input I/O pins for the main clock oscillator XOUT Output XCIN Input I/O pins for a sub clock oscillator XCOUT Output CLKOUT Output Clock output (in single-chip mode) BCLK Output BCLK output (in memory expansion and microprocessor modes)
Page 119: Processor Mode Register 0 (Pm0)
M16C/64A Group 8. Clock Generator 8.2.1 Processor Mode Register 0 (PM0) Processor Mode Register 0 b7 b6 b5 b4 Reset Value Symbol Address 0000 0000b (CNVSS pin is low) 0004h 0000 0011b (CNVSS pin is high) Bit Symbol Bit Name Function PM00 0 : Single-chip mode...
Page 120: System Clock Control Register 0 (Cm0)
M16C/64A Group 8. Clock Generator 8.2.2 System Clock Control Register 0 (CM0) System Clock Control Register 0 b7 b6 b5 b4 Reset Value Symbol Address 0006h 0100 1000b Bit Symbol Bit Name Function CM00 Clock output function select 0 : I/O port bit (enabled in single-chip 1 : Output fC mode only)
Page 121 M16C/64A Group 8. Clock Generator CM02 (Wait mode peripheral function clock stop bit) (b2) This bit is used to stop the f1 peripheral function clock in wait mode. fC, fC32, and fOCO-S are not affected by the CM02 bit. When the PM21 bit in the PM2 register is 1 (clock change disabled), the CM02 bit remains unchanged even when written to.
Page 122: System Clock Control Register 1 (Cm1)
M16C/64A Group 8. Clock Generator 8.2.3 System Clock Control Register 1 (CM1) System Clock Control Register 1 b6 b5 b4 Symbol Address Reset Value 0007h 0010 0000b Bit Symbol Bit Name Function 0 : Clock on CM10 All clock stop control bit 1 : All clocks off (stop mode) 0 : Main clock CM11...
Page 123 M16C/64A Group 8. Clock Generator CM13 (XIN-XOUT feedback resistor select bit) (b3) The CM13 bit can be used when the main clock is not used at all, or when the externally generated clock is supplied to the XIN pin. When connecting a ceramic resonator or crystal between pins XIN and XOUT, set the CM13 bit to 0 (internal feedback resistor connected).
Page 124: Oscillation Stop Detection Register (Cm2)
M16C/64A Group 8. Clock Generator 8.2.4 Oscillation Stop Detection Register (CM2) Oscillation Stop Detection Register Symbol Address Reset Value b6 b5 b4 000Ch 0X00 0010b Bit Symbol Bit Name Function 0: Oscillator stop/restart detect function Oscillator stop/restart detect disabled CM20 enable bit 1: Oscillator stop/restart detect function enabled...
Page 125 M16C/64A Group 8. Clock Generator CM22 (Oscillator stop/restart detect flag) (b2) Condition to become 0: • Set it to 0. Conditions to become 1: • Main clock stop is detected. • Main clock restart is detected. (The CM22 bit remains unchanged even if 1 is written.) When the CM22 bit changes state from 0 to 1, an oscillator stop/restart detect interrupt is generated.
Page 126: Peripheral Clock Select Register (Pclkr)
M16C/64A Group 8. Clock Generator 8.2.5 Peripheral Clock Select Register (PCLKR) Peripheral Clock Select Register Reset Value b6 b5 b4 Symbol Address PCLKR 0012h 0000 0011b Bit Symbol Bit Name Function Timers A and B clock select bit (clock source for timers A and 0: f2TIMAB/f2IIC PCLK0 B, the dead time timer, and...
Page 127: Pll Control Register 0 (Plc0)
M16C/64A Group 8. Clock Generator 8.2.6 PLL Control Register 0 (PLC0) PLL Control Register 0 Symbol Address Reset Value b7 b6 b5 b4 PLC0 001Ch 0X01 X010b Bit Symbol Bit Name Function b2 b1 b0 PLC00 0 : Do not set 1 : Multiply-by-2 0 : Multiply-by-4 PLL multiplying factor...
Page 128: Processor Mode Register 2 (Pm2)
M16C/64A Group 8. Clock Generator 8.2.7 Processor Mode Register 2 (PM2) Processor Mode Register 2 Reset Value b6 b5 b4 Symbol Address 001Eh XX00 0X01b Bit Symbol Bit Name Function — Reserved bit Set to 1. (b0) 0 : Clock is protected by PRCR register PM21 System clock protection bit 1 : Clock change disabled...
Page 129: Clocks Generated By Clock Generators
M16C/64A Group 8. Clock Generator Clocks Generated by Clock Generators Clocks generated by the clock generators are described below. 8.3.1 Main Clock This clock is supplied by the main clock oscillator and used as a clock source for the CPU and peripheral function clocks.
Page 130: Pll Clock
M16C/64A Group 8. Clock Generator 8.3.2 PLL Clock PLL clock is generated by the PLL frequency synthesizer. This clock is used as the clock source for the CPU and peripheral function clocks. After reset, the PLL frequency synthesizer is stopped. PLL clock is a clock which divides the main clock by the selected values of bits PLC05 to PLC04 in the PLC0 register, and then multiplied by the selected values of bits PLC02 to PLC00.
Page 131: Sub Clock (Fc)
M16C/64A Group 8. Clock Generator 8.3.4 Sub Clock (fC) The sub clock is supplied by the sub clock oscillator. This clock is the clock source for count sources of the CPU clock, timer A, timer B, real-time clock, CEC function, and remote control signal receiver. The sub clock oscillator is configured by connecting a crystal between pins XCIN and XCOUT.
Page 132: Cpu Clock And Peripheral Function Clocks
M16C/64A Group 8. Clock Generator CPU Clock and Peripheral Function Clocks The CPU is run by the CPU clock, and the peripheral functions are run by the peripheral function clocks. 8.4.1 CPU Clock and BCLK The CPU clock is an operating clock for the CPU and watchdog timer. It is also used as a sampling clock for the NMI / SD digital filter.
Page 133 M16C/64A Group 8. Clock Generator CPU clock NMI/SD digital filter Watchdog timer fOCO-S Reset CPU clock Voltage detector Clock generator Timer A Divider fC32 Timer B Main clock Real-time clock PLL clock Pulse width modulator Remote control fOCO-S 125 kHz on-chip signal receiver oscillator clock fC32...
Page 134: Clock Output Function
M16C/64A Group 8. Clock Generator Clock Output Function In single-chip mode, the f1, f8, f32 or fC clock can be output from the CLKOUT pin. Use bits CM01 to CM00 in the CM0 register, and the PCLK5 bit in the PCLKR register to select a clock. f8 has the same frequency as f1 divided by 8, and f32 has the same frequency as f1 divided by 32.
Page 135: Oscillator Stop/Restart Detect Function
M16C/64A Group 8. Clock Generator Oscillator Stop/Restart Detect Function This function detects a stop/restart of the main clock oscillator. The oscillator stop/restart detect function can be enabled and disabled with the CM20 bit in the CM2 register. A reset or oscillator stop/restart detect interrupt is generated when an oscillator stop or restart is detected. Set the CM27 bit in the CM2 register to select the reset or interrupt.
Page 136: Operation When Cm27 Bit Is 1 (Oscillator Stop/Restart Detect Interrupt)
M16C/64A Group 8. Clock Generator 8.7.2 Operation When CM27 Bit is 1 (Oscillator Stop/Restart Detect Interrupt) When the CM20 bit is 1 (oscillator stop/restart detect function enabled), the system is placed in the state shown in Table 8.7 if the main clock detects oscillator stop or restart. The CM21 bit becomes 1 in high-speed, medium-speed, or low-speed mode.
Page 137: Using The Oscillator Stop/Restart Detect Function
M16C/64A Group 8. Clock Generator 8.7.3 Using the Oscillator Stop/Restart Detect Function After oscillator stop is detected, if the main clock reoscillates, set the main clock back to the clock source for the CPU clock and peripheral functions by a program. Figure 8.6 shows the Switching from On-Chip Oscillator Clock to Main Clock.
Page 138: Notes On Clock Generator
M16C/64A Group 8. Clock Generator Notes on Clock Generator 8.9.1 Oscillator Using a Crystal or a Ceramic Resonator To connect a crystal/ceramic resonator follow the instructions below: • The oscillation characteristics are tied closely to the user’s board design. Perform a careful evaluation of the board before connecting an oscillator.
Page 139: Noise Countermeasure
M16C/64A Group 8. Clock Generator 8.9.2 Noise Countermeasure 8.9.2.1 Clock I/O Pin Wiring • Connect the shortest possible wiring to the clock I/O pin. • Connect (a) the capacitor's ground lead connected to the crystal/ceramic resonator, and (b) the MCU's VSS pin, with the shortest possible wiring (maximum 20 mm). Noise XOUT XOUT...
Page 140: Cpu Clock
M16C/64A Group 8. Clock Generator 8.9.2.3 Signal Line Whose Level Changes at a High-Speed For a signal line whose level changes at a high-speed, wire it as far away from the crystal/ceramic resonator and its wiring pattern as possible. Do not wire it across or extend it parallel to a clock- related signal line or other signal lines which are sensitive to noise.
Page 141: Pll Frequency Synthesizer
M16C/64A Group 8. Clock Generator 8.9.5 PLL Frequency Synthesizer To use the PLL frequency synthesizer, stabilize the supply voltage within the acceptable range of power supply ripple. Table 8.9 Acceptable Range of Power Supply Ripple Standard Symbol Parameter Unit Min. Typ.
Page 142: Starting Pll Clock Oscillation
M16C/64A Group 8. Clock Generator 8.9.6 Starting PLL Clock Oscillation (Technical update number: 16C-A177A/E) Adhere to the following restrictions when using the following products: R5F364AENFA, R5F364AENFB, R5F364AEDFA, R5F364AEDFB, R5F364A6NFA, R5F364A6NFB, R5F364A6DFA, R5F364A6DFB 8.9.6.1 When Using Voltage Detector 0, 1, or 2 Do not change the PLC07 bit in the PLC0 register from 0 to 1 when any bit from VC25 to VC27 in the VCR2 register is 1.
Page 143: Power Control
M16C/64A Group 9. Power Control Power Control Introduction This chapter describes how to reduce the amount of current consumption. Registers Refer to 8. “Clock Generator” for clock-related registers. Table 9.1 Registers Address Register Symbol Reset Value 0000 0001b (Other than user boot mode) 0220h Flash Memory Control Register 0 FMR0...
Page 144: Flash Memory Control Register 0 (Fmr0)
M16C/64A Group 9. Power Control 9.2.1 Flash Memory Control Register 0 (FMR0) Flash Memory Control Register 0 b6 b5 b4 Symbol Address Reset Value 0000 0001b (other than user boot mode) FMR0 0220h 0010 0001b (user boot mode) Bit Symbol Bit Name Function 0 : Busy (being written or erased)
Page 145: Flash Memory Control Register 2 (Fmr2)
M16C/64A Group 9. Power Control 9.2.2 Flash Memory Control Register 2 (FMR2) Flash Memory Control Register 2 b6 b5 b4 Symbol Address Reset Value FMR2 XXXX 0000b 0222h Bit Symbol Bit Name Function — Set to 0 Reserved bits (b1-b0) Slow read mode enable 0 : Disabled FMR22...
Page 146 M16C/64A Group 9. Power Control Do not set the FMR23 bit to 1 (low current consumption read mode enabled) when any of the following occurs: • When the CM07 bit is 0 (main clock, PLL clock, or on-chip oscillator clock selected as CPU clock source).
Page 147: Clock
M16C/64A Group 9. Power Control Clock The amount of current consumption correlates with the number of operating clocks and frequency. When there are fewer operating clocks and a lower frequency, current consumption will be low. Normal operating mode, wait mode, and stop mode can be used to control power consumption. All mode states, except wait mode and stop mode, are referred to as normal operating mode in this document.
Page 148 M16C/64A Group 9. Power Control 9.3.1.3 125 kHz On-Chip Oscillator Mode The fOCO-S clock divided by 1 (no division), 2, 4, 8 or 16 is used as the CPU clock. f1 with the same frequency of the fOCO-S clock divided by 1 is used as the peripheral function clocks. When fC is supplied, fC and fC32 can be used as the peripheral function clocks.
Page 149: Cpu Clock
M16C/64A Group 9. Power Control Table 9.2 Clocks in Normal Operating Mode Peripheral Clocks Mode CPU Clock fC, fC32 fOCO-S Main clock High-speed mode divided by 1 Main clock divided by 1 Main clock Medium-speed mode Enabled Enabled divided by n PLL clock PLL operating mode PLL clock divided by 1...
Page 150 M16C/64A Group 9. Power Control Table 9.4 Selecting Clock Division Related Bits CM1 Register CM0 Register Division Bits CM17 to CM16 CM06 bit No division Divide-by-2 Divide-by-4 − Divide-by-8 Divide-by-16 − : Any value from 00b to 11b Notes: While in high-speed mode, medium-speed mode, PLL operating mode, 125 kHz on-chip oscillator mode, or 125 kHz on-chip oscillator low power mode.
Page 151: Clock Mode Transition Procedure
M16C/64A Group 9. Power Control 9.3.2 Clock Mode Transition Procedure Figure 9.1 shows Clock Mode Transition. Arrows indicate possible mode transitions. Reset Normal Operating Mode Transitions to wait mode and stop mode enabled 125 kHz on-chip 125 kHz on-chip oscillator low power oscillator mode mode High-speed or...
Page 152 M16C/64A Group 9. Power Control CPU clock source PLL clock PLL clock PLL clock PLL clock PLL operating mode PLL clock divided by 16 divided by 4 divided by 2 divided by 1 divided by 8 CPU clock source High-speed mode Medium-speed mode High-speed mode medium-speed mode...
Page 153 M16C/64A Group 9. Power Control a. Entering high-speed mode or medium-speed mode from 125 kHz on-chip oscillator mode or low- speed mode (1) Start the main clock and wait until the oscillation stabilizes. Refer to 8.3.1 “Main Clock” for details. (2) Select divide-by-8 or divide-by-16 mode by setting the CM06 bit and bits CM17 to CM16.
Page 154: Wait Mode
M16C/64A Group 9. Power Control 9.3.3 Wait Mode The CPU clock stops in wait mode, therefore, the CPU, the watchdog timer, and NMI / SD digital filter clocked by the CPU clock stops running. However, if the CSPRO bit in the CSPR register is 1 (count source protection mode enabled), the watchdog timer remains active.
Page 155 M16C/64A Group 9. Power Control 9.3.3.4 Exiting Wait Mode The MCU exits wait mode by a reset or interrupt. Table 9.6 lists Resets and Interrupts to Exit Wait Mode and Conditions for Use. The peripheral function interrupts are affected by the CM02 bit in the CM0 register. When the CM02 bit is 0 (peripheral function clock f1 does not stop in wait mode), peripheral function interrupts can be used to exit wait mode.
Page 156: Stop Mode
M16C/64A Group 9. Power Control 9.3.4 Stop Mode In stop mode, all oscillator are stopped, so the CPU clock and peripheral function clocks are also stopped. Therefore, the CPU and the peripheral functions using these clocks stop operating. The least amount of power is consumed in this mode.
Page 157 M16C/64A Group 9. Power Control 9.3.4.3 Exiting Stop Mode Use a reset or an interrupt to exit stop mode. Table 9.8 lists Resets and Interrupts to Exit Stop Mode and Conditions for Use. Table 9.8 Resets and Interrupts to Exit Stop Mode and Conditions for Use Interrupt, Reset Conditions for Use Usable...
Page 158: Power Control In Flash Memory
M16C/64A Group 9. Power Control Power Control in Flash Memory 9.4.1 Stopping Flash Memory When the flash memory is stopped, current consumption is reduced. Execute a program in any area other than the flash memory. Figure 9.3 shows the setting procedure to stop and restart the flash memory.
Page 159: Reading Flash Memory
M16C/64A Group 9. Power Control 9.4.2 Reading Flash Memory Current consumption while reading the flash memory can be reduced by using bits FMR22 and FMR23 in the FMR2 register. 9.4.2.1 Slow Read Mode Slow read mode can be used when f(BCLK) is less than or equal to f(SLOW_R) and the PM17 bit in the PM1 register is 1 (one wait).
Page 160: Low Current Consumption Read Mode
M16C/64A Group 9. Power Control 9.4.2.2 Low Current Consumption Read Mode Low current consumption read mode can be used when the CM07 bit in the CM0 register is 1 (sub clock used as CPU clock).Figure 9.5 shows Setting and Canceling Low Current Consumption Read Mode.
Page 161: Reducing Power Consumption
M16C/64A Group 9. Power Control Reducing Power Consumption To reduce power consumption, refer to the following descriptions when designing a system or writing a program. 9.5.1 Ports The MCU retains the state of each I/O port even when it enters wait mode or stop mode. A current flows in the active output ports.
Page 162: Notes On Power Control
M16C/64A Group 9. Power Control Notes on Power Control 9.6.1 CPU Clock When switching the CPU clock source, wait until oscillation of the switched clock source is stable. After exiting stop mode, wait until oscillation stabilizes before changing the division. 9.6.2 Wait Mode •...
Page 163: Low Current Consumption Read Mode
M16C/64A Group 9. Power Control The following is an example program for entering stop mode: Program Example: FSET BSET 0, CM1 ; Enter stop mode JMP.B ; Insert a JMP.B instruction ; At least four NOP instructions • Do not enter stop mode from PLL operating mode. To enter stop mode from PLL operating mode, first enter medium-speed mode, then set the PLC07 bit to 0 (PLL off).
Page 164: 10. Processor Mode
M16C/64A Group 10. Processor Mode 10. Processor Mode 10.1 Introduction Single-chip mode, memory expansion mode, or microprocessor mode can be selected for the processor mode. Table 10.1 lists the Processor Mode Features. Table 10.1 Processor Mode Features Processor Mode Access Space Pins Assigned as I/O Ports All pins are I/O ports or Single-chip mode...
Page 165: Registers
M16C/64A Group 10. Processor Mode 10.2 Registers Table 10.3 Registers Address Register Symbol Reset Value 0000 0000b (CNVSS pin is low) 0004h Processor Mode Register 0 0000 0011b (CNVSS pin is high) 0005h Processor Mode Register 1 0000 1000b 0010h Program 2 Area Control Register PRG2C XXXX XX00b...
Page 166: Processor Mode Register 1 (Pm1)
M16C/64A Group 10. Processor Mode 10.2.2 Processor Mode Register 1 (PM1) Processor Mode Register 1 b6 b5 b4 Symbol Address Reset Value 0005h 0000 1000b Bit Symbol Bit Name Function CS2 area switch bit 0 : CS2 (0E000h to 0FFFFh ) PM10 (data flash enable bit) 1 : Data flash (0E000h to 0FFFFh)
Page 167 M16C/64A Group 10. Processor Mode PM13 (Internal area expansion bit 0) (b3) This bit is used to select the range of the RAM, program ROM 1, and external area. When the PM13 bit is 0, the size of the RAM and program ROM 1 is limited, but a wide range can be selected for the external area.
Page 168: Program 2 Area Control Register (Prg2C)
M16C/64A Group 10. Processor Mode 10.2.3 Program 2 Area Control Register (PRG2C) Program 2 Area Control Register b6 b5 b4 Reset Value Symbol Address PRG2C 0010h XXXX XX00b Bit Symbol Bit Name Function 0 : Enable program ROM 2 PRG2C0 Program ROM 2 disable bit 1 : Disable program ROM 2 (b1)
Page 169: Operations
M16C/64A Group 10. Processor Mode 10.3 Operations 10.3.1 Processor Mode Settings Set the processor mode using the CNVSS pin and bits PM01 to PM00 in the PM0 register. In hardware reset, power-on reset, or voltage monitor 0 reset, the processor mode is selected by the CNVSS pin input level.
Page 170 M16C/64A Group 10. Processor Mode Figure 10.1 shows Memory Map in Single-Chip Mode. Single-Chip Mode 00000h 00400h Internal RAM Address XXXXXh PM13 Bit in PM1 Register XXXXXh RAM size 033FFh 033FFh 12 KB Reserved area 03FFFh 053FFh 20 KB 0D000h 31 KB 03FFFh 07FFFh...
Page 171: 11. Bus
M16C/64A Group 11. Bus 11. Bus 11.1 Introduction Two types of buses are available: • Internal bus in the MCU • External bus which is used to access to external devices in memory expansion mode or microprocessor mode Table 11.1 Bus Specifications Item Specification...
Page 172: Chip Select Control Register (Csr)
M16C/64A Group 11. Bus 11.2.1 Chip Select Control Register (CSR) Chip Select Control Register b7 b6 b5 b4 Reset Value Symbol Address 0008h Bit Symbol Bit Name Function 0 : Chip select output disabled CS0 output enable bit (functions as an I/O port) 1 : Chip select output enabled CS1 output enable bit CS2 output enable bit...
Page 173: Chip Select Expansion Control Register (Cse)
M16C/64A Group 11. Bus 11.2.2 Chip Select Expansion Control Register (CSE) Chip Select Expansion Control Register b7 b6 b5 b4 Symbol Address Reset Value 001Bh Bit Symbol Bit Name Function 0 : 1 wait (1 φ + 1 φ ) CSE00W 1 : 2 waits (1 φ...
Page 174: Operations
M16C/64A Group 11. Bus 11.3 Operations 11.3.1 Common Specifications between the Internal Bus and External Bus 11.3.1.1 Reference Clock Both the internal and external buses operate based on the BCLK. However, the area accessed and wait states affect bus operation. Refer to 11.3.2.1 “Software Wait States of the Internal Bus” and 11.3.5.9 “Software Wait States”...
Page 175: Internal Bus
M16C/64A Group 11. Bus 11.3.2 Internal Bus The internal bus is used to access the internal area in the MCU. 11.3.2.1 Software Wait States of the Internal Bus The PM17 bit in the PM1 register, which is a software-wait-related bit, affects both the internal memory and the external area.
Page 176: External Bus
M16C/64A Group 11. Bus 11.3.3 External Bus The external bus is used to access external devices in memory expansion mode or microprocessor mode. In memory expansion or microprocessor mode, some pins serve as the bus control pins to perform data input to and output from external devices.
Page 177: External Bus Control
M16C/64A Group 11. Bus 11.3.5 External Bus Control The following describes the signals needed for accessing external devices and the functionality of software wait states. 11.3.5.1 Address Bus The address bus consists of 20 lines: A0 to A19. The address bus width can be set to 12, 16, or 20 bits using the PM06 bit in the PM0 register, and the PM11 bit in the PM1 register.
Page 178 M16C/64A Group 11. Bus Example 1 Example 2 Accessing the external area indicated by CSj in the next cycle Accessing the internal ROM or internal RAM in the next cycle after accessing the external area indicated by CSi. after accessing the external area indicated by CSi. The address bus and chip select signal both change state The chip select signal changes state, but the address bus between these two cycles.
Page 179 M16C/64A Group 11. Bus 11.3.5.4 Read and Write Signals When the data bus is 16 bits wide, the read and write signals can be selected based on combinations of RD , BHE , and WR , or combinations of RD , WRL , and WRH using the PM02 bit in the PM0 register. When the data bus is 8 bits wide, use combinations of RD , WR , and BHE .
Page 180 M16C/64A Group 11. Bus RDY Signal 11.3.5.6 This signal is provided for accessing external devices which need to be accessed at low speed. If input to the RDY pin is low at the last falling edge of BCLK in the bus cycle, one wait state is inserted in the bus cycle.
Page 181 M16C/64A Group 11. Bus Table 11.8 Pin Functions for Each Processor Mode Memory Processor Mode Memory Expansion Mode or Microprocessor Mode Expansion Mode 01b ( CS2 is for multiplexed bus and 11b (the entire CS space is for the others are for separate bus) Bits PM05 to PM04 00b (separate bus) 10b ( CS1 is for multiplexed bus and...
Page 182 M16C/64A Group 11. Bus 11.3.5.8 External Bus Status When Internal Area is Accessed Table 11.9 lists the External Bus Status When an Internal Area is Accessed. Figure 11.5 shows the Typical Bus Timings When Accessing SFRs. Table 11.9 External Bus Status When an Internal Area is Accessed Item SFR Accessed Internal ROM or RAM Accessed...
Page 183 M16C/64A Group 11. Bus 11.3.5.9 Software Wait States The PM17 bit in the PM1 register, which is a software-wait-related bit, affects both the internal memory and the external area. Software wait states can be inserted to the external area by setting the PM17 bit, setting the CSiW bit in the CSR register, and bits CSEi1W to CSEi0W in the CSE register for each CSi (i = 0 to 3).
Page 184 M16C/64A Group 11. Bus (1) Separate Bus, No Wait States Bus cycle = 2φ Bus cycle = 1φ BCLK Address (Note 1) Data WR , WRL , WRH (2) Separate Bus, One Wait State (1φ + 1φ) Bus cycle = 2φ Bus cycle = 2φ...
Page 185 M16C/64A Group 11. Bus (1) Separate Bus, Three Wait States (1φ + 3φ) Bus cycle = 4φ Bus cycle = 4φ BCLK Address (Note 1) Data WR , WRL , WRH (2) Multiplexed Bus, One or Two Wait States (1φ + 2φ) Bus cycle = 3φ...
Page 186: Notes On Bus
M16C/64A Group 11. Bus 11.4 Notes on Bus 11.4.1 Reading Data Flash When 2.7 V ≤ VCC1 ≤ 3.0 V and f(BCLK) ≥ 16 MHz, or when 3.0 V < VCC1 ≤ 5.5 V and f(BCLK) ≥ 20 MHz, one wait must be inserted to read the data flash. Use the PM17 bit or the FMR17 bit to insert one wait.
Page 187: 12. Memory Space Expansion Function
M16C/64A Group 12. Memory Space Expansion Function 12. Memory Space Expansion Function 12.1 Introduction The following describes the memory space expansion function. In memory expansion or microprocessor mode, the memory space expansion function allows the access space to be expanded. Table 12.1 lists Memory Space Expansion Function Specifications.
Page 188: Data Bank Register (Dbr)
M16C/64A Group 12. Memory Space Expansion Function 12.2.1 Data Bank Register (DBR) Data Bank Register b7 b6 b5 b4 Symbol Address Reset Value 000Bh Bit Symbol Bit Name Function — No register bits. If necessary, set to 0. The read value is 0. —...
Page 189: Operations
M16C/64A Group 12. Memory Space Expansion Function 12.3 Operations 12.3.1 1-MB Mode In 1-MB mode, the memory space is 1 MB. The external area to be accessed is specified using the CSi signals. Memory expansion mode Microprocessor mode 00000h 00400h Internal RAM Internal RAM XXXXXh...
Page 190 M16C/64A Group 12. Memory Space Expansion Function Memory expansion mode Microprocessor mode 00000h 00400h Internal RAM Internal RAM XXXXXh 08000h Reserved area Reserved area 0D000h 0D800h 0E000h Reserved, external area Data flash 10000h Program ROM 2 Reserved, external area 14000h 27000h Reserved area Reserved area...
Page 191: 4-Mb Mode
M16C/64A Group 12. Memory Space Expansion Function 12.3.2 4-MB Mode In 4-MB mode, the memory space is 4 MB. Bits BSR2 to BSR0 in the DBR register select the bank number to be accessed to read or write data. Setting the OFS bit to 1 (offset) allows the accessed address to be offset by 40000h.
Page 192 M16C/64A Group 12. Memory Space Expansion Function Memory expansion mode Microprocessor mode 00000h 00400h Internal RAM Internal RAM XXXXXh Reserved area Reserved area 04000h (16 KB) 08000h 0D000h 0D800h 0E000h Data flash Reserved, external area 10000h Reserved, external area Program ROM 2 14000h 27000h Reserved area...
Page 193 M16C/64A Group 12. Memory Space Expansion Function Memory expansion mode Microprocessor mode 00000h 00400h Internal RAM Internal RAM XXXXXh 08000h Reserved area Reserved area 0D000h 0D800h 0E000h Data flash Reserved, external area 10000h Program ROM 2 Reserved, external area 14000h 27000h Reserved area Reserved area...
Page 194 M16C/64A Group 12. Memory Space Expansion Function In the example below, the CS pin of a 4-MB ROM is connected to the MCU’s CS0 pin. The 4-MB ROM address input pins AD21, AD20, and AD19 are connected to the MCU’s CS3 , CS2 , and CS1 pins, respectively.
Page 195 M16C/64A Group 12. Memory Space Expansion Function Memory expansion mode where the PM13 bit is 0 ROM address MCU address Output from the MCU Pins OFS bit in DBR OFS bit in DBR Bank Access CS Output Address Output Number Area register = 0 register = 1...
Page 196 M16C/64A Group 12. Memory Space Expansion Function Memory expansion mode where the PM13 bit is 1 ROM address MCU address Output from the MCU Pins Bank Access OFS bit in DBR OFS bit in DBR CS Output Address Output Number Area register = 0 register = 1...
Page 197 M16C/64A Group 12. Memory Space Expansion Function Microprocessor mode ROM address MCU address Output from the MCU Pins Bank Access OFS bit in DBR OFS bit in DBR CS Output Address Output Number Area register = 0 register = 1 A16 A15 to A0 000000h 40000h...
Page 198: 13. Programmable I/O Ports
M16C/64A Group 13. Programmable I/O Ports 13. Programmable I/O Ports 13.1 Introduction Table 13.1 lists Programmable I/O Ports Specifications (hereafter referred to as I/O ports). Each pin functions as an I/O port, a peripheral function input/output, or a bus control pin. To set peripheral functions, refer to the description for the individual function.
Page 199: I/O Ports And Pins
M16C/64A Group 13. Programmable I/O Ports 13.2 I/O Ports and Pins Figure 13.1 to Figure 13.11 and Table 13.3 to Table 13.11 show the I/O port configuration, and Figure 13.12 shows the I/O pin configuration. Pull-up selection Direction register Port latch Data bus (Note 1) Input to respective...
Page 200 M16C/64A Group 13. Programmable I/O Ports Pull-up selection Enables peripheral function output Output from peripheral functions Direction register Data bus Port latch (Note 1) Input to respective peripheral functions Analog input Note: symbolizes a parasitic diode. Make sure the input voltage to each port does not exceed VCC. VCC: VCC1 for ports P6 to P10, and VCC2 for ports P0 to P5.
Page 201 M16C/64A Group 13. Programmable I/O Ports Pull-up selection Direction register PCR0 bit in the PCR register Data bus Port latch (Note 1) Input to respective peripheral functions Analog input Note: symbolizes a parasitic diode. Make sure the input voltage to each port does not exceed VCC. VCC: VCC1 for ports P6 to P10, and VCC2 for ports P0 to P5.
Page 202 M16C/64A Group 13. Programmable I/O Ports Pull-up selection Enables peripheral function output Output from peripheral functions Direction register PCR0 bit in the PCR register Data bus Port latch (Note 1) Input to respective peripheral functions Analog input Note: symbolizes a parasitic diode. Make sure the input voltage to each port does not exceed VCC.
Page 203 M16C/64A Group 13. Programmable I/O Ports Pull-up selection Enables peripheral function output Output from peripheral functions Direction register PCR0 bit in the PCR register Data bus Port latch (Note 1) CMOS output/ N-channel open drain output selection Input to respective peripheral functions Analog input Note:...
Page 204 M16C/64A Group 13. Programmable I/O Ports Pull-up selection Enables peripheral function output Output from peripheral functions Direction register Port latch Data bus (Note 1) CMOS output/ N-channel open drain output selection Input to respective peripheral functions Analog input Note: symbolizes a parasitic diode. Make sure the input voltage to each port does not exceed VCC.
Page 205 M16C/64A Group 13. Programmable I/O Ports Pull-up selection Enables peripheral function output Output from peripheral functions Direction register output Port latch Data bus (Note 1) CMOS output/ N-channel open drain output selection Input to respective peripheral functions Analog input Note: symbolizes a parasitic diode.
Page 206 M16C/64A Group 13. Programmable I/O Ports Enables peripheral function output Output from peripheral functions Direction register Data bus Port latch (Note 1) Input to respective peripheral functions Analog input Note: symbolizes a parasitic diode. Figure 13.8 I/O Ports (N-channel Open Drain Output) Table 13.10 I/O Ports (N-channel Open Drain Output) Peripheral Function I/O...
Page 207 M16C/64A Group 13. Programmable I/O Ports Enables peripheral function output Output from peripheral functions P8_5 PM24 bit in the PM2 register (NMI enabled) Direction register Port latch Data bus (Note 2) SD input CEC input Digital filter NMI interrupt input PM24 bit (NMI enabled) Note: symbolizes a parasitic diode.
Page 208 M16C/64A Group 13. Programmable I/O Ports Pull-up selection CM04 bit in the CM0 register P8_7 Direction register Port latch Data bus (Note 1) CM04 bit Pull-up selection CM04 bit in the CM0 register P8_6 Direction register CM04 bit (XCIN-XCOUT) Port latch Data bus (Note 1) Note:...
Page 209 M16C/64A Group 13. Programmable I/O Ports Pull-up selection Bits DA0E and DA1E in the DACON register (D/A output enabled) Direction register output Data bus Port latch (Note 1) Input to respective peripheral functions Analog input Analog output Bits DA0E and DA1E (D/A output enabled) Note: symbolizes a parasitic diode.
Page 210 M16C/64A Group 13. Programmable I/O Ports BYTE BYTE signal input (Note 1) Internal signal CNVSS CNVSS signal input (Note 1) RESET RESET signal input (Note 1) Note: symbolizes a parasitic diode. Make sure the input voltage to each port does not exceed VCC1. Figure 13.12 I/O Pins R01UH0136EJ0210 Rev.2.10 Page 177 of 800...
Page 211: Registers
M16C/64A Group 13. Programmable I/O Ports 13.3 Registers Table 13.12 Registers Address Register Symbol Reset Value 0360h Pull-Up Control Register 0 PUR0 0000 0000b 0361h Pull-Up Control Register 1 PUR1 0000 0010b 0362h Pull-Up Control Register 2 PUR2 0366h Port Control Register 0000 0XX0b 0369h NMI/SD Digital Filter Register...
Page 212: Pull-Up Control Register 0 (Pur0)
M16C/64A Group 13. Programmable I/O Ports 13.3.1 Pull-Up Control Register 0 (PUR0) Pull-Up Control Register 0 b7 b6 b5 b4 Symbol Address Reset Value PUR0 0360h Bit Symbol Bit Name Function PU00 P0_0 to P0_3 pull-up PU01 P0_4 to P0_7 pull-up PU02 P1_0 to P1_3 pull-up PU03...
Page 213: Pull-Up Control Register 1 (Pur1)
M16C/64A Group 13. Programmable I/O Ports 13.3.2 Pull-Up Control Register 1 (PUR1) Pull-Up Control Register 1 Reset Value b7 b6 b5 b4 Symbol Address 0000 0000b PUR1 0361h 0000 0010b Bit Symbol Bit Name Function PU10 P4_0 to P4_3 pull-up PU11 P4_4 to P4_7 pull-up PU12...
Page 214: Pull-Up Control Register 2 (Pur2)
M16C/64A Group 13. Programmable I/O Ports 13.3.3 Pull-Up Control Register 2 (PUR2) Pull-Up Control Register 2 b7 b6 b5 b4 Symbol Address Reset Value PUR2 0362h Bit Symbol Bit Name Function PU20 P8_0 to P8_3 pull-up PU21 P8_4, P8_6, P8_7 pull-up PU22 P9_0 to P9_3 pull-up 0 : Not pulled high...
Page 215: Port Control Register (Pcr)
M16C/64A Group 13. Programmable I/O Ports 13.3.4 Port Control Register (PCR) Port Control Register b6 b5 b4 Symbol Address Reset Value 0366h 0000 0XX0b Bit Symbol Bit Name Function Operation performed when the P1 register is read 0 : When the port is set to input, the input levels of pins P1_0 to P1_7 are read.
Page 216: Port Pi Register (Pi) (I = 0 To 10)
M16C/64A Group 13. Programmable I/O Ports 13.3.5 Port Pi Register (Pi) (i = 0 to 10) Port Pi Register (i = 0 to 10) Symbol Address Reset Value b7 b6 b5 b4 P0 to P3 03E0h, 03E1h, 03E4h, 03E5h P4 to P7 03E8h, 03E9h, 03ECh, 03EDh P8 to P10 03F0h, 03F1h, 03F4h...
Page 217: Port Pi Direction Register (Pdi) (I = 0 To 10)
M16C/64A Group 13. Programmable I/O Ports 13.3.6 Port Pi Direction Register (PDi) (i = 0 to 10) Port Pi Direction Register (i = 0 to 10) b7 b6 b5 b4 Symbol Address Reset Value PD0 to PD3 03E2h, 03E3h, 03E6h, 03E7h PD4 to PD7 03EAh, 03EBh, 03EEh, 03EFh PD8 to PD10...
Page 218: Nmi/Sd Digital Filter Register (Nmidf)
M16C/64A Group 13. Programmable I/O Ports NMI/SD Digital Filter Register (NMIDF) 13.3.7 NMI/SD Digital Filter Register b7 b6 b5 b4 Symbol Address Reset Value NMIDF 0369h XXXX X000b Bit Symbol Bit Name Function NMIDF0 0 : No filter 1 : CPU clock divided by 2 0 : CPU clock divided by 4 NMI/SD filter sampling clock NMIDF1...
Page 219: Peripheral Function I/O
M16C/64A Group 13. Programmable I/O Ports 13.4 Peripheral Function I/O 13.4.1 Peripheral Function I/O and Port Direction Bits Programmable I/O ports can share pins with peripheral function I/O (see Table 1.4 to Table 1.5 “Pin Names, Pin Package”). Some peripheral function I/O are affected by a port direction bit which shares the same pin.
Page 220: Nmi/Sd Digital Filter
M16C/64A Group 13. Programmable I/O Ports NMI/SD Digital Filter 13.4.3 The NMI / SD input function includes a digital filter. A sampling clock can be selected by bits NMIDF2 to NMIDF0 in the NMIDF register. The NMI level is sampled for every sampling clock. When the same sampled level is detected three times in a row, the level is transferred to the internal circuit.
Page 221: Unassigned Pin Handling
M16C/64A Group 13. Programmable I/O Ports 13.5 Unassigned Pin Handling Table 13.14 Unassigned Pin Handling in Single-Chip Mode Pin Name Connection One of the following: • Set to input mode and connect a pin to VSS via a resistor (pull-down) Ports P0 to P5 •...
Page 222 M16C/64A Group 13. Programmable I/O Ports Table 13.15 Unassigned Pin Handling in Memory Expansion Mode and Microprocessor Mode Pin Name Connection One of the following: • Set to input mode and connect a pin to VSS via a resistor (pull-down) Ports P0 to P5 •...
Page 223: Notes On Programmable I/O Ports
M16C/64A Group 13. Programmable I/O Ports 13.6 Notes on Programmable I/O Ports Influence of SD 13.6.1 When a low-level signal is applied to the SD pin while the IVPCR1 bit in the TB2SC register is 1 (three- phase output forcible cutoff by input on SD pin enabled), the following pins become high-impedance: P7_2/CLK2/TA1OUT/V, P7_3/ CTS2 / RTS2 /TA1IN/ V , P7_4/TA2OUT/W, P7_5/TA2IN/ W , P8_0/TA4OUT/RXD5/SCL5/U, P8_1/TA4IN/ CTS5 / RTS5 / U 13.6.2...
Page 224: Interrupts
M16C/64A Group 14. Interrupts 14. Interrupts 14.1 Introduction Table 14.1 lists Types of Interrupts, and Table 14.2 lists I/O Pins. The pins shown in Table 14.2 are external interrupt input pins. Refer to the peripheral functions for the pins related to the peripheral functions.
Page 225: Registers
M16C/64A Group 14. Interrupts 14.2 Registers Table 14.3 Registers (1/2) Address Register Symbol Reset Value 001Eh Processor Mode Register 2 XX00 0X01b INT7 Interrupt Control Register 0042h INT7IC XX00 X000b INT6 Interrupt Control Register 0043h INT6IC XX00 X000b INT3 Interrupt Control Register 0044h INT3IC XX00 X000b...
Page 226 M16C/64A Group 14. Interrupts Table 14.4 Registers (2/2) Address Register Symbol Reset Value UART6 Transmit Interrupt Control Register, S6TIC, 006Fh Real-Time Clock Compare Interrupt Control XXXX X000b RTCCIC Register 0070h UART6 Receive Interrupt Control Register S6RIC XXXX X000b UART7 Bus Collision Detection Interrupt Control U7BCNIC, 0071h Register, Remote Control Signal Receiver 0...
Page 227: Processor Mode Register 2 (Pm2)
M16C/64A Group 14. Interrupts 14.2.1 Processor Mode Register 2 (PM2) Processor Mode Register 2 b6 b5 b4 Symbol Address Reset Value 001Eh XX00 0X01b Bit Symbol Bit Name Function — Reserved bit Set to 1. (b0) 0 : Clock is protected by PRCR register PM21 System clock protection bit 1 : Clock change disabled...
Page 228: Interrupt Control Register 1
M16C/64A Group 14. Interrupts 14.2.2 Interrupt Control Register 1 (TB5IC, TB4IC/U1BCNIC, TB3IC/U0BCNIC, BCNIC, DM0IC to DM3IC, KUPIC, ADIC, S0TIC to S2TIC, S0RIC to S2RIC, TA0IC to TA4IC, TB0IC to TB2IC, U5BCNIC/CEC1IC, S5TIC/CEC2IC, S5RIC to S7RIC, U6BCNIC/RTCTIC, S6TIC/RTCCIC, U7BCNIC/PMC0IC, S7TIC/PMC1IC, IICIC, SCLDAIC) Interrupt Control Register 1 Symbol Address...
Page 229: (Int7Ic, Int6Ic, Int3Ic, S4Ic/Int5Ic, S3Ic/Int4Ic, Int0Ic To Int2Ic)
M16C/64A Group 14. Interrupts 14.2.3 Interrupt Control Register 2 (INT7IC, INT6IC, INT3IC, S4IC/INT5IC, S3IC/INT4IC, INT0IC to INT2IC) Interrupt Control Register 2 b7 b6 b5 b4 Symbol Address Reset Value XX00 X000b Refer to the table below for symbols and addresses. Bit Symbol Bit Name Function...
Page 230: Interrupt Source Select Register 3 (Ifsr3A)
M16C/64A Group 14. Interrupts 14.2.4 Interrupt Source Select Register 3 (IFSR3A) Interrupt Source Select Register 3 b6 b5 b4 Symbol Address Reset Value IFSR3A 0205h Bit Symbol Bit Name Function 0 : One edge IFSR30 INT6 interrupt polarity select 1 : Both edges INT7 interrupt polarity select 0 : One edge IFSR31...
Page 231: Interrupt Source Select Register 2 (Ifsr2A)
M16C/64A Group 14. Interrupts 14.2.5 Interrupt Source Select Register 2 (IFSR2A) Interrupt Source Select Register 2 b6 b5 b4 Symbol Address Reset Value IFSR2A 0206h Bit Symbol Bit Name Function — Reserved bits Set to 0 (b1-b0) Interrupt request source select 0 : Not used IFSR22 1 : I...
Page 232: Interrupt Source Select Register (Ifsr)
M16C/64A Group 14. Interrupts 14.2.6 Interrupt Source Select Register (IFSR) Interrupt Source Select Register b7 b6 b5 b4 Symbol Address Reset Value IFSR 0207h Bit Symbol Bit Name Function INT0 interrupt polarity select 0 : One edge IFSR0 1 : Both edges INT1 interrupt polarity select 0 : One edge IFSR1...
Page 233: Address Match Interrupt Enable Register (Aier)
M16C/64A Group 14. Interrupts 14.2.7 Address Match Interrupt Enable Register (AIER) Address Match Interrupt Enable Register b7 b6 b5 b4 Symbol Address Reset Value AIER 020Eh XXXX XX00b Bit Symbol Bit Name Function Address match interrupt 0 0 : Interrupt disabled AIER0 enable bit 1 : Interrupt enabled...
Page 234: Address Match Interrupt Register I (Rmadi) (I = 0 To 3)
M16C/64A Group 14. Interrupts 14.2.9 Address Match Interrupt Register i (RMADi) (i = 0 to 3) Address Match Interrupt Register i (i = 0 to 3) (b23) (b16) (b15) (b8) Symbol Address Reset Value 0212h to 0210h X0 0000h RMAD0 0216h to 0214h X0 0000h RMAD1...
Page 235: Port Control Register (Pcr)
M16C/64A Group 14. Interrupts 14.2.10 Port Control Register (PCR) Port Control Register b6 b5 b4 Symbol Address Reset Value 0366h 0000 0XX0b Bit Symbol Bit Name Function Operation performed when the P1 register is read 0 : When the port is set to input, the input levels of pins P1_0 to P1_7 are read.
Page 236: Nmi/Sd Digital Filter Register (Nmidf)
M16C/64A Group 14. Interrupts 14.2.11 NMI/SD Digital Filter Register (NMIDF) NMI/SD Digital Filter Register b7 b6 b5 b4 Symbol Address Reset Value NMIDF 0369h XXXX X000b Bit Symbol Bit Name Function NMIDF0 0 : No filter 1 : CPU clock divided by 2 0 : CPU clock divided by 4 NMI/SD filter sampling clock NMIDF1...
Page 237: Types Of Interrupts
M16C/64A Group 14. Interrupts 14.3 Types of Interrupts Figure 14.1 shows Types of Interrupts. Undefined instruction (UND instruction) Overflow (INTO instruction) Software BRK instruction (non-maskable interrupt) INT instruction Interrupt Watchdog timer Special Oscillator stop/restart detect (non-maskable interrupt) Voltage monitor 1, Voltage monitor 2 Single-step Hardware Address match...
Page 238: Software Interrupts
M16C/64A Group 14. Interrupts 14.4 Software Interrupts A software interrupt occurs when executing instructions. Software interrupts are non-maskable interrupts. 14.4.1 Undefined Instruction Interrupt An undefined instruction interrupt occurs when executing the UND instruction. 14.4.2 Overflow Interrupt An overflow interrupt occurs when executing the INTO instruction with the O flag in the FLG register set to 1 (the operation resulted in an overflow).
Page 239: Hardware Interrupts
M16C/64A Group 14. Interrupts 14.5 Hardware Interrupts Hardware interrupts are classified into two types: special interrupts and peripheral function interrupts. 14.5.1 Special Interrupts Special interrupts are non-maskable interrupts. NMI Interrupt 14.5.1.1 An NMI interrupt is generated when input on the NMI pin changes state from high to low. For details on the NMI interrupt, refer to 14.9 “...
Page 240: Interrupts And Interrupt Vectors
M16C/64A Group 14. Interrupts 14.6 Interrupts and Interrupt Vectors One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respective interrupt vectors. When an interrupt request is accepted, the CPU branches to the address set in the corresponding interrupt vector.
Page 241: Relocatable Vector Tables
M16C/64A Group 14. Interrupts 14.6.2 Relocatable Vector Tables The 256 bytes beginning with the start address set in the INTB register compose a relocatable vector table area. Setting an even address in the INTB register results in the interrupt sequence being executed faster than setting an odd address.
Page 242 M16C/64A Group 14. Interrupts Table 14.7 Relocatable Vector Tables (2/2) Software Vector Address Interrupt Source Interrupt Reference Address (L) to Address (H) Number INT0 +116 to +119 (0074h to 0077h) INT1 +120 to +123 (0078h to 007Bh) 14.8 “INT Interrupt” INT2 +124 to +127 (007Ch to 007Fh) DMA2...
Page 243: Interrupt Control
M16C/64A Group 14. Interrupts 14.7 Interrupt Control 14.7.1 Maskable Interrupt Control The settings for enabling/disabling the maskable interrupts and of the acceptance priority are explained below. Note that these explanations do not apply to non-maskable interrupts. Use the I flag in the FLG register, IPL, and bits ILVL2 to ILVL0 in the corresponding interrupt control register to enable or disable a maskable interrupt.
Page 244: Interrupt Sequence
M16C/64A Group 14. Interrupts 14.7.2 Interrupt Sequence The interrupt sequence is explained here. The sequence starts when an interrupt request is accepted and ends when the interrupt routine is executed. When an interrupt request occurs during execution of an instruction, the processor determines its priority after the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle.
Page 245: Interrupt Response Time
M16C/64A Group 14. Interrupts 14.7.3 Interrupt Response Time Figure 14.4 shows the Interrupt Response Time. The interrupt response or interrupt acknowledge time denotes the time from when an interrupt request is generated until the first instruction in the interrupt routine is executed. Specifically, it consists of the time from when an interrupt request is generated until the executing instruction is completed ((a) in Figure 14.4) and the time during which the interrupt sequence is executed ((b) in Figure 14.4).
Page 246: Saving Registers
M16C/64A Group 14. Interrupts 14.7.5 Saving Registers In the interrupt sequence, the FLG register and PC are saved on the stack. At this time, the 4 upper bits of the PC and the 4 upper (IPL) and 8 lower bits in the FLG register, 16 bits in total, are saved on the stack first.
Page 247: Returning From An Interrupt Routine
M16C/64A Group 14. Interrupts 14.7.6 Returning from an Interrupt Routine The FLG register and PC saved in the stack immediately before entering the interrupt sequence are restored from the stack by executing the REIT instruction at the end of the interrupt routine. Then, the CPU returns to the program which was being executed before the interrupt request was accepted.
Page 248 M16C/64A Group 14. Interrupts Level 0 Priority level of each interrupt Priority level of each interrupt (initial value) Higher SCL/SDA Timer B1 C-bus interface Timer A4 Timer A2 UART7 transmit, NACK7, remote control 1 Timer B3, UART6 receive, ACK6 UART0 start/stop condition detection, bus collision detection UART6 start/stop condition detection, bus collision detection,...
Page 249: Multiple Interrupts
M16C/64A Group 14. Interrupts Determine and output interrupt request level to clock generating circuit I flag Address match Interrupt request accepted Watchdog timer Oscillator stop/restart detect Voltage monitor 1 Voltage monitor 2 Figure 14.9 Interrupt Priority Select Circuit 2 14.7.9 Multiple Interrupts The following shows the internal bit states when control has branched to an interrupt routine.
Page 250: Nmi Interrupt
M16C/64A Group 14. Interrupts NMI Interrupt 14.9 An NMI interrupt is generated when input to the NMI pin changes state from high to low. The NMI interrupt is a non-maskable interrupt. To use the NMI interrupt, set the PM24 bit in the PM2 register to 1 ( NMI interrupt enabled).
Page 251: 14.11 Address Match Interrupt
M16C/64A Group 14. Interrupts 14.11 Address Match Interrupt An address match interrupt is generated immediately before executing the instruction at the address indicated by the RMADi register (i = 0 to 3). Set the start address of any instruction in the RMADi register. Use bits AIER0 and AIER1 in the AIER register, and bits AIER20 and AIER21 in the AIER2 register to enable or disable the interrupt.
Page 252: 14.12 Non-Maskable Interrupt Source Discrimination
M16C/64A Group 14. Interrupts 14.12 Non-Maskable Interrupt Source Discrimination The watchdog timer interrupt, oscillator stop/restart detect interrupt, voltage monitor 1 interrupt, and voltage monitor 2 interrupt share the same interrupt vector. When using some functions together, read the detect flags of the events in an interrupt processing program, and determine the source of the interrupt. Table 14.13 lists Bits Used for Non-Maskable Interrupt Source Discrimination.
Page 253: 14.13 Notes On Interrupts
M16C/64A Group 14. Interrupts 14.13 Notes on Interrupts 14.13.1 Reading Address 00000h Do not read address 00000h by a program. When a maskable interrupt request is accepted, the CPU reads interrupt information (interrupt number and interrupt request priority level) from address 00000h during the interrupt sequence.
Page 254: 14.13.4 Changing An Interrupt Source
M16C/64A Group 14. Interrupts 14.13.4 Changing an Interrupt Source When the interrupt source is changed, the IR bit in the interrupt control register may become 1 (interrupt requested). To use an interrupt, change the interrupt source, and then set the IR bit to 0 (interrupt not requested).
Page 255: 14.13.5 Rewriting The Interrupt Control Register
M16C/64A Group 14. Interrupts 14.13.5 Rewriting the Interrupt Control Register To modify the interrupt control register, follow either of the procedures below: • Modify in places where no interrupt requests corresponding to the interrupt control register may occur. • If an interrupt request can be generated, disable that interrupt and then rewrite the interrupt control register.
Page 256: 14.13.7 Int Interrupt
M16C/64A Group 14. Interrupts 14.13.7 INT Interrupt • Either a low level of at least tw(INL) width or a high level of at least tw(INH) width is necessary for the signal input to pins INT0 through INT7 , regardless of the CPU operation clock. •...
Page 257: 15. Watchdog Timer
M16C/64A Group 15. Watchdog Timer 15. Watchdog Timer 15.1 Introduction The watchdog timer contains a 15-bit counter, and the count source protection mode (enabled/disabled) can be set. Table 15.1 lists Watchdog Timer Specifications. Refer to 6.4.8 “Watchdog Timer Reset” for details of watchdog timer reset. Figure 15.1 shows Watchdog Timer Block Diagram.
Page 258: Registers
M16C/64A Group 15. Watchdog Timer 15.2 Registers Table 15.2 Registers Address Register Symbol Reset Value 002Ch Voltage Monitor 2 Control Register VW2C 1000 0X10b 037Ch Count Source Protection Mode Register CSPR 037Dh Watchdog Timer Refresh Register WDTR 037Eh Watchdog Timer Start Register WDTS 037Fh Watchdog Timer Control Register...
Page 259: Count Source Protection Mode Register (Cspr)
M16C/64A Group 15. Watchdog Timer VW2C3 (WDT detection flag) (b3) Use this bit in an interrupt routine to determine the source of the interrupts from the watchdog timer, the oscillator stop/restart detect, the voltage monitor 1, and the voltage monitor 2. Condition to become 0: •...
Page 260: Watchdog Timer Refresh Register (Wdtr)
M16C/64A Group 15. Watchdog Timer 15.2.3 Watchdog Timer Refresh Register (WDTR) Watchdog Timer Refresh Register Symbol Address Reset Value WDTR 037Dh Function Setting 00h and then FFh refreshes the watchdog timer. After the watchdog timer interrupt occurs, refresh the watchdog timer by setting the WDTR register. 15.2.4 Watchdog Timer Start Register (WDTS) Watchdog Timer Start Register...
Page 261: Watchdog Timer Control Register (Wdc)
M16C/64A Group 15. Watchdog Timer 15.2.5 Watchdog Timer Control Register (WDC) Watchdog Timer Control Register b6 b5 b4 Symbol Address Reset Value 037Fh 00XX XXXXb Bit Symbol Bit Name Function WDC0 WDC1 WDC2 Higher-order bits (b14 to b10) of the watchdog timer can be read WDC3 WDC4 —...
Page 262: Optional Function Select Area
M16C/64A Group 15. Watchdog Timer 15.3 Optional Function Select Area In the optional function select area, the MCU state after reset and the function to prevent rewrite in parallel I/O mode are selected. The optional function select area is not an SFR, and therefore cannot be rewritten by a program. Set an appropriate value when writing a program to flash memory.
Page 263: Operations
M16C/64A Group 15. Watchdog Timer 15.4 Operations 15.4.1 Count Source Protection Mode Disabled The CPU clock is used as the watchdog timer count source when count source protection mode is disabled. Table 15.3 lists Watchdog Timer Specifications (Count Source Protection Mode Disabled). Table 15.3 Watchdog Timer Specifications (Count Source Protection Mode Disabled) Item...
Page 264: Count Source Protection Mode Enabled
M16C/64A Group 15. Watchdog Timer 15.4.2 Count Source Protection Mode Enabled fOCO-S is used as the watchdog timer count source when the count source protection mode is enabled. Table 15.4 lists the Watchdog Timer Specifications (Count Source Protection Mode Enabled). Table 15.4 Watchdog Timer Specifications (Count Source Protection Mode Enabled) Item...
Page 265: Interrupts
M16C/64A Group 15. Watchdog Timer 15.5 Interrupts Watchdog timer interrupts are non-maskable interrupts. The watchdog timer interrupt, oscillator stop/restart detect interrupt, voltage monitor 1 interrupt, and voltage monitor 2 interrupt share an vector. When using multiple functions, read the detect flag in an interrupt process program to determine the source of the interrupt.
Page 266: Notes On The Watchdog Timer
M16C/64A Group 15. Watchdog Timer 15.6 Notes on the Watchdog Timer After the watchdog timer interrupt is generated, use the WDTR register to refresh the watchdog timer counter. R01UH0136EJ0210 Rev.2.10 Page 233 of 800 Jul 31, 2012...
Page 267: 16. Dmac
M16C/64A Group 16. DMAC 16. DMAC 16.1 Introduction The direct memory access controller (DMAC) allows data to be transferred without CPU intervention. There are four DMAC channels. Each time a DMA request occurs, the DMAC transfers one (8- or 16-bit) unit of data from the source address to the destination address.
Page 268 M16C/64A Group 16. DMAC Address bus DMA0 source pointer SAR0 DMA0 destination pointer DAR0 DMA0 forward address pointer DMA1 source pointer SAR1 DMA1 destination pointer DAR1 DMA1 forward address pointer DMA0 transfer counter reload register TCR0 DMA0 transfer counter TCR0 DMA2 source pointer SAR2 DMA2 destination pointer DAR2 DMA1 transfer counter reload register TCR1...
Page 269: Registers
M16C/64A Group 16. DMAC 16.2 Registers Table 16.2 lists Registers. Do not access these registers using the DMAC. Table 16.2 Registers Address Register Symbol Reset Value 0180h 0181h DMA0 Source Pointer SAR0 0182h 0184h 0185h DMA0 Destination Pointer DAR0 0186h 0188h DMA0 Transfer Counter TCR0...
Page 270: Dmai Source Pointer (Sari) (I = 0 To 3)
M16C/64A Group 16. DMAC 16.2.1 DMAi Source Pointer (SARi) (i = 0 to 3) DMAi Source Pointer (i = 0 to 3) (b23) (b16) (b15) (b8) Symbol Address Reset Value 0182h to 0180h SAR0 0X XXXXh 0192h to 0190h SAR1 0X XXXXh SAR2 01A2h to 01A0h...
Page 271: Dmai Transfer Counter (Tcri) (I = 0 To 3)
M16C/64A Group 16. DMAC 16.2.3 DMAi Transfer Counter (TCRi) (i = 0 to 3) DMAi Transfer Counter (i = 0 to 3) (b15) (b8) Symbol Address Reset Value TCR0 0189h to 0188h Undefined 0199h to 0198h TCR1 Undefined TCR2 01A9h to 01A8h Undefined TCR3 01B9h to 01B8h...
Page 272: Dmai Control Register (Dmicon) (I = 0 To 3)
M16C/64A Group 16. DMAC 16.2.4 DMAi Control Register (DMiCON) (i = 0 to 3) DMAi Control Register (i = 0 to 3) b7 b6 b5 b4 Symbol Address Reset Value DM0CON 018Ch 0000 0X00b DM1CON 019Ch 0000 0X00b DM2CON 01ACh 0000 0X00b DM3CON 01BCh...
Page 273: Dmai Source Select Register (Dmisl) (I = 0 To 3)
M16C/64A Group 16. DMAC 16.2.5 DMAi Source Select Register (DMiSL) (i = 0 to 3) DMAi Source Select Register (i = 0 to 3) b7 b6 b5 b4 Symbol Address Reset Value DM0SL 0398h DM1SL 039Ah DM2SL 0390h DM3SL 0392h Bit Symbol Bit Name Function...
Page 274 M16C/64A Group 16. DMAC Table 16.3 Sources of DMA Request (DMA0) DSEL4 to DSEL0 DMS is 0 (Basic Source of Request) DMS is 1 (Expanded Source of Request) Falling edge of the INT0 pin 0 0 0 0 0 b –...
Page 275 M16C/64A Group 16. DMAC Table 16.5 Sources of DMA Request (DMA2) DSEL4 to DSEL0 DMS is 0 (Basic Source of Request) DMS is 1 (Expanded Source of Request) Falling edge of the INT2 pin 0 0 0 0 0 b –...
Page 276: Operations
M16C/64A Group 16. DMAC 16.3 Operations 16.3.1 DMA Enabled When data transfer starts after setting the DMAE bit in the DMiCON register to 1 (enabled), the DMAC operates as listed below (i = 0 to 3). If 1 is written to the DMAE bit when it is already set to 1, the DMAC also performs the following operations.
Page 277: Transfer Cycles
M16C/64A Group 16. DMAC 16.3.3 Transfer Cycles A transfer cycle is composed of a bus cycle to read data from a source address (source read), and a bus cycle to write data to a destination address (destination write). The number of read and write bus cycles varies with the source and destination addresses.
Page 278 M16C/64A Group 16. DMAC (1) Transfers are performed in 8-bit or 16-bit units, and the transfer source is an even address. BCLK Address Dummy CPU use Source CPU use Destination cycle RD signal WR signal Data bus Dummy CPU use Source CPU use Destination...
Page 279: Dmac Transfer Cycles
M16C/64A Group 16. DMAC 16.3.4 DMAC Transfer Cycles The formula for calculating the number of DMAC transfer cycles is shown below. Number of transfer cycles per transfer unit = Number of read cycles × j + Number of write cycles × k Table 16.8 DMAC Transfer Cycles Memory Expansion Mode...
Page 280: Single Transfer Mode
M16C/64A Group 16. DMAC 16.3.5 Single Transfer Mode In single transfer mode, the transfer stops when the DMAi transfer counter underflows. Figure 16.3 shows an Operation Example in Single Transfer Mode. Single Transfer Mode When a DMA transfer begins, the DMAS bit becomes 0. DMAS bit Underflow TCRi register...
Page 281: Repeat Transfer Mode
M16C/64A Group 16. DMAC 16.3.6 Repeat Transfer Mode In repeat transfer mode, when the DMAi transfer counter underflows, it is reloaded with the value of the DMAi transfer counter reload register and DMA transfer continues. Figure 16.4 shows an Operation Example in Repeat Transfer Mode.
Page 282: Channel Priority And Dma Transfer Timing
M16C/64A Group 16. DMAC 16.3.7 Channel Priority and DMA Transfer Timing If multiple channels among DMA0 to DMA3 are enabled and DMA transfer request signals are detected as active in the same sampling period (one period from a falling edge to the next falling edge of BCLK), the DMAS bit on each channel becomes 1 (DMA requested) at the same time.
Page 283: Interrupts
M16C/64A Group 16. DMAC 16.4 Interrupts Refer to operation examples for interrupt request generation timing. For details on interrupt control, refer to 14.7 “Interrupt Control”. Table 16.11 DMAC Interrupt Related Registers Address Register Symbol Reset Value 004Bh DMA0 Interrupt Control Register DM0IC XXXX X000b 004Ch...
Page 284: Notes On Dmac
M16C/64A Group 16. DMAC 16.5 Notes on DMAC 16.5.1 Write to the DMAE Bit in the DMiCON Register (i = 0 to 3) (Technical update number: TN-M16C-92-0306) When both of the following conditions are met, follow steps (1) and (2) below. Conditions •...
Page 285: 17. Timer A
M16C/64A Group 17. Timer A 17. Timer A 17.1 Introduction Timers A consists of timers A0 to A4. Each timer operates independently of the others. Table 17.1 lists Timer A Specifications, Table 17.2 lists Differences in Timer A Mode, Figure 17.1 shows Timer A and B Count Sources, Figure 17.2 shows Timer A Configuration, Figure 17.3 shows Timer A Block Diagram, and Table 17.3 lists I/O Ports.
Page 286 M16C/64A Group 17. Timer A fC32 fOCO-S f64TIMAB f32TIMAB f8TIMAB f1TIMAB or f2TIMAB TCK1 to TCK0 TMOD1 to TMOD0 00b: Timer mode TCS3 10b: One-shot timer mode 11b: PWM mode Timer A0 Timer A0 TCS2 to TCS0 interrupt 000b 01b: Event counter mode 001b 010b TA0TGH to TA0TGL...
Page 287 M16C/64A Group 17. Timer A Data Bus fC32 fOCO-S PWMFSi f64TIMAB TAi1 register TAi register f32TIMAB f8TIMAB Count source select f1TIMAB TCS3 or f2TIMAB TCK1 to TCK0 ·Timer: TMOD1 to TMOD0 = 00b, MR2 = 0 Reload register ·One-shot timer: TMOD1 to TMOD0 = 10b TMOD1 to TMOD0, TCS7...
Page 288: Registers
M16C/64A Group 17. Timer A 17.2 Registers Table 17.4 lists registers associated with timer A. Refer to “registers and the setting” in each mode for registers and bit settings. Table 17.4 Registers Address Register Symbol Reset Value 0012h Peripheral Clock Select Register PCLKR 0000 0011b 0015h...
Page 289: Peripheral Clock Select Register (Pclkr)
M16C/64A Group 17. Timer A 17.2.1 Peripheral Clock Select Register (PCLKR) Peripheral Clock Select Register Symbol Address Reset Value b6 b5 b4 PCLKR 0012h 0000 0011b Bit Symbol Bit Name Function Timers A and B clock select bit (clock source for timers A and 0: f2TIMAB/f2IIC PCLK0 B, the dead time timer, and...
Page 290: Timer A Count Source Select Register I (Tacsi) (I = 0 To 2)
M16C/64A Group 17. Timer A 17.2.3 Timer A Count Source Select Register i (TACSi) (i = 0 to 2) Timer A Count Source Select Register 0, Timer A Count Source Select Register 1 Symbol Address Reset Value b7 b6 b5 b4 TACS0 to TACS1 01D0h to 01D1h Bit Symbol...
Page 291: 16-Bit Pulse Width Modulation Mode Function Select Register (Pwmfs)
M16C/64A Group 17. Timer A 17.2.4 16-bit Pulse Width Modulation Mode Function Select Register (PWMFS) 16-bit Pulse Width Modulation Mode Function Select Register Symbol Address Reset Value b6 b5 b4 PWMFS 0XX0 X00Xb 01D4h Bit Symbol Bit Name Function — No register bit.
Page 292: Timer A Waveform Output Function Select Register (Tapofs)
M16C/64A Group 17. Timer A 17.2.5 Timer A Waveform Output Function Select Register (TAPOFS) Timer A Waveform Output Function Select Register Symbol Address Reset Value b7 b6 b5 b4 TAPOFS XXX0 0000b 01D5h Bit Symbol Bit Name Function POFS0 TA0OUT output polar control bit POFS1 TA1OUT output polar control bit 0 : Output waveform high-level active...
Page 293: Timer A Output Waveform Change Enable Register (Taow)
M16C/64A Group 17. Timer A 17.2.6 Timer A Output Waveform Change Enable Register (TAOW) Timer A Output Waveform Change Enable Register Symbol Address Reset Value b7 b6 b5 b4 TAOW XXX0 X00Xb 01D8h Bit Symbol Bit Name Function — No register bit. If necessary, set to 0. The read value is undefined. —...
Page 294: Timer Ai Register (Tai) (I = 0 To 4)
M16C/64A Group 17. Timer A 17.2.7 Timer Ai Register (TAi) (i = 0 to 4) Timer Ai Register (i = 0 to 4) (b15) (b8) Symbol Address Reset Value 0327h to 0326h XXXXh 0329h to 0328h XXXXh 032Bh to 032Ah XXXXh 032Dh to 032Ch XXXXh...
Page 295: Timer Ai-1 Register (Tai1) (I = 1, 2, 4)
M16C/64A Group 17. Timer A 17.2.8 Timer Ai-1 Register (TAi1) (i = 1, 2, 4) Timer Ai-1 Register (i = 1, 2, 4) (b15) (b8) Symbol Address Reset Value TA11 0303h to 0302h XXXXh TA21 0305h to 0304h XXXXh TA41 0307h to 0306h XXXXh Mode...
Page 296: One-Shot Start Flag (Onsf)
M16C/64A Group 17. Timer A 17.2.10 One-Shot Start Flag (ONSF) One-Shot Start Flag Symbol Address Reset Value b7 b6 b5 b4 ONSF 0322h Bit Name Function Bit Symbol TA0OS Timer A0 one-shot start flag TA1OS Timer A1 one-shot start flag The timer starts counting by setting this bit TA2OS Timer A2 one-shot start flag...
Page 297: Trigger Select Register (Trgsr)
M16C/64A Group 17. Timer A 17.2.11 Trigger Select Register (TRGSR) Trigger Select Register Symbol Address Reset Value b7 b6 b5 b4 TRGSR 0323h Bit Symbol Bit Name Function Timer A1 event/trigger b1 b0 TA1TGL select bit 0 : Input on TA1IN selected 1 : TB2 selected 0 : TA0 selected TA1TGH...
Page 298: Increment/Decrement Flag (Udf)
M16C/64A Group 17. Timer A 17.2.12 Increment/Decrement Flag (UDF) Increment/Decrement Flag b7 b6 b5 b4 Symbol Address Reset Value 0324h Bit Symbol Bit Name Function Timer A0 increment/ TA0UD decrement flag Timer A1 increment/ TA1UD decrement flag 0 : Decrement Timer A2 increment/ TA2UD 1 : Increment...
Page 299: Timer Ai Mode Register (Taimr) (I = 0 To 4)
M16C/64A Group 17. Timer A 17.2.13 Timer Ai Mode Register (TAiMR) (i = 0 to 4) Timer Ai Mode Register (i = 0 to 4) Symbol b7 b6 b5 b4 Address Reset Value TA0MR to TA4MR 0336h to 033Ah Bit Name Function Bit Symbol TMOD0...
Page 300: Operations
M16C/64A Group 17. Timer A 17.3 Operations 17.3.1 Common Operations 17.3.1.1 Operating Clock The count source for each timer acts as a clock, controlling such timer operations as counting and reloading. If the conditions to start counting are met, the stopped counter starts counting at the count timing of the first count source.
Page 301 M16C/64A Group 17. Timer A 17.3.1.3 Count Source Internal clocks are counted in timer mode, one-shot timer mode, PWM mode, and programmable output mode. Refer to Figure 17.1 “Timer A and B Count Sources” for details. Table 17.5 lists the Timer A Count Sources.
Page 302: Timer Mode
M16C/64A Group 17. Timer A 17.3.2 Timer Mode In timer mode, the timer counts an internally generated count source. Table 17.6 lists Timer Mode Specifications, Table 17.7 lists Registers and the Setting in Timer Mode, and Figure 17.5 shows an Operation Example in Timer Mode.
Page 303 M16C/64A Group 17. Timer A Table 17.7 Registers and Settings in Timer Mode Register Function and Setting PCLKR PCLK0 Select the count source. CPSRF CPSR Write 1 to reset the clock prescaler. PWMFS PWMFSi Set to 0. TACS0 to TACS2 7 to 0 Select the count source.
Page 304 M16C/64A Group 17. Timer A Timer Mode Timer Ai Mode Register (i = 0 to 4) Symbol Address Reset Value b6 b5 b4 TA0MR to TA4MR 0336h to 033Ah Bit Symbol Bit Name Function TMOD0 b1 b0 Operation mode select bit 0 : Timer mode TMOD1 0 : No pulse output...
Page 305 M16C/64A Group 17. Timer A Count source Count stopped Count stopped by TAiIN gate function by TAiS bit Count started Count operations 0000h n + 1 Underflow and reload TAiS bit in the TABSR register TAiIN input TAiOUT output Output inverted Low-level output POFSi = 0 Low-level output...
Page 306: Event Counter Mode (When Not Using Two-Phase Pulse Signal Processing)
M16C/64A Group 17. Timer A 17.3.3 Event Counter Mode (When Not Using Two-Phase Pulse Signal Processing) In event counter mode, the timer counts pulses from an external device, or overflows/underflows of other timers. Timers A2, A3, and A4 can count two-phase external signals. Refer to 17.3.4 “Event Counter Mode (When Processing Two-Phase Pulse Signal)”...
Page 307 M16C/64A Group 17. Timer A Table 17.9 Registers and Settings in Event Counter Mode (When Not Using Two-Phase Pulse Signal Processing) Register Function and Setting PCLKR PCLK0 - (setting unnecessary) CPSRF CPSR Write 1 to reset the clock prescaler. PWMFS PWMFSi Set to 0.
Page 308 M16C/64A Group 17. Timer A Event Counter Mode (When Not Using Two-Phase Pulse Signal Processing) Timer Ai Mode Register (i = 0 to 4) Symbol Address Reset Value b6 b5 b4 TA0MR to TA4MR 0336h to 033Ah Bit Symbol Bit Name Function TMOD0 b1 b0...
Page 309 M16C/64A Group 17. Timer A TAiIN input Overflow and reload FFFFh Decrement Counter operations Count started Increment 0000h Underflow FFFFh-n+1 Count reload stopped TAiS bit in the TABSR register TAiUD bit in the UDF register TAiOUT output POFSi = 0 Low-level output Output inverted at underflow or overflow Low-level output at count stop...
Page 310: Event Counter Mode (When Processing Two-Phase Pulse Signal)
M16C/64A Group 17. Timer A 17.3.4 Event Counter Mode (When Processing Two-Phase Pulse Signal) Timers A2, A3, and A4 can be used to count two-phase pulse signals. Table 17.10 lists Event Counter Mode Specifications (When Processing Two-Phase Pulse Signal with Timers A2, A3, and A4). Table 17.11 lists Registers and the Setting in Event Counter Mode (When Processing Two-Phase Pulse Signal).
Page 311 M16C/64A Group 17. Timer A Table 17.11 Registers and Settings in Event Counter Mode (When Processing Two-Phase Pulse Signal) Register Function and Setting PCLKR PCLK0 - (setting unnecessary) CPSRF CPSR Write 1 to reset the clock prescaler. PWMFS PWMFSi Set to 0. TACS0 to TACS2 7 to 0 - (setting unnecessary)
Page 312 M16C/64A Group 17. Timer A Event Counter Mode (When Using Two-Phase Pulse Signal Processing) Timer Ai Mode Register (i = 2 to 4) Symbol Address Reset Value b6 b5 b4 TA2MR to TA4MR 0338h to 033Ah Bit Symbol Bit Name Function TMOD0 b1 b0...
Page 313 M16C/64A Group 17. Timer A 17.3.4.1 Normal Processing The timer increments at rising edges or decrements at falling edges on the TAjIN pin when input signals to the TAjOUT (j = 2, 3) pin is high level. TAjOUT TAjIN Increment Increment Increment Decrement Decrement Decrement j = 2, 3 Figure 17.7 Normal Processing...
Page 314 M16C/64A Group 17. Timer A 17.3.4.3 Counter Initialization Using Two-Phase Pulse Signal Processing This function initializes the timer count value to 0000h using Z-phase (counter initialization) input during two-phase pulse signal processing. This function can only be used in timer A3 event counter mode during two-phase pulse signal processing, free-running type, multiply-by-4 processing, with Z-phase entered from the ZP pin.
Page 315: One-Shot Timer Mode
M16C/64A Group 17. Timer A 17.3.5 One-Shot Timer Mode In one-shot timer mode, the timer is activated only once per trigger. When the trigger occurs, the timer starts and continues operating for a given period. Table 17.12 lists One-Shot Timer Mode Specifications.
Page 316 M16C/64A Group 17. Timer A Table 17.13 Registers and Settings in One-Shot Timer Mode Register Setting PCLKR PCLK0 Select the count source. CPSRF CPSR Write 1 to reset the clock prescaler. PWMFS PWMFSi Set to 0. TACS0 to TACS2 7 to 0 Select the count source.
Page 317 M16C/64A Group 17. Timer A One-Shot Timer Mode Timer Ai Mode Register (i = 0 to 4) Symbol Address Reset Value b6 b5 b4 TA0MR to TA4MR 0336h to 033Ah Bit Symbol Bit Name Function TMOD0 b1 b0 Operation mode select bit 1 0 : One-shot timer mode TMOD1 0 : No pulse output...
Page 318 M16C/64A Group 17. Timer A Count source Count starts with a maximum of a 1.5 cycle delay of the count source after an external trigger. Reload and Reload stop counting Count operations 0000h Reload and stop After retrigger, counting when 0000h is set.
Page 319: Pulse Width Modulation (Pwm) Mode
M16C/64A Group 17. Timer A 17.3.6 Pulse Width Modulation (PWM) Mode In PWM mode, the timer outputs pulses of a given width in succession. The counter functions as either a 16-bit pulse width modulator or 8-bit pulse width modulator. Table 17.14 lists PWM Mode Specifications.
Page 320 M16C/64A Group 17. Timer A Table 17.15 Registers and Settings in PWM Mode Register Setting PCLKR PCLK0 Select the count source. CPSRF CPSR Write 1 to reset the clock prescaler. PWMFS PWMFSi Set to 0. TACS0 to TACS2 7 to 0 Select the count source.
Page 321 M16C/64A Group 17. Timer A Pulse Width Modulation (PWM) Mode Timer Ai Mode Register (i = 0 to 4) Symbol Address Reset Value b6 b5 b4 TA0MR to TA4MR 0336h to 033Ah Bit Symbol Bit Name Function TMOD0 Operation mode select bit 1 : PWM mode or programmable output mode TMOD1...
Page 322 M16C/64A Group 17. Timer A 65535 65535 65535 Reload count started 65535-n when a value other than Count started 0000h is written. Count operations Count stopped 0000h 65535-n Reload 0000h and Write 0000h to the TAi Becomes 0 stop counting. register during this period.
Page 323 M16C/64A Group 17. Timer A Count started Counter operations of 0000h lower bits 255-n Count started Counter operations of upper bits 0000h 255-n TAiS bit in the TABSR register TAiOUT output POFSi = 0 POFSi = 1 (n+1)(m+1) n(m+1) n(m+1) 255(m+1) 255(m+1) Low-level output...
Page 324: Programmable Output Mode (Timers A1, A2, And A4)
M16C/64A Group 17. Timer A 17.3.7 Programmable Output Mode (Timers A1, A2, and A4) In programmable output mode, the timer outputs low- and high-levels of pulse width successively. Table 17.16 lists Programmable Output Mode Specifications. Table 17.17 lists Registers and the Setting in Programmable Output Mode.
Page 325 M16C/64A Group 17. Timer A Table 17.17 Registers and Settings in Programmable Output Mode Register Function and Setting PCLKR PCLK0 Select the count source. CPSRF CPSR Write 1 to reset the clock prescaler. PWMFS PWMFSi Set to 1. TACS0 to TACS2 7 to 0 Select the count source.
Page 326 M16C/64A Group 17. Timer A Programmable Output Mode Timer Ai Mode Register (i = 1, 2, 4) Symbol Address Reset Value b6 b5 b4 TA0MR to TA4MR 0336h to 033Ah Bit Symbol Bit Name Function TMOD0 b1 b0 Operation mode select bit 1 : PWM mode or programmable output mode TMOD1 0 : No pulse output...
Page 327 M16C/64A Group 17. Timer A Count started Count stopped 0000h Count the updated Update registers TAi and Set to 0 value. TAi1 during this period. by a program TAiS bit Cannot be a retrigger in the TABSR register after count start Count stopped TAiIN input TAiOW bit...
Page 328: Interrupts
M16C/64A Group 17. Timer A 17.4 Interrupts Refer to individual operation examples for interrupt request generating timing. Refer to 14.7 “Interrupt Control” for details of interrupt control. Table 17.18 lists Timer A Interrupt Related Registers. Table 17.18 Timer A Interrupt Related Registers Address Register Symbol...
Page 329: Notes On Timer A
M16C/64A Group 17. Timer A 17.5 Notes on Timer A 17.5.1 Common Notes on Multiple Modes 17.5.1.1 Register Setting The timer stops after reset. Set the mode, count source, counter value, etc., using registers TAiMR, TAi, TAi1, UDF, TRGSR, PWMFS, TACS0 to TACS2, TAPOFS, PCLKR, and bits TAZIE, TA0TGL, and TA0TGH in the ONSF register before setting the TAiS bit in the TABSR register to 1 (count started) (i = 0 to 4).
Page 330: Timer A (Timer Mode)
M16C/64A Group 17. Timer A 17.5.2 Timer A (Timer Mode) 17.5.2.1 Reading the Timer The counter value can be read from the TAi register at any time while counting. However, if the counter is read at the same time as it is reloaded, the read value is FFFFh. Also, if the counter is read before it starts counting, or after a value is set in the TAi register while not counting, the set value is read.
Page 331: Timer A (Pulse Width Modulation Mode)
M16C/64A Group 17. Timer A 17.5.5 Timer A (Pulse Width Modulation Mode) 17.5.5.1 Changing Operating Modes The IR bit becomes 1 when setting a timer operating mode with any of the following: • Selecting PWM mode or programmable output mode after reset •...
Page 332: Timer A (Programmable Output Mode)
M16C/64A Group 17. Timer A 17.5.6 Timer A (Programmable Output Mode) 17.5.6.1 Changing the Operating Mode The IR bit becomes 1 when setting a timer operating mode with any of the following: • Selecting PWM mode or programmable output mode after reset •...
Page 333: 18. Timer B
M16C/64A Group 18. Timer B 18. Timer B 18.1 Introduction Timer B consists of timers B0 to B5. Each timer operates independently of the others. Table 18.1 lists Timer B Specifications, Figure 18.1 shows Timer A and B Count Sources, Figure 18.2 shows the Timer B Configuration, Figure 18.3 shows the Timer B Block Diagram, and Table 18.2 lists the I/O Ports.
Page 334 M16C/64A Group 18. Timer B fC32 fOCO-S Timer B2 overflow or underflow (to timer A count source) f64TIMAB ↑ f32TIMAB f8TIMAB TMOD1 to TMOD0 f1TIMAB TCK1 to TCK0 or f2TIMAB 00b: Timer mode TCS3 10b: Pulse period, pulse width measurement mode Timer B0 interrupt Timer B0 TCS2 to TCS0...
Page 335 M16C/64A Group 18. Timer B Data Bus PPWFS12 to PPWFS10 PPWFS22 to PPWFS20 register register TBi1 Clock source select f1TIMAB TCK1 to TCK0 Reload register Reload register TCS3 f2TIMAB or TCS7 00b: Timer mode f8TIMAB TMOD1 to TMOD0 Selector 10b: Pulse period, pulse width measurement mode f32TIMAB fC32 TCS2 to TCS0...
Page 336: Registers
M16C/64A Group 18. Timer B 18.2 Registers Table 18.3 lists registers associated with timer B. Refer to “registers and the setting” in each mode for registers and bit settings. Table 18.3 Registers Address Register Symbol Reset Value 0012h Peripheral Clock Select Register PCLKR 0000 0011b 0015h...
Page 337: Peripheral Clock Select Register (Pclkr)
M16C/64A Group 18. Timer B 18.2.1 Peripheral Clock Select Register (PCLKR) Peripheral Clock Select Register Reset Value Symbol Address b6 b5 b4 PCLKR 0012h 0000 0011b Bit Symbol Bit Name Function Timers A and B clock select bit (clock source for timers A and 0: f2TIMAB/f2IIC PCLK0 B, the dead time timer, and...
Page 338: Timer Bi Register (Tbi) (I = 0 To 5)
M16C/64A Group 18. Timer B 18.2.3 Timer Bi Register (TBi) (i = 0 to 5) Timer Bi Register (i = 0 to 5) (b15) (b8) Symbol Address Reset Value 0331h to 0330h XXXXh 0333h to 0332h XXXXh 0335h to 0334h XXXXh 0311h to 0310h XXXXh...
Page 339: Timer Bi-1 Register (Tbi1) (I = 0 To 5)
M16C/64A Group 18. Timer B 18.2.4 Timer Bi-1 Register (TBi1) (i = 0 to 5) Timer Bi-1 Register (i = 0 to 5) (b15) (b8) Symbol Address Reset Value TB01 01C1h to 01C0h XXXXh TB11 01C3h to 01C2h XXXXh TB21 01C5h to 01C4h XXXXh TB31...
Page 340: Pulse Period/Pulse Width Measurement Mode Function Select Register I (Ppwfsi) (I = 1, 2)
M16C/64A Group 18. Timer B 18.2.5 Pulse Period/Pulse Width Measurement Mode Function Select Register i (PPWFSi) (i = 1, 2) Pulse Period/Pulse Width Measurement Mode Function Select Register 1 Symbol Address Reset Value b7 b6 b5 b4 PPWFS1 XXXX X000b 01C6h Bit Symbol Bit Name...
Page 341: Timer B Count Source Select Register I (Tbcsi) (I = 0 To 3)
M16C/64A Group 18. Timer B 18.2.6 Timer B Count Source Select Register i (TBCSi) (i = 0 to 3) Timer B Count Source Select Register 0, Timer B Count Source Select Register 2 Symbol Address Reset Value b7 b6 b5 b4 TBCS0 01C8h TBCS2...
Page 342: Count Start Flag (Tabsr) Timer B3/B4/B5 Count Start Flag (Tbsr)
M16C/64A Group 18. Timer B 18.2.7 Count Start Flag (TABSR) Timer B3/B4/B5 Count Start Flag (TBSR) Count Start Flag b7 b6 b5 b4 Symbol Address Reset Value TABSR 0320h Bit Symbol Bit Name Function TA0S Timer A0 count start flag TA1S Timer A1 count start flag TA2S...
Page 343: Timer Bi Mode Register (Tbimr) (I = 0 To 5)
M16C/64A Group 18. Timer B 18.2.8 Timer Bi Mode Register (TBiMR) (i = 0 to 5) Timer Bi Mode Register (i = 0 to 5) Symbol Address Reset Value b7 b6 b5 b4 TB0MR to TB2MR 033Bh to 033Dh 00XX 0000b TB3MR to TB5MR 031Bh to 031Dh 00XX 0000b...
Page 344: Operations
M16C/64A Group 18. Timer B 18.3 Operations 18.3.1 Common Operations 18.3.1.1 Operating Clock The count source for each timer acts as a clock, controlling such timer operations as counting and reloading. 18.3.1.2 Counter Reload Timing Timer Bi starts counting from the value (n) set in the TBi register. The TBi register consists of a counter and a reload register.
Page 345 M16C/64A Group 18. Timer B 18.3.1.3 Count Source Internal clocks are counted in timer mode, pulse period measurement mode, and pulse width measurement mode. Refer to Figure 18.1 “Timer A and B Count Sources” for details. Table 18.4 lists Timer B Count Sources. f1 is any of the clocks listed below.
Page 346: Timer Mode
M16C/64A Group 18. Timer B 18.3.2 Timer Mode In timer mode, the timer counts an internally generated count source. Table 18.5 lists Timer Mode Specifications, Table 18.6 lists Registers and Setting in Timer Mode, and Figure 18.4 shows an Operation Example in Timer Mode. Table 18.5 Timer Mode Specifications Item...
Page 347 M16C/64A Group 18. Timer B Timer Mode Timer Bi Mode Register (i = 0 to 5) Symbol Address Reset Value b6 b5 b4 TB0MR to TB2MR 033Bh to 033Dh 00XX 0000b TB3MR to TB5MR 031Bh to 031Dh 00XX 0000b Bit Symbol Bit Name Function TMOD0...
Page 348: Event Counter Mode
M16C/64A Group 18. Timer B 18.3.3 Event Counter Mode In event counter mode, the timer counts pulses from an external device, or overflows and underflows of other timers. Table 18.7 lists Event Counter Mode Specifications, Table 18.8 lists Registers and Settings in Event Counter Mode, and Figure 18.5 shows an Operation Example in Event Counter Mode.
Page 349 M16C/64A Group 18. Timer B Event Counter Mode Timer Bi Mode Register (i = 0 to 5) Symbol Address Reset Value b6 b5 b4 TB0MR to TB2MR 033Bh to 033Dh 00XX 0000b TB3MR to TB5MR 031Bh to 031Dh 00XX 0000b Bit Symbol Bit Name Function...
Page 350 M16C/64A Group 18. Timer B TBiIN input Count stop by TBiS bit Count start Count operations 0000h Underflow and reload TBiS bit in the TABSR register or TBSR register IR bit in the TBiIC register Set to 0 by accepting an interrupt request, or by a program. i = 0 to 5 The above assumes the following: •...
Page 351: Pulse Period/Pulse Width Measurement Modes
M16C/64A Group 18. Timer B 18.3.4 Pulse Period/Pulse Width Measurement Modes In pulse period and pulse width measurement modes, the timer measures the pulse period or pulse width of an external signal. Table 18.9 lists Specifications of Pulse Period/Pulse Width Measurement Modes, Table 18.10 lists Registers and Settings in Pulse Period/Pulse Width Measurement Modes, Figure 18.6 shows Operation Example in Pulse Period Measurement Mode, and Figure 18.7 shows an Operation Example in Pulse Width Measurement Mode.
Page 352 M16C/64A Group 18. Timer B Table 18.10 Registers and Settings in Pulse Period/Pulse Width Measurement Modes Register Function and Setting PCLKR PCLK0 Select the count source. CPSRF CPSR Write 1 to reset the clock prescaler. Measurement result can be read when the bits in the PPWFS1 or TBi1 15 to 0 PPWFS2 register corresponding to timer Bi are 1.
Page 353 M16C/64A Group 18. Timer B Pulse Period/Pulse Width Measurement Modes Timer Bi Mode Register (i = 0 to 5) Symbol Address Reset Value b6 b5 b4 TB0MR to TB2MR 033Bh to 033Dh 00XX 0000b TB3MR to TB5MR 031Bh to 031Dh 00XX 0000b Bit Symbol Bit Name...
Page 354 M16C/64A Group 18. Timer B Count source Transfer to the TBi register (Measured value 3) (Undefined Transfer to value) the TBi register Transfer to the TBi register (Measured value 4) (Measured value 1) (Undefined (Measured value) value 2) Count start 0000h Becomes 0000h Becomes 0000h...
Page 355 M16C/64A Group 18. Timer B Count source FFFFh Transfer to (Undefined the TBi register value) Transfer to the TBi register (Measured value 3) (Measured value 1) (Undefined (Measured value) value 2) Count started 0000h Becomes 0000h Becomes 0000h TBiS bit in the TABSR register or TBSR register TBiIN input...
Page 356: Interrupts
M16C/64A Group 18. Timer B 18.4 Interrupts Refer to individual operation examples for interrupt request generating timing. Refer to 14.7 “Interrupt Control” for details of interrupt control. Table 18.11 lists Timer B Interrupt Related Registers. Table 18.11 Timer B Interrupt Related Registers Address Register Symbol...
Page 357: Notes On Timer B
M16C/64A Group 18. Timer B 18.5 Notes on Timer B 18.5.1 Common Notes on Multiple Modes 18.5.1.1 Register Setting The timer is stopped after reset. Set the mode, count source, etc., using registers TBiMR, TBCS0 to TBCS3, TBi, PCLKR, PPWFS1, and PPWFS2 before setting the TBiS bit in the TABSR or TBSR register to 1 (count started) (i = 0 to 5).
Page 358: Timer B (Pulse Period/Pulse Width Measurement Modes)
M16C/64A Group 18. Timer B 18.5.4 Timer B (Pulse Period/Pulse Width Measurement Modes) 18.5.4.1 MR3 Bit in the TBiMR Register To clear the MR3 bit to 0 by writing to the TBiMR register while the TBiS bit is 1 (count started), be sure to set the same value as previously set to bits TMOD0, TMOD1, MR0, MR1, TCK0, and TCK1, and set bit 4 to 0.
Page 359: 19. Three-Phase Motor Control Timer Function
M16C/64A Group 19. Three-Phase Motor Control Timer Function 19. Three-Phase Motor Control Timer Function 19.1 Introduction Timers A1, A2, A4, and B2 can be used to output three-phase motor drive waveforms. Table 19.1 and Table 19.2 list Three-Phase Motor Control Timer Function Specifications. Three-Phase Motor Control Timer Function Block Diagrams are shown in Figure 19.1 and Figure 19.2.
Page 360 M16C/64A Group 19. Three-Phase Motor Control Timer Function Table 19.2 Three-Phase Motor Control Timer Function Specifications (2/2) Item Specification ′ – Triangular wave modulation : ---------------------------------- - Three-phase PWM output width m+1-n+n' Sawtooth wave modulation : ------ - n, n’: Setting value of registers TA4, TA1, and TA2 (of registers TA4, TA41, TA1, TA11, TA2, and TA21 when setting the INV11 bit to 1), 0001h to FFFFh fi: Count source frequency (f1TIMAB, f2TIMAB, f8TIMAB, f32TIMAB, f64TIMAB, fOCO-S, fC32)
Page 361 M16C/64A Group 19. Three-Phase Motor Control Timer Function INV13 ICTB2 register n = 1 to 15 Circuit to set interrupt INV00 INV01 generation frequency INV11 Timer B2 Timer B2 Timer B2 underflow ICTB2 counter interrupt Reload n = 1 to 15 request bit PWCON PWCON...
Page 362 M16C/64A Group 19. Three-Phase Motor Control Timer Function IVPCR1 Reset PD8_0 INV03 PFC0 Data bus INV04 INV05 INV14 P8_0 port latch U (pin) PDRT PDRU The above diagram shows an example of U-phase. IVPCR1 : Bit in the TB2SC register INV03 to INV05 : Bits in the INVC0 register PD8_0 : Bit in the PD8 register...
Page 363: Registers
M16C/64A Group 19. Three-Phase Motor Control Timer Function 19.2 Registers Refer to “registers and settings” in each mode for register and bit settings. Three-phase motor control timer function uses timers A1, A2, A4, and B2. For other registers related to timers A1, A2, A4, and B2, refer to 17.
Page 364: Timer B2 Register (Tb2)
M16C/64A Group 19. Three-Phase Motor Control Timer Function 19.2.1 Timer B2 Register (TB2) Timer B2 Register (b15) (b8) Symbol Address Reset Value 0335h to 0334h Undefined Function Setting Range If the setting value is n, the counter frequency is n + 1 0000h to FFFFh Timers A1, A2, and A4 start each time an underflow occurs.
Page 365: Three-Phase Pwm Control Register 0 (Invc0)
M16C/64A Group 19. Three-Phase Motor Control Timer Function 19.2.3 Three-Phase PWM Control Register 0 (INVC0) Three-Phase PWM Control Register 0 b7 b6 b5 b4 Symbol Address Reset Value 0308h INVC0 Bit Symbol Bit Name Function INV00 Timer B2 underflow ICTB2 count condition select 0 : Timer B2 underflow when timer A1 reload control signal is 0 INV01...
Page 366 M16C/64A Group 19. Three-Phase Motor Control Timer Function INV03 (Three-phase motor control timer output control bit) (b3) Conditions to become 0: • The INV04 bit is 1 (simultaneous turn-on disabled) and the INV05 bit is 1 (simultaneous turn-on detected). • The INV03 bit is set to 0 by a program.
Page 367: Three-Phase Pwm Control Register 1 (Invc1)
M16C/64A Group 19. Three-Phase Motor Control Timer Function 19.2.4 Three-Phase PWM Control Register 1 (INVC1) Three-Phase PWM Control Register 1 b7 b6 b5 b4 Symbol Address Reset Value INVC1 0309h Bit Symbol Bit Name Function 0 : Timer B2 underflow Timer A1, A2 and A4 start INV10 1 : Timer B2 underflow and write to the TB2...
Page 368 M16C/64A Group 19. Three-Phase Motor Control Timer Function INV13 (Carrier wave rise/fall detect flag) (b3) The INV13 bit is enabled only when the INV06 bit is set to 0 (triangular wave modulation mode) and the INV11 bit to 1 (three-phase mode 1). INV16 (Dead time timer trigger select bit) (b6) If both of the following conditions are met, set the INV16 bit to 1 (rising edge of the three-phase output shift register output).
Page 369: Three-Phase Output Buffer Register I (Idbi) (I = 0, 1)
M16C/64A Group 19. Three-Phase Motor Control Timer Function 19.2.5 Three-Phase Output Buffer Register i (IDBi) (i = 0, 1) Three-Phase Output Buffer Register i (i = 0, 1) b7 b6 b5 b4 Symbol Address Reset Value IDB0 030Ah XX11 1111b IDB1 030Bh XX11 1111b...
Page 370: Timer B2 Interrupt Generation Frequency Set Counter (Ictb2)
M16C/64A Group 19. Three-Phase Motor Control Timer Function 19.2.7 Timer B2 Interrupt Generation Frequency Set Counter (ICTB2) Timer B2 Interrupt Generation Frequency Set Counter Symbol Address Reset Value ICTB2 030Dh Undefined Function Setting Range When a setting value is n, timer B2 interrupt is generated every nth count timer B2 underflow meets the condition 1 to 15 selected by bits INV01 to INV00 in the INVC0 register.
Page 371: Timer B2 Special Mode Register (Tb2Sc)
M16C/64A Group 19. Three-Phase Motor Control Timer Function 19.2.8 Timer B2 Special Mode Register (TB2SC) Timer B2 Special Mode Register Symbol Address Reset Value b6 b5 b4 TB2SC 033Eh X000 0000b Bit Symbol Bit Name Function 0 : Timer B2 underflow Timer B2 reload timing PWCON 1 : Timer A output at odd-numbered...
Page 372: Position-Data-Retain Function Control Register (Pdrf)
M16C/64A Group 19. Three-Phase Motor Control Timer Function 19.2.9 Position-Data-Retain Function Control Register (PDRF) Position-Data-Retain Function Control Register b7 b6 b5 b4 Symbol Address Reset Value PDRF 030Eh XXXX 0000b Bit Symbol Bit Name Function Input level at IDW pin is retained. W-phase position data retain PDRW 0: Low level...
Page 373: Port Function Control Register (Pfcr)
M16C/64A Group 19. Three-Phase Motor Control Timer Function 19.2.10 Port Function Control Register (PFCR) Port Function Control Register b7 b6 b5 b4 Symbol Address Reset Value PFCR 0318h 0011 1111b Bit Symbol Bit Name Function 0: I/O port P8_0 Port P8_0 output function PFC0 1: Three-phase PWM output (U-phase select bit...
Page 374: Operations
M16C/64A Group 19. Three-Phase Motor Control Timer Function 19.3 Operations 19.3.1 Common Operations in Multiple Modes 19.3.1.1 Carrier Wave Cycle Control Timer B2 controls the cycle of the carrier wave. In triangular wave modulation mode, the cycle of the carrier wave is double the cycle of timer B2 underflow. In sawtooth wave modulation mode, the cycle of the carrier wave is equal to the cycle of timer B2 underflow.
Page 375 M16C/64A Group 19. Three-Phase Motor Control Timer Function 19.3.1.2 Three-Phase PWM Wave Control Timer A4 controls U- and U -phase waveforms, timer A1 controls V- and V -phase waveforms, and timer A2 controls W- and W -phase waveforms. Timer Ai (i = 1, 2, 4) starts counting by a trigger selected by the INV10 bit in the INVC1 register, and generates a one-shot pulse (internal signal).
Page 376 M16C/64A Group 19. Three-Phase Motor Control Timer Function 19.3.1.5 Simultaneous Conduction Prevention This function prevents the upper and lower output signals from being active simultaneously due to program errors or unexpected program operation. When the high- and low-side output signals become active at the same time while the simultaneous conduction is disabled by the INV04 bit in the INVC0 register, the following occur: •...
Page 377 M16C/64A Group 19. Three-Phase Motor Control Timer Function 19.3.1.7 Three-Phase PWM Output Pin Select Pins U, U , V, V , W, and W output a three-phase PWM waveform when the PFCi bit (i = 0 to 5) in the PFCR register is 1 (three-phase PWM output).
Page 378 M16C/64A Group 19. Three-Phase Motor Control Timer Function 19.3.1.8 Three-Phase Output Forced Cutoff Function While the INV02 bit in the INVC0 register is 1 (three-phase motor control timer function) and the INV03 bit is 1 (three-phase motor control timer output enabled), when a low-level signal is applied to the SD pin, the INV03 bit in the INVC0 register becomes 0 (three-phase motor control timer output disabled), and pins corresponding to U, U , V, V , W and W outputs change concurrently as follows: •...
Page 379 M16C/64A Group 19. Three-Phase Motor Control Timer Function 19.3.1.9 Position-Data-Retain Function The position-data-retain function employs three position-data input pins: U-, V-, and W-phase. Input levels of IDU, IDV, and IDW inputs are retained. The falling edge or rising edge of the high-side output signal of each phase can be selected by setting the PDRT bit in the PDRF register as a position-data-retain trigger.
Page 380: Triangular Wave Modulation Three-Phase Mode 0
M16C/64A Group 19. Three-Phase Motor Control Timer Function 19.3.2 Triangular Wave Modulation Three-Phase Mode 0 Triangular wave modulation uses the timer B2 cycle as a reference cycle. Table 19.9 lists Three-Phase Mode 0 Specifications, and Figure 19.6 shows Example of Three-Phase Mode 0 Operation. Table 19.9 Three-Phase Mode 0 Specifications Item...
Page 381 M16C/64A Group 19. Three-Phase Motor Control Timer Function Table 19.10 Registers and Settings in Three-Phase Mode 0 (1/2) Register Function and Setting INV00 Disabled (Despite the setting, the ICTB2 register counts timer B2 underflow.) INV01 INV02 Set to 1 (three-phase motor control timer function used). INV03 Set to 1 (three-phase motor control timer output enabled).
Page 382 M16C/64A Group 19. Three-Phase Motor Control Timer Function Table 19.11 Registers and Settings in Three-Phase Mode 0 (2/2) Register Function and Setting TA0S Not used for three-phase motor control timer. TA1S Set to 1 when starting counting, and to 0 when stopping counting. TA2S Set to 1 when starting counting, and to 0 when stopping counting.
Page 383 M16C/64A Group 19. Three-Phase Motor Control Timer Function Triangular Waveform as a Carrier Wave Carrier wave Signal wave TB2S bit in the TABSR register Timer B2 Timer A1 reload control signal IR bit in the TB2IC register (timer B2 interrupt request) TA4 register a’...
Page 384 M16C/64A Group 19. Three-Phase Motor Control Timer Function 19.3.2.1 Three-Phase PWM Wave Output Timing Control In three-phase mode 0, when a start trigger for timers A1, A2, and A4 is generated, the counter starts counting the value of the TAi register (i = 1, 2, 4). 19.3.2.2 Three-Phase PWM Waveform Output Level Control In triangular wave modulation mode, the output levels set in registers IDB0 and IDB1 are transferred...
Page 385: Triangular Wave Modulation Three-Phase Mode 1
M16C/64A Group 19. Three-Phase Motor Control Timer Function 19.3.3 Triangular Wave Modulation Three-Phase Mode 1 Triangular wave modulation uses twice the cycles of timer B2 as a reference cycle. Table 19.12 lists Three-Phase Mode 1 Specifications, and Figure 19.7 shows Example of Three-Phase Mode 1 Operation.
Page 386 M16C/64A Group 19. Three-Phase Motor Control Timer Function Table 19.13 Registers and Settings in Three-Phase Mode 1 (1/2) Register Functions and Setting INV00 Select the timing that the ICTB2 register starts counting. INV01 INV02 Set to 1 (three-phase motor control timer function used). INV03 Set to 1 (three-phase motor control timer output enabled).
Page 387 M16C/64A Group 19. Three-Phase Motor Control Timer Function Table 19.14 Registers and Settings in Three-Phase Mode 1 (2/2) Register Function and Setting TA1TGH to Se to 01b (when using V-phase output control circuit). TA1TGL TA2TGH to Set to 01b (when using W-phase output control circuit). TA2TGL TRGSR TA3TGH to...
Page 388 M16C/64A Group 19. Three-Phase Motor Control Timer Function Triangular Waveform as a Carrier Wave Carrier wave Signal wave TB2S bit in the TABSR register Timer B2 Timer A1 reload control signal INV13 bit IR bit in the TB2IC register (timer B2 interrupt request) TA4 register TA41 register a’...
Page 389 M16C/64A Group 19. Three-Phase Motor Control Timer Function 19.3.3.1 INV13 Bit in the INVC1 Register In three-phase mode 1, the INV13 bit can be used to detect whether the cycle of the carrier wave is the first half or the last half. The INV13 bit is a flag which checks the state of timer A1 reload control signals.
Page 390 M16C/64A Group 19. Three-Phase Motor Control Timer Function 19.3.3.2 Three-Phase PWM Waveform Output Timing Control In three-phase mode 1, when a start trigger for timers A1, A2, and A4 is generated, the value set in the TAi1 register is counted first. Afterward, the values in registers TAi1 and TAi are alternately counted every time a start trigger for timers A1, A2, and A4 is generated.
Page 391 M16C/64A Group 19. Three-Phase Motor Control Timer Function 19.3.3.3 Carrier Wave Control In three-phase mode 1, the reload timing of the TB2 register can be selected by setting the PWCON bit in the TB2SC register. 19.3.3.4 Three-Phase PWM Waveform Output Level Control In triangular wave modulation mode, the output levels set in registers IDB0 and IDB1 are transferred to the three-phase output shift registers by a transfer trigger.
Page 392: Sawtooth Wave Modulation Mode
M16C/64A Group 19. Three-Phase Motor Control Timer Function 19.3.4 Sawtooth Wave Modulation Mode In this mode, the sawtooth wave is modulated. Table 19.16 lists Sawtooth Wave Modulation Mode Specifications, and Figure 19.9 shows Example of Sawtooth Wave Modulation Mode Operation. Table 19.16 Sawtooth Wave Modulation Mode Specifications Item...
Page 393 M16C/64A Group 19. Three-Phase Motor Control Timer Function Table 19.17 Registers and Settings in Sawtooth Wave Modulation Mode (1/2) Register Function and Setting INV00 Disabled (Despite the settings, the ICTB2 register counts timer B2 underflow.) INV01 INV02 Set to 1 (three-phase motor control timer function used). INV03 Set to 1 (three-phase motor control timer output enabled).
Page 394 M16C/64A Group 19. Three-Phase Motor Control Timer Function Table 19.18 Registers and Settings in Sawtooth Wave Modulation Mode (2/2) Register Function and Setting TA1TGH to Set to 01b (when using V-phase output control circuit). TA1TGL TA2TGH to Set to 01b (when using W-phase output control circuit). TA2TGL TRGSR TA3TGH to...
Page 395 M16C/64A Group 19. Three-Phase Motor Control Timer Function Sawtooth Waveform as a Carrier Wave Carrier wave Signal wave TB2S bit in the TABSR register Timer B2 IR bit in the TB2IC register (timer B2 interrupt request) Timer A4 start trigger signal Timer A4 one-shot pulse Rewrite registers IDB0 and IDB1...
Page 396 M16C/64A Group 19. Three-Phase Motor Control Timer Function 19.3.4.1 Three-Phase PWM Waveform Output Timing Control In sawtooth wave modulation mode, when a start trigger for timers A1, A2, and A4 is generated, the counter starts counting the value in the TAi register (i = 1, 2, 4). 19.3.4.2 Three-Phase PWM Waveform Output Level Control In sawtooth wave modulation mode, the output levels set in registers IDB0 and IDB1 are transferred...
Page 397: Interrupts
M16C/64A Group 19. Three-Phase Motor Control Timer Function 19.4 Interrupts The timer B2 interrupt and timer A1, A2, and A4 interrupts can be used with the three-phase motor control timer. 19.4.1 Timer B2 Interrupt When the setting value in the ICTB2 register is n, a timer B2 interrupt request is generated at the timings below.
Page 398: Notes On Three-Phase Motor Control Timer Function
M16C/64A Group 19. Three-Phase Motor Control Timer Function 19.5 Notes on Three-Phase Motor Control Timer Function 19.5.1 Timer A and Timer B Refer to 17.5 “Notes on Timer A” and 18.5 “Notes on Timer B”. Influence of SD 19.5.2 When a low-level signal is applied to the SD pin while the IVPCR1 bit in the TB2SC register is 1 (three- phase output forcible cutoff by input on SD pin enabled), the following pins become high-impedance: P7_2/CLK2/TA1OUT/V, P7_3/ CTS2 / RTS2 /TA1IN/ V , P7_4/TA2OUT/W, P7_5/TA2IN/ W , P8_0/TA4OUT/RXD5/SCL5/U, P8_1/TA4IN/ CTS5 / RTS5 / U...
Page 399: 20. Real-Time Clock
M16C/64A Group 20. Real-Time Clock 20. Real-Time Clock 20.1 Introduction The real-time clock generates a 1-second signal from a count source and counts seconds, minutes, hours, a.m./p.m., a day, and a week. It also detects matches with specified seconds, minutes, and hours. Table 20.1 lists Real-Time Clock Specifications, Figure 20.1 shows a Real-Time Clock Block Diagram, and Table 20.2 lists the I/O Port.
Page 400 M16C/64A Group 20. Real-Time Clock RTCCMP0 TOENA HRIE RTCCMP1 MNIE SEIE RTCOUT pin RTCCSEC RTCCMIN RTCCHR PMCMP Match Comparator Control RTC compare interrupt Circuit Match Comparator (IR bit in RTCCIC register) Match Comparator Match Comparator TSTART Initialize RTCCMP0 RTCCMP1 RTCCMP1 TCSTF Write 1 RTCPM...
Page 401: Registers
M16C/64A Group 20. Real-Time Clock 20.2 Registers Table 20.3 Registers Address Register Symbol Reset Value 0340h Real-Time Clock Second Data Register RTCSEC 0341h Real-Time Clock Minute Data Register RTCMIN X000 0000b 0342h Real-Time Clock Hour Data Register RTCHR XX00 0000b 0343h Real-Time Clock Day Data Register RTCWK...
Page 402: Real-Time Clock Second Data Register (Rtcsec)
M16C/64A Group 20. Real-Time Clock 20.2.1 Real-Time Clock Second Data Register (RTCSEC) Real-Time Clock Second Data Register Symbol Address Reset Value b7 b6 b5 b4 RTCSEC 0340h Setting Bit Symbol Bit Name Function Range SC00 SC01 Count 0 to 9 every second. When the digit increments, 1 First digit of second count bit 0 to 9...
Page 403: Real-Time Clock Minute Data Register (Rtcmin)
M16C/64A Group 20. Real-Time Clock 20.2.2 Real-Time Clock Minute Data Register (RTCMIN) Real-Time Clock Minute Data Register Symbol Address Reset Value b7 b6 b5 b4 RTCMIN 0341h X000 0000b Setting Bit Symbol Bit Name Function Range MN00 Count 0 to 9 every minute. MN01 When the digit increments, 1 First digit of minute count bit...
Page 404: Real-Time Clock Hour Data Register (Rtchr)
M16C/64A Group 20. Real-Time Clock 20.2.3 Real-Time Clock Hour Data Register (RTCHR) Real-Time Clock Hour Data Register Symbol Address Reset Value b7 b6 b5 b4 RTCHR 0342h XX00 0000b Setting Bit Symbol Bit Name Function Range HR00 Count 0 to 9 every hour. HR01 When the digit increments, 1 First digit of hour count bit...
Page 405: Real-Time Clock Day Data Register (Rtcwk)
M16C/64A Group 20. Real-Time Clock 20.2.4 Real-Time Clock Day Data Register (RTCWK) Real-Time Clock Day Data Register Symbol Address Reset Value b7 b6 b5 b4 XXXX X000b RTCWK 0343h Bit Symbol Bit Name Function b2 b1 b0 0 : Day 1 1 : Day 2 0 : Day 3 Day count bit...
Page 406: Real-Time Clock Control Register 1 (Rtccr1)
M16C/64A Group 20. Real-Time Clock 20.2.5 Real-Time Clock Control Register 1 (RTCCR1) Real-Time Clock Control Register 1 Symbol Address Reset Value b6 b5 b4 0000 X00Xb RTCCR1 0344h Bit Symbol Bit Name Function — Reserved bit Set to 0 (b0) Real-time clock count status 0 : Count stopped TCSTF...
Page 407 M16C/64A Group 20. Real-Time Clock RTCRST (Real-Time clock reset bit) (b4) When setting this bit to 0 after setting it to 1, the following are set automatically: • The values are reset in registers RTCSEC, RTCMIN, RTCHR, RTCWK, RTCCR2, RTCCSR, RTCCSEC, RTCCMIN, and RTCCHR.
Page 408: Real-Time Clock Control Register 2 (Rtccr2)
M16C/64A Group 20. Real-Time Clock 20.2.6 Real-Time Clock Control Register 2 (RTCCR2) Real-Time Clock Control Register 2 Symbol Address Reset Value b7 b6 b5 b4 RTCCR2 0345h X000 0000b Bit Symbol Bit Name Function 0 : Disable periodic interrupt triggered Periodic interrupt triggered every second SEIE...
Page 409 M16C/64A Group 20. Real-Time Clock Table 20.4 Periodic Interrupt Sources Factor Interrupt Source Interrupt Enable Bit Periodic interrupt Value in RTCWK register is set to 000b (1-week period) WKIE triggered every week Periodic interrupt RTCWK register is updated (1-day period) DYIE triggered every day Periodic interrupt...
Page 410: Real-Time Clock Count Source Select Register (Rtccsr)
M16C/64A Group 20. Real-Time Clock 20.2.7 Real-Time Clock Count Source Select Register (RTCCSR) Real-Time Clock Count Source Select Register Symbol Address Reset Value b6 b5 b4 RTCCSR 0346h XXX0 0000b Bit Symbol Bit Name Function b1 b0 RCS0 0 0 : f1 Count source select bit 0 1 : Do not set 1 0 : fC...
Page 411: Real-Time Clock Second Compare Data Register (Rtccsec)
M16C/64A Group 20. Real-Time Clock 20.2.8 Real-Time Clock Second Compare Data Register (RTCCSEC) Real-Time Clock Second Compare Data Register Symbol Address Reset Value b7 b6 b5 b4 X000 0000b RTCCSEC 0348h Setting Bit Symbol Bit Name Function Range SCMP00 SCMP01 First digit of second compare data bit Store compare data 0 to 9...
Page 412: Real-Time Clock Minute Compare Data Register (Rtccmin)
M16C/64A Group 20. Real-Time Clock 20.2.9 Real-Time Clock Minute Compare Data Register (RTCCMIN) Real-Time Clock Minute Compare Data Register Symbol Address Reset Value b7 b6 b5 b4 RTCCMIN 0349h X000 0000b Setting Bit Symbol Bit Name Function Range MCMP00 MCMP01 First digit of minute compare data bit Store compare data 0 to 9...
Page 413: Real-Time Clock Hour Compare Data Register (Rtcchr)
M16C/64A Group 20. Real-Time Clock 20.2.10 Real-Time Clock Hour Compare Data Register (RTCCHR) Real-Time Clock Hour Compare Data Register Symbol Address Reset Value b7 b6 b5 b4 X000 0000b RTCCHR 034Ah Setting Bit Symbol Bit Name Function Range HCMP00 HCMP01 Store compare data 0 to 9 First digit of hour compare data bit...
Page 414: Operations
M16C/64A Group 20. Real-Time Clock 20.3 Operations 20.3.1 Basic Operation The real-time clock generates a 1-second signal from the count source selected in the RTCCSR register and counts seconds, minutes, hours, a.m./p.m., a day, and a week. The day and time to start the count can be set using registers RTCSEC, RTCMIN, RTCHR, RTCWK, and the RTCPM bit in the RTCCR1 register.
Page 415 M16C/64A Group 20. Real-Time Clock Time and day change TSTART bit in RTCCR1 register ← 0 Stop real-time clock operation (not necessary when count is stopped) (counting) TCSTF bit in RTCCR1 register = 0? Yes (count stopped) RTCTIC register ← 00h Disable real-time clock periodic interrupt RTCCIC register ←...
Page 416 M16C/64A Group 20. Real-Time Clock Time and day change TSTART bit in RTCCR1 register ← 0 Stop real-time clock operation (not necessary when count is stopped or in compare mode 3) (counting) TCSTF bit in RTCCR1 register = 0? Yes (count stopped) RTCTIC register ←...
Page 417: Compare Mode
M16C/64A Group 20. Real-Time Clock 20.3.2 Compare Mode In compare mode, time data and compare data are compared, and a compare match is detected. When a match is detected, the following occur: • Compare interrupt request Refer to 20.4 “Interrupts” for details. •...
Page 418 M16C/64A Group 20. Real-Time Clock Figure 20.6 shows Difference between Compare Modes, Figure 20.7 shows Count Start/Stop Operating Example, Figure 20.8 shows Compare Mode 1 Operating Example, Figure 20.9 shows Compare Mode 2 Operating Example, and Figure 20.10 shows Compare Mode 3 Operating Example. RTCHR RTCPM RTCMIN...
Page 419 M16C/64A Group 20. Real-Time Clock BSY bit Set to 1 by a program Set to 0 by a program TSTART bit in the Count RTCCR1 register started TCSTF bit in the Count stopped RTCCR1 register RTCSEC Undefined Undefined RTCMIN RTCHR RTCPM bit RTCOUT pin output Low is output after counting starts.
Page 420 M16C/64A Group 20. Real-Time Clock BSY bit TCSTF bit in the RTCCR1 register Continue counting Compare match Undefined RTCSEC Continue using the count value Undefined RTCMIN RTCHR RTCPM bit Set to 0 by accepting an interrupt request, or by a program. IR bit in the RTCCIC register IR bit in the RTCTIC register RTCOUT pin output...
Page 421 M16C/64A Group 20. Real-Time Clock BSY bit TCSTF bit in the RTCCR1 register 1 Continue counting Compare match RTCSEC defined Undefined Set back to the reset value RTCMIN Undefined RTCHR Undefined RTCPM bit Undefined IR bit in the RTCCIC register Set to 0 by accepting an interrupt request, or by a program.
Page 422 M16C/64A Group 20. Real-Time Clock BSY bit TCSTF bit Count stopped in RTCCR1 register Compare match RTCSEC Undefined Set back to the reset value RTCMIN Undefined RTCHR Undefined RTCPM bit Undefined IR bit in RTCCIC register Set to 0 by accepting an interrupt request, or by a program.
Page 423: Interrupts
M16C/64A Group 20. Real-Time Clock 20.4 Interrupts The real-time clock generates two types of interrupt: • Periodic interrupts triggered every second, minute, hour, day, and week • Compare match interrupt See Table 20.4 Periodic Interrupt Sources for details on periodic interrupt sources, individual mode specifications and an operating example for the interrupt request generating timing.
Page 424: Notes On Real-Time Clock
M16C/64A Group 20. Real-Time Clock 20.5 Notes on Real-Time Clock 20.5.1 Starting and Stopping the Count The real-time clock uses the TSTART bit for instructing the count to start or stop, and the TCSTF bit which indicates count started or stopped. Bits TSTART and TCSTF are in the RTCCR1 register. The real-time clock starts counting and the TCSTF bit becomes 1 (count started) when the TSTART bit is set to 1 (count started).
Page 425: Time Reading Procedure In Real-Time Clock Mode
M16C/64A Group 20. Real-Time Clock 20.5.4 Time Reading Procedure in Real-Time Clock Mode In real-time clock mode, read time data bits when the BSY bit in the RTCSEC register is 0 (not while data is updated). When reading multiple registers, if data is rewritten between reading registers, an errant time will be read.
Page 426: 21. Pulse Width Modulator
M16C/64A Group 21. Pulse Width Modulator 21. Pulse Width Modulator 21.1 Introduction The pulse width modulator (PWM) consists of two independent PWM circuits. Table 21.1 lists PWM Specifications, Figure 21.1 shows Block Diagram of PWM, and Table 21.2 lists I/O Ports. Table 21.1 PWM Specifications Item...
Page 427: Registers
M16C/64A Group 21. Pulse Width Modulator Data bus PWM0 prescaler PWM0 register prelatch prelatch PWMEN0 Transfer control circuit PWM0 prescaler PWM0 register PWMCLK1 to PWMCLK0 latch latch =00b =01b PWM0 PWM0 prescaler PWM0 register =10b =11b 1/16 PWMPORT0 PD4_6 PWMSEL0 PWM0 PD9_3 The above shows an example block diagram of PWM0.
Page 428: Pwm Control Register 0 (Pwmcon0)
M16C/64A Group 21. Pulse Width Modulator 21.2.1 PWM Control Register 0 (PWMCON0) PWM Control Register 0 b6 b5 b4 Symbol Address Reset Value PWMCON0 0370h Bit Symbol Bit Name Function 0: Output PWM0 signal from P9_3 PWMSEL0 PWM0 output pin select bit 1: Output PWM0 signal from P4_6 0: Output PWM1 signal from P9_4 PWMSEL1...
Page 429: Pwmi Prescaler (Pwmprei) (I = 0, 1)
M16C/64A Group 21. Pulse Width Modulator 21.2.2 PWMi Prescaler (PWMPREi) (i = 0, 1) PWMi Prescaler (i = 0, 1) Symbol Address Reset Value PWMPRE0 0372h PWMPRE1 0374h Function Setting Range PWM cycle 00h to FFh 21.2.3 PWMi Register (PWMREGi) (i = 0, 1) PWMi Register (i = 0, 1) Symbol Address...
Page 430: Pwm Control Register 1 (Pwmcon1)
M16C/64A Group 21. Pulse Width Modulator 21.2.4 PWM Control Register 1 (PWMCON1) PWM Control Register 1 b6 b5 b4 Symbol Address Reset Value 0 0 0 PWMCON1 0376h Bit Symbol Bit Name Function 0: Output disabled PWMEN0 PWM0 output enable bit 1: Output enabled 0: Output disabled PWMEN1...
Page 431: Operations
M16C/64A Group 21. Pulse Width Modulator 21.3 Operations 21.3.1 Setting Procedure Follow the procedure below to set individual registers in order to start PWMi (i = 0, 1) output. (All SFRs are assumed to be reset. Refer the register descriptions to access registers or bits.) (1) Write output data of the port corresponding to the pin for PWMi output to the P9 or P4 register.
Page 432 M16C/64A Group 21. Pulse Width Modulator PWMENi bit in the PWMCON1 register PWMi prescaler prelatch Set the PWMREGi register by a program PWMi register prelatch PWMi prescaler latch PWMi register latch (m+1) × n Low level is output in this cycle High level is output in this cycle when PWMi register latch is 00h when PWMi register latch is FFh...
Page 433: 22. Remote Control Signal Receiver
M16C/64A Group 22. Remote Control Signal Receiver 22. Remote Control Signal Receiver 22.1 Introduction The remote control signal receiver has two circuits for checking the width and period of an of external pulse. Table 22.1 lists Remote Control Receiver Specifications, Figure 22.1 to Figure 22.3 show remote control signal receiver block diagrams, and Table 22.2 lists the I/O Ports.
Page 434 M16C/64A Group 22. Remote Control Signal Receiver INFLG PMCi internal Edge detection input signal PMCi count Counter CEFLG source PMC0 PMCiTIM PMC0RBIT PMC0DAT0 PMC0DAT1 PMC0DAT5 BFULFLG Comparator REFLG DRFLG PMCiHDPMIN Comparator CPFLG PTHDFLG PMCiHDPMAX PTD0FLG PTD1FLG CPEN PMCiD0PMIN SDFLG PMCiD0PMAX CPN2 to CPN0 PMCiD1PMIN PMC0CPD...
Page 435 M16C/64A Group 22. Remote Control Signal Receiver PMC1CON3 register Clock source CSRC1 to CSRC0 CDIV1 to CDIV0 Timer B1 underflow Divided- PMC1 count by-8 Timer B2 underflow Divided- source by-4 Divided- by-2 Sampling clock of PMC1 digital filter PMC0CON3 register CSRC1 to CSRC0 CDIV1 to CDIV0 Divided-...
Page 436: Registers
M16C/64A Group 22. Remote Control Signal Receiver 22.2 Registers Table 22.3 Registers (PMC0 Circuit) Address Register Symbol Reset Value 01F0h PMC0 Function Select Register 0 PMC0CON0 01F1h PMC0 Function Select Register 1 PMC0CON1 00XX 0000b 01F2h PMC0 Function Select Register 2 PMC0CON2 0000 00X0b 01F3h...
Page 437 M16C/64A Group 22. Remote Control Signal Receiver Table 22.4 Registers (PMC1 Circuit) Address Register Symbol Reset Value 01F8h PMC1 Function Select Register 0 PMC1CON0 XXX0 X000b 01F9h PMC1 Function Select Register 1 PMC1CON1 XXXX 0X00b 01FAh PMC1 Function Select Register 2 PMC1CON2 0000 00X0b 01FBh...
Page 438: Pmci Function Select Register 0 (Pmcicon0) (I = 0, 1)
M16C/64A Group 22. Remote Control Signal Receiver 22.2.1 PMCi Function Select Register 0 (PMCiCON0) (i = 0, 1) PMC0 Function Select Register 0 b7 b6 b5 b4 Symbol Address Reset Value PMC0CON0 01F0h Bit Symbol Bit Name Function 0: Operation disabled PMC0 operation enable bit 1: Operation enabled Input signal polarity invert...
Page 439 M16C/64A Group 22. Remote Control Signal Receiver EHOLD (Error flag hold bit) (b3) When a receive error occurs, the period when the REFLG bit in the PMC0STS register retains 1 (receive error) can be selected. Refer to “REFLG (Receive error flag) (b1)” in 22.2.5 “PMCi Status Register (PMCiSTS) (i = 0, 1)”...
Page 440: Pmci Function Select Register 1 (Pmcicon1) (I = 0, 1)
M16C/64A Group 22. Remote Control Signal Receiver 22.2.2 PMCi Function Select Register 1 (PMCiCON1) (i = 0, 1) PMC0 Function Select Register 1 b7 b6 b5 b4 Symbol Address Reset Value PMC0CON1 01F1h 00XX 0000b Bit Symbol Bit Name Function b1 b0 0 0 : Period measurement (between rising edge and rising edge)
Page 441 M16C/64A Group 22. Remote Control Signal Receiver EXSDEN (Special pattern detect block select bit) (b6) EXHDEN (Header pattern detect block select bit) (b7) Use these bits when PMC0 and PMC1 are linked and operated in pattern match mode. Otherwise, set them to 0.
Page 442: Pmci Function Select Register 2 (Pmcicon2) (I = 0, 1)
M16C/64A Group 22. Remote Control Signal Receiver 22.2.3 PMCi Function Select Register 2 (PMCiCON2) (i = 0, 1) PMC0 Function Select Register 2 b7 b6 b5 b4 Symbol Address Reset Value PMC0CON2 01F2h 0000 00X0b Bit Symbol Bit Name Function 0: Stops ENFLG PMC0 status flag...
Page 443 M16C/64A Group 22. Remote Control Signal Receiver CEFLG (Counter overflow flag) (b4) Conditions to become 0: • The EN bit in the PMCiCON0 register is 0 (PMCi operation stops) • Measurement timing selected by bits TYP1 to TYP0 in the PMCiCON1 register Condition to become 1: •...
Page 444: Pmci Function Select Register 3 (Pmcicon3) (I = 0, 1)
M16C/64A Group 22. Remote Control Signal Receiver 22.2.4 PMCi Function Select Register 3 (PMCiCON3) (i = 0, 1) PMC0 Function Select Register 3 b7 b6 b5 b4 Symbol Address Reset Value PMC0CON3 01F3h Bit Symbol Bit Name Function b3 b2 b1 b0 0 0 0 0 : Pattern match mode Mode select bit 1 1 1 1 : Input capture mode...
Page 445: Pmci Status Register (Pmcists) (I = 0, 1)
M16C/64A Group 22. Remote Control Signal Receiver 22.2.5 PMCi Status Register (PMCiSTS) (i = 0, 1) PMC0 Status Register b7 b6 b5 b4 Symbol Address Reset Value PMC0STS 01F4h Bit Symbol Bit Name Function 0: Not match CPFLG Compare match flag 1: Match 0: No error occurs REFLG...
Page 446 M16C/64A Group 22. Remote Control Signal Receiver CPFLG (Compare match flag) (b0) This bit is enabled when the CPEN bit in the PMC0CPC register is set to 1 (compare enabled). Conditions to become 0: • When the EN bit in the PMCiCON0 register is 0 (PMCi operation disabled). •...
Page 447 M16C/64A Group 22. Remote Control Signal Receiver DRFLG (Data receiving flag) (b2) The DRFLG bit indicates the receiving state of the remote control signal. The bit is 1 while receiving one frame. When data reception ends, the bit becomes 0. Conditions to become 0: •...
Page 448: Pmci Interrupt Source Register (Pmciint) (I = 0, 1)
M16C/64A Group 22. Remote Control Signal Receiver 22.2.6 PMCi Interrupt Source Register (PMCiINT) (i = 0, 1) PMC0 Interrupt Source Register b7 b6 b5 b4 Symbol Address Reset Value PMC0INT 01F5h Bit Symbol Bit Name Function Compare match flag 0: Disabled CPINT interrupt enable bit 1: Enabled...
Page 449: Pmci Header Pattern Set Register (Min) (Pmcihdpmin) (I = 0, 1) Pmci Header Pattern Set Register (Max) (Pmcihdpmax) (I = 0, 1)
M16C/64A Group 22. Remote Control Signal Receiver 22.2.7 PMCi Header Pattern Set Register (MIN) (PMCiHDPMIN) (i = 0, 1) PMCi Header Pattern Set Register (MAX) (PMCiHDPMAX) (i = 0, 1) PMCi Header Pattern Set Register (MIN) (i = 0, 1) (b15) (b8) b0 b7...
Page 450 M16C/64A Group 22. Remote Control Signal Receiver The PMCiHDPMIN The PMCiHDPMAX register value register value Header pattern The PMCiD1PMIN The PMCiD1PMAX register value register value Data 1 pattern The PMCiD0PMIN The PMCiD0PMAX register value register value Data 0 pattern The above shows the case for independent operation. For independent operation, the ranges between minimum and maximum values of header, data 0, and data 1 patterns should not overlap each other.
Page 451: Pmci Data 0 Pattern Set Register (Min) (Pmcid0Pmin) (I = 0, 1) Pmci Data 0 Pattern Set Register (Max) (Pmcid0Pmax) (I = 0, 1) Pmci Data 1 Pattern Set Register (Min) (Pmcid1Pmin) (I = 0, 1) Pmci Data 1 Pattern Set Register (Max) (Pmcid1Pmax) (I = 0, 1)
M16C/64A Group 22. Remote Control Signal Receiver 22.2.8 PMCi Data 0 Pattern Set Register (MIN) (PMCiD0PMIN) (i = 0, 1) PMCi Data 0 Pattern Set Register (MAX) (PMCiD0PMAX) (i = 0, 1) PMCi Data 1 Pattern Set Register (MIN) (PMCiD1PMIN) (i = 0, 1) PMCi Data 1 Pattern Set Register (MAX) (PMCiD1PMAX) (i = 0, 1) PMCi Data 0 Pattern Set Register (MIN) (i = 0, 1) Symbol...
Page 452: Pmci Measurements Register (Pmcitim) (I = 0, 1)
M16C/64A Group 22. Remote Control Signal Receiver See Figure 22.4 “Setting Values of the Header Pattern and Data Patterns”. When not detecting data 0, set registers PMCiD0PMIN and PMCiD0PMAX to 00h. When not detecting data 1, set registers PMCiD1PMIN and PMCiD1PMAX to 00h. When in combined operation, set registers PMC1D0PMIN, PMC1D0PMAX, PMC1D1PMIN, and PMC1D1PMAX to 00h.
Page 453: Pmc0 Receive Data Store Register I (Pmc0Dati) (I = 0 To 5)
M16C/64A Group 22. Remote Control Signal Receiver 22.2.11 PMC0 Receive Data Store Register i (PMC0DATi) (i = 0 to 5) PMC0 Receive Data Store Register i (i = 0 to 5) Address Reset Value Symbol D08Ch PMC0DAT0 PMC0DAT1 D08Dh D08Eh PMC0DAT2 D08Fh PMC0DAT3...
Page 454: Pmc0 Compare Control Register (Pmc0Cpc)
M16C/64A Group 22. Remote Control Signal Receiver 22.2.12 PMC0 Compare Control Register (PMC0CPC) PMC0 Compare Control Register b7 b6 b5 b4 Symbol Address Reset Value PMC0CPC 01F6h XXX0 X000b Bit Symbol Bit Name Function CPN0 When the setting value is n, bits n to CPN1 Compare bit specify bit 0 are compared.
Page 455: Pmc0 Compare Data Register (Pmc0Cpd)
M16C/64A Group 22. Remote Control Signal Receiver 22.2.13 PMC0 Compare Data Register (PMC0CPD) PMC0 Compare Data Register Symbol Address Reset Value PMC0CPD 01F7h Function Compare data This register is enabled when the CPEN bit in the PMC0CPC register is 1 (compare enabled). Bits to be compared are selected by bits CPN2 to CPN0 in the PMC0CPC register.
Page 456: Operations
M16C/64A Group 22. Remote Control Signal Receiver 22.3 Operations 22.3.1 Common Operations in Multiple Modes 22.3.1.1 Count Source The clock source and divisor of the count source can be selected by bits CSRC1 to CSRC0 and bits CDIV1 to CDIV0 in the PMCiCON3 register (see Figure 22.3 “Remote Control Signal Receiver Block Diagram (3/3) (PMCi Count Source)”).
Page 457 M16C/64A Group 22. Remote Control Signal Receiver 22.3.1.2 PMCi Input The options below can be selected in PMCi input (see Figure 22.2 “Remote Control Signal Receiver Block Diagram (2/3) (PMCi Input)”). • Input pin • Input polarity • Digital filter A pin to which the PMCi signal is input is selected by setting bits PSEL1 to PSEL0 in the PMCiCON2 register.
Page 458: Pattern Match Mode (Pmc0 And Pmc1 Operate Independently)
M16C/64A Group 22. Remote Control Signal Receiver 22.3.2 Pattern Match Mode (PMC0 and PMC1 Operate Independently) Pattern match mode determines whether an external pulse matches a specified pattern. The header, data 0, and data 1 patterns can be measured in PMC0 and PMC1 separately. Table 22.8 Pattern Match Mode Specifications (Independent Operation) Contents...
Page 459 M16C/64A Group 22. Remote Control Signal Receiver Table 22.9 Registers and Setting Values in Pattern Match Mode (Independent Operation) (1/2) Function Register PMC0 PMC1 Set to 1. Set to 1. SINV Select input signal polarity. Select input signal polarity. Select filter enabled or Select filter enabled or disabled.
Page 460 M16C/64A Group 22. Remote Control Signal Receiver Table 22.10 Registers and Setting Values in Pattern Match Mode (Independent Operation) (2/2) Function Register PMC0 PMC1 Set to 1 when using compare CPINT match flag interrupt. Set to 1 when using receive Set to 1 when using receive REINT error flag interrupt.
Page 461 M16C/64A Group 22. Remote Control Signal Receiver PMCi internal input signal Bits TYP1 to TYP0 are 00b (period measurement) Overflow at the setting value Counter operation Count stopped Count started Count started PMCiTIM register Bits TYP1 to TYP0 are 01b (high level width measurement) Overflow at the setting value Counter...
Page 462 M16C/64A Group 22. Remote Control Signal Receiver Frame starts Next frame starts Receive error Frame ends Data 1 Header Header Data 0 Data 0 PMCi internal input signal DRFLG PTHDFLG PTD0FLG PTD1FLG Becomes 0 when next data Receive error is REFLG is detected detected...
Page 463 M16C/64A Group 22. Remote Control Signal Receiver 22.3.2.4 Compare Function (PMC0) Values for registers PMC0CPD and PMC0DAT0 are compared. As a result, it can be detected that the first 1 to 8 bits of the remote control signal are the specific values. When using the compare function, set the following: •...
Page 464: Pattern Match Mode (Combined Operation Of Pmc0 And Pmc1)
M16C/64A Group 22. Remote Control Signal Receiver 22.3.3 Pattern Match Mode (Combined Operation of PMC0 and PMC1) PMC0 and PMC1 are combined and one remote control signal can be received. In a combined operation, data 0 and data 1 are detected in PMC0. Whether to detect the header and special data in PMC0 or PMC1 can be selected.
Page 465 M16C/64A Group 22. Remote Control Signal Receiver Table 22.12 Registers and Setting Values in Pattern Match Mode (Combined Operation) (1/2) Function Register PMC0 PMC1 Set to 1. Refer to 22.3.3.1 Set to 1. Refer to 22.3.3.1 “Setting Procedure”. “Setting Procedure”. SINV Set to 0.
Page 466 M16C/64A Group 22. Remote Control Signal Receiver Table 22.13 Registers and Setting Values in Pattern Match Mode (Combined Operation) (2/2) Function Register PMC0 PMC1 Set to 1 when using compare CPINT match flag interrupt. Set to 1 when using receive REINT Set to 0.
Page 467 M16C/64A Group 22. Remote Control Signal Receiver 22.3.3.1 Setting Procedure To start or stop counting, follow these steps: (1) Set bits CSRC1 to CSRC0 and bits CDIV1 to CDIV0 in the PMCiCON3 register. (2) Set bits PSEL1 to PSEL0 in the PMCiCON2 register and bits FIL and SINV in the PMCiCON0 register.
Page 468 M16C/64A Group 22. Remote Control Signal Receiver 22.3.3.5 Compare Function (PMC0) Values from registers PMC0CPD and PMC0DAT0 are compared. From the result, reception of the specified value which is selected from the first 1 to 8 bits of the remote control signal can be detected. When using the compare function, set the following: •...
Page 469: Input Capture Mode (Operating Pmc0 And Pmc1 Independently)
M16C/64A Group 22. Remote Control Signal Receiver 22.3.4 Input Capture Mode (Operating PMC0 and PMC1 Independently) The input capture mode measures width or period of external pulse. PMC0 and PMC1 can be measured independently. Table 22.15 Input Capture Mode Specifications (Independent Operation) Content Item PMC0 Circuit...
Page 470 M16C/64A Group 22. Remote Control Signal Receiver Table 22.16 Registers and Setting Values in Input Capture Mode (Independent Operation) (1/2) Function Register PMC0 PMC1 Set to 1. Set to 1. SINV Select input signal polarity. Select input signal polarity. Select filter enabled or disabled. Select filter enabled or disabled.
Page 471 M16C/64A Group 22. Remote Control Signal Receiver Table 22.17 Registers and Setting Values in Input Capture Mode (Independent Operation) (2/2) Function Register PMC0 PMC1 CPINT Set to 0. REINT Set to 0. Set to 0. DRINT Set to 0. Set to 0. BFULINT Set to 0.
Page 472 M16C/64A Group 22. Remote Control Signal Receiver PMCi internal input signal EN bit FFFFh Counter operation Count started Counter value Bits TYP1 to TYP0 are 00b (period measurement (between rising edge and rising edge) PMCiTIM register IR bit The bit becomes 0 when an interrupt request is accepted, or by setting the bit to 0.
Page 473: Input Capture Mode (Simultaneous Count Operation Of Pmc0 And Pmc1)
M16C/64A Group 22. Remote Control Signal Receiver 22.3.5 Input Capture Mode (Simultaneous Count Operation of PMC0 and PMC1) PMC0 and PMC1 inputs can be measured simultaneously in input capture mode. Table 22.18 Input Capture Mode Specifications (Simultaneous Count Operation) Content Item PMC0 Circuit PMC1 Circuit...
Page 474 M16C/64A Group 22. Remote Control Signal Receiver Table 22.19 Registers and Setting Values in Input Capture Mode (Simultaneous Count Operation) (1/2) Function Register PMC0 PMC1 Set to 1. (Refer to 22.3.5.1 “Setting Set to 1. (Refer to 22.3.5.1 “Setting Procedure”). Procedure”).
Page 475 M16C/64A Group 22. Remote Control Signal Receiver Table 22.20 Registers and Setting Values in Input Capture Mode (Simultaneous Count Operation) (2/2) Function Register PMC0 PMC1 CPINT Set to 0. REINT Set to 0. Set to 0. DRINT Set to 0. Set to 0.
Page 476: Interrupts
M16C/64A Group 22. Remote Control Signal Receiver 22.4 Interrupts The remote control signal receiver has remote control signal receiver 0 interrupt and remote control signal receiver 1 interrupt. The remote control signal receiver 0 interrupt and remote control signal receiver 1 interrupt are interrupts in PMC0 and PMC1, respectively.
Page 477 M16C/64A Group 22. Remote Control Signal Receiver Figure 22.10 shows Remote Control Signal Receiver Interrupts. CPINT DRINT1 DRINT0 DRINT CPFLG REINT REFLG DRFLG BFULINT BFULFLG PTHDINT PTHDFLG PMC0 interrupt PTDINT PTD0FLG (IR bit in the PMC0IC register) PTD1FLG TIMINT Timer measure interrupt request SDINT SDFLG CEINT...
Page 478 M16C/64A Group 22. Remote Control Signal Receiver Refer to 14.7 “Interrupt Control” for details on interrupt control. Table 22.22 lists Registers Associated with Remote Control Signal Receiver Interrupts. Table 22.22 Registers Associated with Remote Control Signal Receiver Interrupts Address Register Symbol Reset Value UART7 Bus Collision Detection Interrupt Control...
Page 479: Notes On Remote Control Signal Receiver
M16C/64A Group 22. Remote Control Signal Receiver 22.5 Notes on Remote Control Signal Receiver 22.5.1 Starting/Stopping PMCi The EN bit in the PMCiCON0 register controls the start/stop of PMCi. The ENFLG bit in the PMCiCON2 register indicates that operation started/stopped. The PMCi circuit starts operating by setting the EN bit to 1 (operation enabled) and the ENFLG bit becomes 1 (operating).
Page 480: Combined Operation
M16C/64A Group 22. Remote Control Signal Receiver 22.5.4 Combined Operation When using combined operation, set same value to bits TYP1 to TYP0 in the PMC0CON1 register and bits TYP1 to TYP0 in the PMC1CON1 register. R01UH0136EJ0210 Rev.2.10 Page 447 of 800 Jul 31, 2012...
Page 481: Serial Interface Uarti (I = 0 To 2, 5 To 7)
M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.1 Introduction Each UART has a dedicated timer to generate a transmit/receive clock, and operates independently of the others.
Page 482 M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) PCLK1 f2SIO f1SIO or f2SIO f1SIO f8SIO f32SIO TXD0 RXD polarity polarity RXD0 switching circuit switching SMD2 to SMD0 UART reception circuit 100b, 101b, 110b Receive Transmit/ Reception 1/16...
Page 483 M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) PCLK1 f2SIO f1SIO or f2SIO f1SIO f8SIO f32SIO TXD1 RXD polarity RXD1 polarity switching circuit switching UART reception SMD2 to SMD0 circuit 100b, 101b, 110b Receive Transmit/ 1/16 clock...
Page 484 M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) PCLK1 f2SIO f1SIO or f2SIO f1SIO f8SIO f32SIO TXDi RXD polarity polarity RXDi switching circuit switching UART reception SMD2 to SMD0 circuit 100b, 101b, 110b Receive Transmit/ 1/16 clock...
Page 485 M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) IOPOL Not inverted RXDi RXD data inverse circuit Inverted Clock sync type UART (7 bits) UART PRYE (8 bits) clock sync STPS UART (7 bits) type UARTi receive register disabled PAR enabled...
Page 486: Registers
M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.2 Registers Table 23.3 and Table 23.4 list registers associated with UART0 to UART2 and UART5 to UART7. Refer to “Registers Used and Settings” in each mode for the settings of registers and bits. Table 23.3 Registers (1/2) Address...
Page 487 M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) Table 23.4 Registers (2/2) Address Register Symbol Reset Value 026Dh UART2 Transmit/Receive Control Register 1 U2C1 0000 0010b 026Eh UART2 Receive Buffer Register U2RB 026Fh 0284h UART5 Special Mode Register 4 U5SMR4 0285h...
Page 488: Peripheral Clock Select Register (Pclkr)
M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.2.1 Peripheral Clock Select Register (PCLKR) Peripheral Clock Select Register Symbol Address Reset Value b6 b5 b4 PCLKR 0012h 0000 0011b Bit Symbol Bit Name Function Timers A and B clock select bit (clock source for timers A and 0: f2TIMAB/f2IIC...
Page 489: Uarti Transmit/Receive Mode Register (Uimr) (I = 0 To 2, 5 To 7)
M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.2.2 UARTi Transmit/Receive Mode Register (UiMR) (i = 0 to 2, 5 to 7) UARTi Transmit/Receive Mode Register (i = 0 to 2, 5 to 7) Symbol Address Reset Value...
Page 490: Uarti Bit Rate Register (Uibrg) (I = 0 To 2, 5 To 7)
M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.2.3 UARTi Bit Rate Register (UiBRG) (i = 0 to 2, 5 to 7) UARTi Bit Rate Register (i = 0 to 2, 5 to 7) Symbol Address Reset Value...
Page 491: Uarti Transmit/Receive Control Register 0 (Uic0) (I = 0 To 2, 5 To 7)
M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.2.5 UARTi Transmit/Receive Control Register 0 (UiC0) (i = 0 to 2, 5 to 7) UARTi Transmit/Receive Control Register 0 (i = 0 to 2, 5 to 7) Symbol Address Reset Value...
Page 492 M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) NCH (Data output select bit) (b5) TXD2/SDA2 and SCL2 are N-channel open drain outputs. They cannot be set as CMOS outputs. Nothing is assigned to the NCH bit in the U2C0 register. If necessary, set this bit to 0. This function is used to set the P-channel transistor of the CMOS output buffer always off, but not to change pins TXDi/SDAi and SCLi to open drain output completely.
Page 493: Uarti Transmit/Receive Control Register 1 (Uic1) (I = 0 To 2, 5 To 7)
M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.2.6 UARTi Transmit/Receive Control Register 1 (UiC1) (i = 0 to 2, 5 to 7) UARTi Transmit/Receive Control Register 1 (i = 0, 1) b7 b6 b5 b4 Symbol Address After Reset...
Page 494: Uarti Receive Buffer Register (Uirb) (I = 0 To 2, 5 To 7)
M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.2.7 UARTi Receive Buffer Register (UiRB) (i = 0 to 2, 5 to 7) UARTi Receive Buffer Register (i = 0 to 2, 5 to 7) (b15) (b8) Symbol...
Page 495 M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) FER (Framing error flag) (b13) The FER bit is disabled when bits SMD2 to SMD0 are set to 001b (clock synchronous serial I/O mode) or to 010b (I C mode).
Page 496: Uart Transmit/Receive Control Register 2 (Ucon)
M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.2.8 UART Transmit/Receive Control Register 2 (UCON) UART Transmit/Receive Control Register 2 b7 b6 b5 b4 Symbol Address After Reset X000 0000b UCON 0250h Bit symbol Bit Name Function UART0 transmit interrupt...
Page 497: Uarti Special Mode Register 4 (Uismr4) (I = 0 To 2, 5 To 7)
M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.2.9 UARTi Special Mode Register 4 (UiSMR4) (i = 0 to 2, 5 to 7) UARTi Special Mode Register 4 (i = 0 to 2, 5 to 7) Symbol Address Reset Value...
Page 498 M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) ACKD (ACK data bit) (b4) ACKC (ACK data output enable bit) (b5) SWC9 (SCL wait auto insert bit 3) (b7) This bit is used in slave mode of I C mode.
Page 499: Uarti Special Mode Register 3 (Uismr3) (I = 0 To 2, 5 To 7)
M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.2.10 UARTi Special Mode Register 3 (UiSMR3) (i = 0 to 2, 5 to 7) UARTi Special Mode Register 3 (i = 0 to 2, 5 to 7) Symbol Address Reset Value...
Page 500: Uarti Special Mode Register 2 (Uismr2) (I = 0 To 2, 5 To 7)
M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.2.11 UARTi Special Mode Register 2 (UiSMR2) (i = 0 to 2, 5 to 7) UARTi Special Mode Register 2 (i = 0 to 2, 5 to 7) Symbol Address Reset Value...
Page 501: Uarti Special Mode Register (Uismr) (I = 0 To 2, 5 To 7)
M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.2.12 UARTi Special Mode Register (UiSMR) (i = 0 to 2, 5 to 7) UARTi Special Mode Register (i = 0 to 2, 5 to 7) Symbol Address Reset Value...
Page 502: Operations
M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.3 Operations 23.3.1 Clock Synchronous Serial I/O Mode The clock synchronous serial I/O mode uses a transmit/receive clock to transmit/receive data. Table 23.5 lists the Clock Synchronous Serial I/O Mode Specifications. Table 23.5 Clock Synchronous Serial I/O Mode Specifications Item...
Page 503 M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) Table 23.6 lists Pin Functions in Clock Synchronous Serial I/O Mode (Multiple Transmit/Receive Clock Output Pin Function Not Selected). Table 23.7 lists P6_4 Pin Functions in Clock Synchronous Serial I/O Mode.
Page 504 M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) Table 23.8 Registers Used and Settings in Clock Synchronous Serial I/O Mode Register Bits Function PCLKR PCLK1 Select the count source for the UiBRG register. 0 to 7 Set transmission data.
Page 505 M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) (1) Example of Transmit Timing (Internal Clock Selected) Transmit/receive clock TE bit in the UiC1 register Set the data in the UiTB register. TI bit in the UiC1 register Data is transferred from the UiTB register to the UARTi transmit register.
Page 506 M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.3.1.1 CLK Polarity Select Function Use the CKPOL bit in the UiC0 register (i = 0 to 2, 5 to 7) to select the transmit/receive clock polarity. Figure 23.6 shows the Transmit/Receive Clock Polarity.
Page 507 M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.3.1.2 LSB First/MSB First Select Function Use the UFORM bit in the UiC0 register (i = 0 to 2, 5 to 7) to select the bit order. Figure 23.7 shows the Bit Order.
Page 508 M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.3.1.4 Serial Data Logic Switching Function When the UiLCH bit in the UiC1 register (i = 0 to 2, 5 to 7) is 1 (inverted), the data written to the UiTB register has its logic inverted before being transmitted.
Page 509 M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) CTS/RTS Function 23.3.1.6 The CTS function is used to start transmit/receive operation when a low signal is applied to the CTSi / RTSi (i = 0 to 2, 5 to 7) pin. Transmit/receive operation begins when input to the CTSi / RTSi pin becomes low.
Page 510: Clock Asynchronous Serial I/O (Uart) Mode
M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.3.2 Clock Asynchronous Serial I/O (UART) Mode The UART mode allows data to be transmitted/received after setting the desired bit rate and bit order. Table 23.9 lists the UART Mode Specifications. Table 23.9 UART Mode Specifications Item...
Page 511 M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) Table 23.10 lists I/O Pin Functions in UART Mode. Table 23.11 lists the P6_4 Pin Functions in UART Mode. Note that for a period from when the UARTi operating mode is selected to when transmission starts, the TXDi pin outputs a high-level signal.
Page 512 M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) Table 23.12 Registers Used and Settings in UART Mode Register Bits Function PCLKR PCLK1 Select the count source for the UiBRG register. UiTB 0 to 8 Set transmission data.
Page 513 M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) (1) 8-bit Data Transmit Timing (with a Parity Bit and 1 Stop Bit) The transmit/receive clock stops once because a high-level signal is applied to the CTS pin when the stop bit is verified. The transmit/receive clock resumes running as soon as a low-level signal is applied to the CTS pin.
Page 514 M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) Example of Receive Timing When Character Bit Length is 8 Bits (Parity Disabled, 1 Stop Bit) Clock divided by UiBRG RE bit in UiC1 register Stop bit Start bit RXDi Sampled as low...
Page 515 M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.3.2.1 Bit Rate In UART mode, the frequency set by the UiBRG register (i = 0 to 2, 5 to 7) divided by 16 becomes a bit rate.
Page 516 M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.3.2.2 LSB First/MSB First Select Function As shown in Figure 23.14, the bit order can be selected by setting the UFORM bit in the UiC0 register. This function is enabled when the character bit length is 8 bits.
Page 517 M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.3.2.3 Serial Data Logic Switching Function The logic of the data written to the UiTB register is inverted and then transmitted. Similarly, the inverted logic of the received data is read when the UiRB register is read. (1) UiLCH bit in the UiC1 register = 0 (not inverted) Transmit/ High...
Page 518 M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) CTS/RTS Function 23.3.2.5 The CTS function is used to start transmit operation when a low signal is applied to the CTSi / RTSi (i = 0 to 2, 5 to 7) pin. Transmit operation begins when input to the CTSi / RTSi pin becomes low. If the input level is switched from low to high during transmit operation, the operation stops after the ongoing transmit/receive operation is completed.
Page 519: Special Mode 1 (I 2 C Mode)
M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.3.3 Special Mode 1 (I C Mode) C mode is compatible with the simplified I C interface. Table 23.14 lists the I C Mode Specifications. Table 23.16 and Table 23.17 list the Registers Used and Settings in I C Mode.
Page 520 M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) SDAi Start and stop condition generation block STSPSEL = 1 DMA0 to DMA3 request SDA (STSP) Delay SCL (STSP) circuit STSPSEL = 0 IICM2 = 1 Transmission UARTi transmit, NACKi register...
Page 521 M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) Table 23.16 Registers Used and Settings in I C Mode (1/2) Function Register Bits Master Slave Select the count source for the UiBRG Select the count source for the UiBRG PCLKR PCLK1 register.
Page 522 M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) Table 23.17 Registers Used and Settings in I C Mode (2/2) Function Register Bits Master Slave IICM2 See Table 23.18 “I C Mode Functions”. See Table 23.18 “I C Mode Functions”.
Page 523 M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) In I C mode, functions and timings vary depending on the IICM2 bit setting in the UiSMR2 register. Figure 23.20 shows Transfer to UiRB Register and Interrupt Timing. See Figure 23.20 for the timing of transferring data to the UiRB register, the bit position of the data stored in the UiRB register, types of interrupts, interrupt requests, and DMA request generation timing.
Page 524 M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) (1) IICM2 = 0 (ACK and NACK interrupts), CKPH = 1 (clock delay) Initial value and 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit...
Page 525 M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.3.3.1 Detecting Start and Stop Conditions Start and stop conditions are detected by their respective detectors. Whether a start or a stop condition has been detected is determined. A start condition detect interrupt request is generated when the SDAi pin changes state from high to low while the SCLi pin is in the high state.
Page 526 M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) (1) Slave mode STSPSEL bit BBS bit ACK/ NACK Start condition detection Stop condition detection interrupt request generated interrupt request generated (2) Master mode (when CKPH is 1) STAREQ bit STPREQ bit STSPSEL bit...
Page 527 M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) Start condition generation BBS bit in the UiSMR Wait for bus release. register is 1 ? (bus busy) 0 (bus free) UiSMR4 ← 70h Set the STSPSEL bit to 0. UiMR ←...
Page 528 M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.3.3.3 Arbitration The MCU determines whether the transmit data matches data input to the SDAi pin on the rising edge of SCLi. If it does not match the input data, arbitration takes place at the SDAi pin by stopping data output.
Page 529 M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) (1) SWC bit function SDAi (master) SCLi (master) SDAi (slave) Address bit comparison, acknowledge generation SCLi (slave) Clock line is Clock line is held low released (2) SWC9 bit function (SWC = 0) SDAi (master)
Page 530 M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) (1) Clock synchronization Clock output of other device SCLi Internal clock Change the internal clock Resume Stop counting signal from high to low to counting start counting low period (2) Synchronization period Internal clock SCLi...
Page 531 M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) To be compatible with SCL low hold from another device, the high time count starts after high is determined. 1 / (2f (theoretical value)) 1 / (2f (theoretical value)) SCL clock Noise filter width + 1 to 1.5 cycles...
Page 532 M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.3.3.7 SDA Digital Delay When transferring data with the I 2 C-bus, change the data while the SCL clock is low. When SDA is changed while the SCL clock is a high, the change is recognized as one of the corresponding conditions (see 23.5.3.4 “Setup and Hold Times When Generating a Start/Stop Condition”).
Page 533 M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) UARTi Transmit Buffer Register (UiTB) b8 b7 Set these bits to 1 to release the SDAi pin 0: ACK generated 1: NACK generated Figure 23.30 UiTB Register Setting (SDA Input) - ACK (Receiver) Released (Hi-Z)
Page 534: Special Mode 2
M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.3.4 Special Mode 2 In special mode 2, the serial interface module allows serial communication between one master and multiple slaves. The transmit/receive clock polarity and phase are selectable. Table 23.20 lists Special Mode 2 Specifications.
Page 535 M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) P1_3 P1_2 P7_2 (CLK2) P7_1 (RXD2) P7_0 (TXD2) MCU (master) MCU (slave) MCU (slave) Figure 23.32 Serial Bus Communication Control Example in Special Mode 2 (UART2) Table 23.21 I/O Pin Functions in Special Mode 2 Pin Name...
Page 536 M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) Table 23.22 Registers Used and Settings in Special Mode 2 Register Bits Function PCLKR PCLK1 Select the count source for the UiBRG register. 0 to 7 Set transmission data.
Page 537 M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.3.4.1 Clock Phase Setting Function One of four combinations of transmit/receive clock phases and polarities can be selected using the CKPH bit in the UiSMR3 register and the CKPOL bit in the UiC0 register. Make sure the transmit/receive clock polarity and phase are the same for the master and slaves to be used for communication.
Page 538: Special Mode 3 (Ie Mode)
M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.3.5 Special Mode 3 (IE Mode) In this mode, 1 bit of IEBus is approximated by 1 byte of UART mode waveform. Table 23.23 lists the Registers Used and Settings in IE Mode. Figure 23.34 shows the Bus Collision Detect Function-Related Bits.
Page 539 M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) (1) ABSCS bit in UiSMR register (bus collision detect sampling clock select) (i = 0 to 2, 5 to 7) When ABSCS is 0, bus collision is determined at the rising edge of the transmit/receive clock. Transmit/receive clock TXDi RXDi...
Page 540: Special Mode 4 (Sim Mode) (Uart2)
M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.3.6 Special Mode 4 (SIM Mode) (UART2) In this mode, the serial interface module allows SIM interface devices to communicate in UART mode. Both direct and inverted formats are available. The TXD2 pin outputs a low-level signal when a parity error is detected.
Page 541 M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) Table 23.25 Registers Used and Settings in SIM Mode Register Function 0 to 7 Set transmit data. U2TB 0 to 7 Received data can be read. U2RB OER, FER, PER, SUM Error flag U2BRG...
Page 542 M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) (1) Transmit Timing Transmit/receive clock TE bit in U2C1 register Data is written to the U2TB register. (Note 1) TI bit in U2C1 register Data is transferred from the U2TB register to the UART2 transmit Stop Start...
Page 543 M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) Figure 23.36 shows the Example of SIM Interface Connection. Connect pins TXD2 and RXD2, and then place a pull-up resistance. SIM card TXD2 RXD2 Figure 23.36 Example of SIM Interface Connection 23.3.6.1 Parity Error Signal Output The parity error signal is enabled by setting the U2ERE bit in the U2C1 register to 1 (error signal...
Page 544 M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.3.6.2 Formats Two formats are available: direct format and inverse format. For direct format, set the PRYE bit in the U2MR register to 1 (parity enabled), the PRY bit to 1 (even parity), the UFORM bit in the U2C0 register to 0 (LSB first), and the U2LCH bit in the U2C1 register to 0 (not inverted).
Page 545: Interrupts
M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.4 Interrupts UART0 to UART2, UART5 to UART7 include interrupts by transmission, reception, ACK, NACK, start/stop condition detection, and bus collision detection. 23.4.1 Interrupt Related Registers Refer to operation examples in each mode for interrupt sources and interrupt request generation timing.
Page 546: Reception Interrupt
M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) Some interrupts of UART0 to UART2 and UART5 to UART7 share interrupt vectors and interrupt control registers with other peripheral functions. When using these interrupts, select them by interrupt source select registers.
Page 547: Notes On Serial Interface Uarti (I = 0 To 2, 5 To 7)
M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.5 Notes on Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.5.1 Common Notes on Multiple Modes Influence of SD 23.5.1.1 When a low-level signal is applied to the SD pin while the IVPCR1 bit in the TB2SC register is 1 (three- phase output forcible cutoff by input on SD pin enabled), the following pins become high-impedance: P7_2/CLK2/TA1OUT/V, P7_3/ CTS2 / RTS2 /TA1IN/ V , P7_4/TA2OUT/W, P7_5/TA2IN/ W , P8_0/TA4OUT/RXD5/SCL5/U, P8_1/TA4IN/ CTS5 / RTS5 / U...
Page 548: Special Mode 1 (I C Mode)
M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.5.2.3 Reception In clock synchronous serial I/O mode, a shift clock is generated by activating a transmitter. Set the UARTi-associated registers for a transmit operation even if the MCU is used for a receive operations only.
Page 549 M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.5.3.3 Low/High-level Input Voltage and Low-level Output Voltage The low-level input voltage, high-level input voltage, and low-level output voltage differ from the I bus specification. Refer to the recommended operating conditions for I/O ports which share the pins with SCL and SDA.
Page 550: Special Mode 4 (Sim Mode)
M16C/64A Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.5.3.5 Restrictions on the Bit Rate When Using the UiBRG Count Source In I C mode, set the UiBRG register to a value of 03h or greater. A maximum of three UiBRG count source cycles are necessary until the internal circuit acknowledges the SCL clock level.
Page 551: 24. Serial Interface Si/O3 And Si/O4
M16C/64A Group 24. Serial Interface SI/O3 and SI/O4 24. Serial Interface SI/O3 and SI/O4 24.1 Introduction SI/O3 and SI/O4 are dedicated clock-synchronous serial I/O ports. Table 24.1 lists SI/O3 and SI/O4 Specifications. Figure 24.1 shows SI/O3 and SI/O4 Block Diagram, and Table 24.2 lists the I/O Ports. Table 24.1 SI/O3 and SI/O4 Specifications Item...
Page 552 M16C/64A Group 24. Serial Interface SI/O3 and SI/O4 Clock source select f2SIO PCLK1 SMi1 to SMi0 f1SIO f8SIO Synchronous 1/(n + 1) circuit f32SIO SiBRG register SMi3 SMi4 SMi6 SMi6 CLK polarity SI/Oi interrupt SI/O counter i CLKi reversing (IR bit in the SiIC circuit register) SMi2...
Page 553: Registers
M16C/64A Group 24. Serial Interface SI/O3 and SI/O4 24.2 Registers Table 24.3 lists registers associated with SI/O3 and SI/O4. Table 24.3 Registers Address Register Symbol Reset Value 0012h Peripheral Clock Select Register PCLKR 0000 0011b 0270h SI/O3 Transmit/Receive Register S3TRR 0272h SI/O3 Control Register 0100 0000b...
Page 554: Peripheral Clock Select Register (Pclkr)
M16C/64A Group 24. Serial Interface SI/O3 and SI/O4 24.2.1 Peripheral Clock Select Register (PCLKR) Peripheral Clock Select Register Reset Value b6 b5 b4 Symbol Address PCLKR 0012h 0000 0011b Bit Symbol Bit Name Function Timers A and B clock select bit (clock source for timers A and 0: f2TIMAB/f2IIC PCLK0...
Page 555: Oi Control Register (Sic) (I = 3, 4)
M16C/64A Group 24. Serial Interface SI/O3 and SI/O4 24.2.3 SI/Oi Control Register (SiC) (i = 3, 4) SI/Oi Control Register (i = 3, 4) Symbol Address Reset Value b7 b6 b5 b4 0100 0000b 0272h 0100 0000b 0276h Bit symbol Bit Name Function b1 b0...
Page 556: Oi Bit Rate Register (Sibrg) (I = 3, 4)
M16C/64A Group 24. Serial Interface SI/O3 and SI/O4 24.2.4 SI/Oi Bit Rate Register (SiBRG) (i = 3, 4) SI/Oi Bit Rate Register (i = 3, 4) Symbol Address Reset Value Undefined S3BRG 0273h S4BRG 0277h Undefined Function Setting Range SiBRG divides the count source by n + 1 where n = set 00h to FFh value Use the MOV instruction to write to the SiBRG register.
Page 557: Operations
M16C/64A Group 24. Serial Interface SI/O3 and SI/O4 24.3 Operations 24.3.1 Basic Operations SI/Oi transmits and receives data simultaneously. The SiTRR register is not divided into a register for transmission/reception and buffer. Write transmit data to the SiTRR register while transmission/ reception is stopped.
Page 558: Lsb First Or Msb First Selection
M16C/64A Group 24. Serial Interface SI/O3 and SI/O4 24.3.3 LSB First or MSB First Selection Bit order is selected by setting the SMi5 bit in the SiC register (i = 3, 4). Figure 24.3 shows Bit Order. (1) The SMi5 bit in the SiC register is set to 0 (LSB first) CLKi TXDi RXDi...
Page 559: Internal Clock
M16C/64A Group 24. Serial Interface SI/O3 and SI/O4 24.3.4 Internal Clock When the SMi6 bit in the SiC register is 1, data is transmitted/received using the internal clock. The internal clock is selected by setting the PCLK1 bit in the PCLKR register and bits SMi1 to SMi0 in the SiC register.
Page 560: Function For Selecting Souti State After Transmission
M16C/64A Group 24. Serial Interface SI/O3 and SI/O4 24.3.5 Function for Selecting SOUTi State after Transmission The SOUTi pin state after transmission can be selected when the SMi6 bit in the SiC register is set to 1 (internal clock). If bits SM26 and SM27 in the S34C2 register are both set to 1 (last bit level retained), output from the SOUTi pin retains the last bit level after transmission.
Page 561: External Clock
M16C/64A Group 24. Serial Interface SI/O3 and SI/O4 24.3.6 External Clock When the SMi6 bit in the SiC register is 0, data is transmitted/received using the external clock. The external clock is used as a transmit/receive clock, the SOUTi output level from when the SMi3 bit in the SiC register is set to 1 (SI/Oi enabled) and SMi2 bit is set to 0 (SOUTi output enabled) to when the first data is output can be selected by the SMi7 bit in the SiC register.
Page 562: Function For Setting Souti Initial Value
M16C/64A Group 24. Serial Interface SI/O3 and SI/O4 24.3.8 Function for Setting SOUTi Initial Value When the SMi6 bit in the SiC register is 0 (external clock), the SOUTi pin output can be fixed high or low when not transmitting/receiving data. High or low can be selected by setting the SMi7 bit in the SiC register.
Page 563: Interrupt
M16C/64A Group 24. Serial Interface SI/O3 and SI/O4 24.4 Interrupt Refer to the operation example for interrupt source or interrupt request generation timing. Refer to 14.7 “Interrupt Control” for interrupt control. Table 24.5 lists Registers Associated with SI/O3 and SI/O4. Table 24.5 Registers Associated with SI/O3 and SI/O4 Address...
Page 564: Notes On Serial Interface Si/O3 And Si/O4
M16C/64A Group 24. Serial Interface SI/O3 and SI/O4 24.5 Notes on Serial Interface SI/O3 and SI/O4 24.5.1 SOUTi Pin Level When SOUTi Output Is Disabled When the SMi2 bit in the SiC register is set to 1 (SOUTi output disabled), the target pin becomes high- impedance regardless of which pin function being used.
Page 565: Introduction
M16C/64A Group 25. Multi-master I C-bus Interface 25. Multi-master I C-bus Interface 25.1 Introduction The multi-master I C-bus interface (I C interface) is a serial communication circuit based on the I C-bus data transmit/receive format, and is equipped with arbitration lost detect and clock synchronous functions. Table 25.1 lists the Multi-master I C-bus Interface Specifications, Table 25.2 lists the I C Interface...
Page 566: Multi-Master I C-Bus Interface
M16C/64A Group 25. Multi-master I C-bus Interface Table 25.2 C Interface Detection Function Item Function A function to detect a slave address match when in slave transmission/reception. If slave address match is detected, an ACK is Slave address match returned. If the slave address match is not detected, a NACK is returned, detection and no further data is transmitted/received.
Page 567 M16C/64A Group 25. Multi-master I C-bus Interface I2C0 control register 1 (S3D0) ICK1 ICK0 PEC PED WIT SIM I2C0 address register 2 (S0D2) I2C0 address register 1 (S0D1) I2C0 status register 1 (S11) I2C0 address register 0 (S0D0) C-bus Interrupt interface SCL/SDA Address comparator...
Page 568: Registers Descriptions
M16C/64A Group 25. Multi-master I C-bus Interface 25.2 Registers Descriptions Table 25.4 lists registers associated with multi-master I C-bus interface. When the CM07 bit in the CM0 register is set to 1 (sub clock is CPU clock), registers listed in Table 25.4 should not be accessed. Set them after the CM07 bit is set to 0 (main clock, PLL clock, or on-chip oscillator clock).
Page 569 M16C/64A Group 25. Multi-master I C-bus Interface 25.2.1 Peripheral Clock Select Register (PCLKR) Peripheral Clock Select Register Reset Value b6 b5 b4 Symbol Address PCLKR 0012h 0000 0011b Bit Symbol Bit Name Function Timers A and B clock select bit (clock source for timers A and 0: f2TIMAB/f2IIC PCLK0...
Page 570 M16C/64A Group 25. Multi-master I C-bus Interface 25.2.2 I2C0 Data Shift Register (S00) I2C0 Data Shift Register Symbol Address Reset Value 02B0h Function Transmit/receive data is stored. When the I C interface is a transmitter, write transmit data to the S00 register. When the I C interface is a receiver, received data can be read from the S00 register.
Page 571 M16C/64A Group 25. Multi-master I C-bus Interface 25.2.3 I2C0 Address Register i (S0Di) (i = 0 to 2) I2C0 Address Register i (i = 0 to 2) b7 b6 b5 b4 Reset Value Symbol Address S0D0 02B2h 0000 000Xb 0000 000Xb S0D1 02BAh 0000 000Xb...
Page 572 M16C/64A Group 25. Multi-master I C-bus Interface 25.2.4 I2C0 Control Register 0 (S1D0) I2C0 Control Register 0 Symbol Address Reset Value b7 b6 b5 b4 S1D0 02B3h Bit Symbol Bit Name Function b2 b1 b0 0 0 0: 8 0 0 1: 7 0 1 0: 6 Bit counter (number of 0 1 1: 5...
Page 573 M16C/64A Group 25. Multi-master I C-bus Interface • Bits AAS2 to AAS0 in the S11 register: 0 (slave address not matches) • The TOF bit in the S4D0 register: 0 (timeout not detected) ALS (Data format select bit) (b4) The ALS bit is enabled in slave mode. When the ALS bit is 0 (addressing format), the slave address match detection is performed.
Page 574 M16C/64A Group 25. Multi-master I C-bus Interface 25.2.5 I2C0 Clock Control Register (S20) I2C0 Clock Control Register Symbol Address Reset Value b7 b6 b5 b4 02B4h Bit Symbol Bit Name Function CCR0 CCR1 Refer to bits CCR4 to CCR0 (Bit Rate CCR2 Bit rate control bit Control Bit) (b4 to b0) in the next page.
Page 575 M16C/64A Group 25. Multi-master I C-bus Interface FASTMODE (SCL mode select bit) (b5) When using the fast-mode I C-bus standard (maximum 400 kbps), set the FASTMODE bit to 1 (fast- mode) and set fVIIC to 4 MHz or more. Rewrite the FASTMODE bit when the ES0 bit in the S1D0 register is 0 (disabled). ACKBIT (ACK bit) (b6) The ACK bit is enabled in master reception, slave reception, or slave address reception.
Page 576 M16C/64A Group 25. Multi-master I C-bus Interface 25.2.6 I2C0 Start/Stop Condition Control Register (S2D0) I2C0 Start/Stop Condition Control Register Symbol Address Reset Value b7 b6 b5 b4 0001 1010b S2D0 02B5h Bit Symbol Bit Name Function SSC0 SSC1 Refer to SSC4 to SSC0 (Start/Stop SSC2 Start/stop condition setting bit Condition Setting Bit) (b4 to b0) in the...
Page 577 M16C/64A Group 25. Multi-master I C-bus Interface 25.2.7 I2C0 Control Register 1 (S3D0) I2C0 Control Register 1 Symbol Address After Reset b7 b6 b5 b4 0011 0000b S3D0 02B6h Bit Symbol Bit Name Function 0: I C-bus interrupt by stop condition Stop condition detect interrupt detection is disabled enable bit...
Page 578 M16C/64A Group 25. Multi-master I C-bus Interface WIT (Data receive interrupt enable bit) (b1) The WIT bit is enabled in master reception or slave reception. The WIT bit has two functions: • Selects the I C-bus interrupt timing when data is received. (write) •...
Page 579 M16C/64A Group 25. Multi-master I C-bus Interface When setting the WIT bit to 1 in receive mode, and the ACK clock is present: C-bus interrupt is enabled at eighth clock) SCLMM clock SDAMM ACKBIT bit in the Write by a program S20 register PIN bit in the S10 register Internal WAIT flag...
Page 580 M16C/64A Group 25. Multi-master I C-bus Interface PED (SDAMM/port function switch bit) (b2) PEC (SCLMM/port function switch bit) (b3) Bits PEC and PED are enabled when the ES0 bit in the S1D0 register is 1 (I C interface enabled). When the PEC bit is set to 1 (output port), the P7_1 bit value is output from the SCLMM pin regardless of the internal SCL output signal and PD7_1 bit value.
Page 581 M16C/64A Group 25. Multi-master I C-bus Interface 25.2.8 I2C0 Control Register 2 (S4D0) I2C0 Control Register 2 Symbol Address Reset Value b7 b6 b5 b4 S4D0 02B7h Bit Symbol Bit Name Function Timeout detect function 0: Disabled enable bit 1: Enabled 0: Not detected Timeout detect flag 1: Detected...
Page 582 M16C/64A Group 25. Multi-master I C-bus Interface TOSEL (Timeout detect time select bit) (b2) Set the TOSEL bit to select a timeout detection period. The TOSEL bit is enabled when the TOE bit is 1 (timeout detect function enabled). When long time is selected, the internal counter increments fVIIC as a 16-bit counter. When short time is selected, the internal counter increments fVIIC as a 14-bit counter.
Page 583 M16C/64A Group 25. Multi-master I C-bus Interface 25.2.9 I2C0 Status Register 0 (S10) I2C0 Status Register 0 Symbol Address Reset Value b7 b6 b5 b4 0001 000Xb 02B8h Bit Symbol Bit Name Function When read, 0: Last bit = 0 1: Last bit = 1 Last receive bit When write, see Table 25.10 “Functions...
Page 584 M16C/64A Group 25. Multi-master I C-bus Interface Table 25.10 lists Functions Enabled by Writing to the S10 Register. Only set the values listed in Table 25.10. If the values listed in Table 25.10 are written to the S10 register, the 6 lower bits in the S10 register will not be changed.
Page 585 M16C/64A Group 25. Multi-master I C-bus Interface AAS (Slave address compare flag) (b2) The AAS bit function in read access is described below. See Table 25.10 “Functions Enabled by Writing to the S10 Register” for the bit function in write access. Conditions to become 0: •...
Page 586 M16C/64A Group 25. Multi-master I C-bus Interface PIN (I C-bus interface interrupt request bit) (b4) The PIN bit function in read access is described below. See Table 25.10 “Functions Enabled by Writing to the S10 Register” for the bit function in write access. Conditions to become 0: •...
Page 587 M16C/64A Group 25. Multi-master I C-bus Interface TRX (Communication mode select bit 0) (b6) Set the TRX bit to select transmit mode or receive mode. Conditions to become 0: • The TRX bit is set to 0 by a program. •...
Page 588 M16C/64A Group 25. Multi-master I C-bus Interface 25.2.10 I2C0 Status Register 1 (S11) I2C0 Status Register 1 Symbol Address Reset Value b7 b6 b5 b4 XXXX X000b 02B9h Bit Symbol Bit Name Function 0: No address matched AAS0 Slave address 0 compare flag 1: Address matched 0: No address matched AAS1...
Page 589 M16C/64A Group 25. Multi-master I C-bus Interface 25.3 Operations 25.3.1 Clock Figure 25.5 shows the I C-bus Interface Clock. PCLKR register PCLK0 = 1 f1IIC System clock select fIIC circuit C-bus system clock f2IIC Divide-by-2 Divide-by-m fVIIC PCLK0 = 0 S20 register FASTMODE = 0 Divide-by-8...
Page 590 M16C/64A Group 25. Multi-master I C-bus Interface 25.3.1.2 Bit Rate and Duty Cycle Bit rate is determined by a combination of fVIIC, the FASTMODE bit in the S20 register, and bits CCR4 to CCR0 in the S20 register. Table 25.11 lists the Bit Rate of Internal SCL Output and Duty Cycle. When the change in the internal SCL output high level is a negative value, although the low period increases the amount that the high periods decreases, the bit rate does not increase.
Page 591 M16C/64A Group 25. Multi-master I C-bus Interface 25.3.1.3 Receiving a Slave Address in Wait Mode and Stop Mode When the CM02 bit in the CM0 register is set to 0 (peripheral clock f1 does not stop in wait mode) and transition is made to wait mode, the I C interface can receive the slave address even in wait mode.
Page 592 M16C/64A Group 25. Multi-master I C-bus Interface 25.3.2 Generating a Start Condition Follow the procedure below when the ES0 bit in the S1D0 register is 1 (I C interface enabled) and the BB bit in the S10 register is set to 0 (bus free). Figure 25.6 shows the Procedure to Generate a Start Condition.
Page 593 M16C/64A Group 25. Multi-master I C-bus Interface The start condition generation timing depends on the modes - standard clock mode or fast-mode. Figure 25.7 shows the Start Condition Generation Timing. Table 25.13 lists the Setup/Hold Time for Generating a Start/Stop Condition. Write signal to the S00 register SCLMM Setup...
Page 594 M16C/64A Group 25. Multi-master I C-bus Interface 25.3.3 Generating a Stop Condition Use the following procedure when the ES0 bit in the S1D0 register is 1 (I C interface enabled). (1) Write C0h to the S10 register. The I C interface enters the stop condition standby state and the SDAMM pin is driven low. (2) Write dummy data to the S00 register.
Page 595 M16C/64A Group 25. Multi-master I C-bus Interface 25.3.4 Generating a Restart Condition Use the following procedure to generate a restart condition when 1-byte data is transmitted/received. (1) Write E0h to the S10 register. (Start condition standby state. The SDAMM pin released.) (2) Wait until the SDAMM pin level becomes high.
Page 596 M16C/64A Group 25. Multi-master I C-bus Interface 25.3.5 Start Condition Overlap Protect The I C interface generates a start condition by setting registers S10 and S00 by a program. The bus system must be free before setting these registers. Check whether the bus is free with the BB bit in the S10 register by a program before setting the registers.
Page 597 M16C/64A Group 25. Multi-master I C-bus Interface The start condition overlap protect is enabled from the falling edge of SDAMM (start condition) to the completion of the slave address receive. If data is written to registers S10 and S00 during that period, the above operation is performed.
Page 598 M16C/64A Group 25. Multi-master I C-bus Interface 25.3.6 Arbitration Lost When all of the conditions below are met, the SDAMM pin signal level becomes low by an external device and the I C interface determines that it has lost arbitration. (a) Transmit/receive (one of the following) •...
Page 599 M16C/64A Group 25. Multi-master I C-bus Interface When arbitration lost is detected: • The AL bit in the S10 register becomes 1 (arbitration lost detected) • Internal SDA output becomes high. (SDAMM released) • The I C interface enters the slave receive mode The TRX bit in the S10 register is 0 (receive mode).
Page 600 M16C/64A Group 25. Multi-master I C-bus Interface 25.3.7 Detecting Start/Stop Conditions Figure 25.13 shows Start Condition Detection, Figure 25.14 shows Stop Condition Detection, and Table 25.14 lists Conditions to Detect Start/Stop Condition. A start/stop condition can be detected only when the start/stop condition detect parameters are selected by setting bits SSC4 to SSC0 in the S2D0 register, and the signals input to pins SCLMM and SDAMM meet all three conditions (SCLMM release time, setup time, and hold time) listed in Table 25.14.
Page 601 M16C/64A Group 25. Multi-master I C-bus Interface Table 25.14 Conditions to Detect Start/Stop Condition Standard Clock Mode Fast-Mode SCLMM open time SSC value + 1 cycle 4 cycles SSC value 1 cycle --------------------------- - Setup time 2 cycles SSC value Hold time 2 cycles --------------------------- - cycles...
Page 602 M16C/64A Group 25. Multi-master I C-bus Interface 25.3.8 Operation after Transmitting/Receiving a Slave Address or Data After a slave address or 1-byte data has been transmitted/received, the PIN bit in the S10 register becomes 0 (interrupt requested) at the falling edge of the ACK clock. The IR bit in the IICIC register becomes 1 (interrupt requested) at the same time.
Page 603 M16C/64A Group 25. Multi-master I C-bus Interface 25.3.9 Timeout Detection When the SCL clock is stopped during transmission/reception, each device stops operating, keeping the communication state. To avoid this, the I C interface incorporates a function to detect timeouts and generate an I C-bus interrupt request when the SCLMM pin is driven high for more than the selected timeout detection period during transmission/reception.
Page 604 M16C/64A Group 25. Multi-master I C-bus Interface 25.3.10 Data Transmit/Receive Examples The data transmit/receive examples are described in this section. The conditions for the examples are as follows: • Slave address: 7 bits • Data: 8 bits • ACK clock •...
Page 605 M16C/64A Group 25. Multi-master I C-bus Interface 25.3.10.2 Master Transmission Master transmission is described in this section. The initial settings described in 25.3.10.1 “Initial Settings” are assumed to be completed. Figure 21.17 shows master transmission operation. The following programs (A) to (C) are executed at (A) to (C) in Figure 25.17, respectively. S: Start condition A: ACK R: Read...
Page 606 M16C/64A Group 25. Multi-master I C-bus Interface 25.3.10.3 Master Reception Master reception is described in this section. The initial settings described in 25.3.10.1 “Initial Settings” are assumed to be completed. Figure 25.18 shows the operation example of master reception. The following programs (A) to (D) are executed at (A) to (D) in Figure 25.18, respectively. S: Start condition A: ACK R: Read...
Page 607 M16C/64A Group 25. Multi-master I C-bus Interface 25.3.10.4 Slave Reception The slave reception is described in this section. The initial settings described in 225.3.10.1 “Initial Settings” are assumed to be completed. Figure 25.19 shows the example of slave reception. The following programs (A) to (C) are executed at (A) to (C) in Figure 25.19, respectively.
Page 608 M16C/64A Group 25. Multi-master I C-bus Interface 25.3.10.5 Slave Transmission Slave transmission is described in this section. The initial settings described in 25.3.10.1 “Initial Settings” are assumed to be completed. Figure 25.20 shows the example of slave transmission. The following programs (A) to (B) are executed at (A) and (B) in Figure 25.20, respectively. When arbitration lost is detected, the TRX bit becomes 0 (receive mode) even when the bit after the slave address is 1 (read).
Page 609 M16C/64A Group 25. Multi-master I C-bus Interface 25.4 Interrupts The I C interface generates interrupt requests. Figure 25.21 shows I C Interface Interrupts, and Table 25.16 lists I C-bus Interrupts. C-bus Interrupt ACKCLK bit in the S20 register Falling edge of the last bit clock (Data transmit/receive of transmit/receive data detected completed)
Page 610 M16C/64A Group 25. Multi-master I C-bus Interface Table 25.16 C-bus Interrupts Associated Bits (Register) Interrupt Interrupt Interrupt Source Control Interrupt Interrupt Register enabled request Completion of data transmit/receive When the ACKCLK bit in the S20 register is 0: Detection of the falling edge of the last clock of transmit/receive data through the SCLMM pin —...
Page 611 M16C/64A Group 25. Multi-master I C-bus Interface Table 25.17 Registers Associated with I C Interface Interrupts Address Register Symbol Reset Value I2C-bus Interface Interrupt Control 007Bh IICIC XXXX X000b Register 007Ch SCL/SDA Interrupt Control Register SCLDAIC XXXX X000b 0206h Interrupt Source Select Register 2 IFSR2A When using the I C-bus interface interrupt, set the IFSR22 bit in the IFSR2A register to 1 (I...
Page 612: Notes On Multi-Master I C-Bus Interface
M16C/64A Group 25. Multi-master I C-bus Interface 25.5 Notes on Multi-master I C-bus Interface 25.5.1 Limitation on CPU Clock When the CM07 bit in the CM0 register is 1 (CPU clock is a sub clock), do not access the registers listed in Table 25.4 “Registers”.
Page 613: Generating Stop Condition
M16C/64A Group 25. Multi-master I C-bus Interface 25.5.4 Generating Stop Condition (Technical update number: TN-16C-A176A/E) In the multi-master I C-bus interface, when the slave device and/or other master devices drive the SCLMM line low, no normal stop condition is generated. This is because the SDAMM line is released while the SCLMM line is still driven low.
Page 614 M16C/64A Group 25. Multi-master I C-bus Interface Generate a stop condition Save the flag register on the stack and disable interrupts Change P7_0 pin (SDAMM) to forcibly output low Wait for t SU;DAT Change P7_1 pin (SCLMM) to forcibly output high (Hi-Z) P7_1 = 1 ? (SCLMM is line high?) Set an interrupt request source as rising edge of the SCLMM...
Page 615 M16C/64A Group 26. Consumer Electronics Control (CEC) Function 26. Consumer Electronics Control (CEC) Function 26.1 Introduction The CEC function indicates circuitry which supports the transmission and reception of CEC signals standardized by the High-Definition Multimedia Interface (HDMI). Table 26.1 and Table 26.2 list the CEC Function Specifications, Figure 26.1 shows the CEC Function Block Diagram and Table 26.3 lists the I/O Pin.
Page 616 M16C/64A Group 26. Consumer Electronics Control (CEC) Function Table 26.2 CEC Function Specifications (2/2) Item Specification Digital filter enabled/disabled Transmission stop selected Transmission stop by receiving ACK or NACK can be selected. Arbitration lost detection conditions One of the following conditions can be selected: •...
Page 617 M16C/64A Group 26. Consumer Electronics Control (CEC) Function CCLK1 to CCLK0 Clock control Supply to CEC blocks circuit (32.768 kHz) Timer A underflow CTNACK, CTACKEN CCTB1 CCTBE PCR4 CTXDEN Transmission CTFLG CTD8FLG circuit Detect transmission of 8 bits of data CRACK CCRBAO ACK output...
Page 618 M16C/64A Group 26. Consumer Electronics Control (CEC) Function 26.2 Registers The CEC function's bits and registers are synchronized with the count source. Register values change immediately after being rewritten by a program, while the internal circuit starts operating from the next count source timing.
Page 619 M16C/64A Group 26. Consumer Electronics Control (CEC) Function 26.2.2 CEC Function Control Register 2 (CECC2) CEC Function Control Register 2 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address Reset Value CECC2 0351h Bit Symbol Bit Name Function 0: Detects falling edge acceptable Receive edge detection range CRRNG...
Page 620 M16C/64A Group 26. Consumer Electronics Control (CEC) Function Table 26.5 ACK Output When Inserted by Hardware Destination Address ACK Output Address selected by the CRADRI1 or CRADRI2 register Received Destination address (own address) Matches the received Destination address Direct (0000b to 1110b) Does not match the received Destination address NACK 1111b (matches the received Destination address)
Page 621 M16C/64A Group 26. Consumer Electronics Control (CEC) Function 26.2.3 CEC Function Control Register 3 (CECC3) CEC Function Control Register 3 b7 b6 b5 b4 b3 b2 b1 b0 Address Reset Value Symbol XXXX 0000b CECC3 0352h Bit Symbol Bit Name Function 0: Disabled CTXDEN...
Page 622 M16C/64A Group 26. Consumer Electronics Control (CEC) Function CEOMI (EOM disable bit) (b3) Set the CEOMI bit to select whether to continue or stop the operation when the EOM bit is 1. Table 26.6 lists Operation When the EOM Bit is 1. Do not write to the CEOMI bit while transmitting/receiving. When the CEOMI bit is 1 (EOM disabled), data transmission continues even after the EOM bit is set to 1 and transmitted.
Page 623 M16C/64A Group 26. Consumer Electronics Control (CEC) Function 26.2.4 CEC Function Control Register 4 (CECC4) CEC Function Control Register 4 b7 b6 b5 b4 b3 b2 b1 b0 Address Reset Value Symbol CECC4 0353h Bit Symbol Bit Name Function b2 b1 b0 CRISE0 0: Standard value 1: Standard value - 30 μ...
Page 624 M16C/64A Group 26. Consumer Electronics Control (CEC) Function CFALL1-CFALL0 (Falling timing select bit) (b5-b4) The falling timing of the signal in transmission is specified. Do not write to bits CFALL1 to CFALL0 while transmitting/receiving. Table 26.7 Falling Timing of Signal in Transmission Falling Timing Bits CFALL1 to CFALL0 Start bit...
Page 625 M16C/64A Group 26. Consumer Electronics Control (CEC) Function 26.2.5 CEC Flag Register (CECFLG) CEC Flag Register b7 b6 b5 b4 b3 b2 b1 b0 Address Reset Value Symbol CECFLG 0354h Bit Symbol Bit Name Function 0: Waiting CRFLG Receive status flag 1: Receiving 0: Waiting CTFLG...
Page 626 M16C/64A Group 26. Consumer Electronics Control (CEC) Function 26.2.6 CEC Interrupt Source Select Register (CISEL) CEC Interrupt Source Select Register b7 b6 b5 b4 b3 b2 b1 b0 Address Reset Value Symbol CISEL 0355h Bit Symbol Bit Name Function 8th bit receive interrupt 0: Disabled CRISEL0 enable bit...
Page 627 M16C/64A Group 26. Consumer Electronics Control (CEC) Function 26.2.7 CEC Transmit Buffer Register 1 (CCTB1) CEC Transmit Buffer Register 1 Symbol Address Reset Value CCTB1 0356h Function Sets the transmit data Rewrite the CCTB1 register when the CTXDEN bit in the CECC3 register is 0 (transmit disabled), or the CTXDEN bit is 1 and the CTD8FLG in the CECFLG register is 1 (while bits EOM and ACK are being transmitted after the eighth bit has been transmitted).
Page 628 M16C/64A Group 26. Consumer Electronics Control (CEC) Function 26.2.9 CEC Receive Buffer Register 1 (CCRB1) CEC Receive Buffer Register 1 Symbol Address Reset Value CCRB1 0358h Function Reads the receive data. Read the CCRB1 register after receiving the eighth bit (the CRD8FLG bit in the CECFLG register changes from 0 to 1).
Page 629 M16C/64A Group 26. Consumer Electronics Control (CEC) Function 26.2.11 CEC Receive Follower Address Set Register 1 (CRADRI1), CEC Receive Follower Address Set Register 2 (CRADRI2) CEC Receive Follower Address Set Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address Reset Value...
Page 630 M16C/64A Group 26. Consumer Electronics Control (CEC) Function 26.2.12 Port Control Register (PCR) Port Control Register b6 b5 b4 Symbol Address Reset Value 0366h 0000 0XX0b Bit Symbol Bit Name Function Operation performed when the P1 register is read 0 : When the port is set to input, the input levels of pins P1_0 to P1_7 are read.
Page 631 M16C/64A Group 26. Consumer Electronics Control (CEC) Function 26.3 Operations 26.3.1 Standard Value and I/O Timing CEC transmission/reception is based on the count source cycle. When outputting, an output waveform is based on the count source cycle which is closest to the CEC standard value.
Page 632 M16C/64A Group 26. Consumer Electronics Control (CEC) Function 26.3.4 Digital Filter Input to the CEC pin goes into the internal circuit in synchronization with the count source. If the same level signal is input to the CEC pin twice in a row that level is transferred to the internal circuit, when the CFIL bit in the CECC2 register is 1 (digital filter enable).
Page 633 M16C/64A Group 26. Consumer Electronics Control (CEC) Function 26.3.5 Reception 26.3.5.1 Start Bit Detection The detect timing of the start bit and data bit is selected by setting the CRRNG bit in the CEC2 register. Select the start bit acceptable range by setting the CSTRRNG bit in the CECC2 register. Figure 26.5 shows Start Bit Acceptable Range.
Page 634 M16C/64A Group 26. Consumer Electronics Control (CEC) Function 26.3.5.2 Data Bit Detection The detect timing of the start bit and data bit (other than the start bit) is selected by setting the CRRNG bit in the CECC2 register. Select the data bit acceptable range by setting the CDATRNG bit in the CECC2 register.
Page 635 M16C/64A Group 26. Consumer Electronics Control (CEC) Function Both edges are detected Acceptable range Acceptable range When the CDATRNG bit is 0: ±200 µs ±350 µs When the CDATRNG bit is 1: ±300 µs ±500 µs CEC input (input data: 0) 0 ms 1.5 ms 2.4 ms...
Page 636 M16C/64A Group 26. Consumer Electronics Control (CEC) Function When the CABTWEN bit is 0: Low pulse is immediately output regardless of the CEC signal state. Receive error occurs 3.6 ms 3 to 4 cycles of the count source When the CABTWEN bit is 1: Low pulse is output at the rising edge of the CEC signal.
Page 637 M16C/64A Group 26. Consumer Electronics Control (CEC) Function (1) Low pulse is output automatically when a reception error occurs While the CRXDEN bit is 0 (receive disabled), by setting the CABTEN bit to 1 (error low pulse output enabled) followed by CRXDEN bit to 1 (receive enabled), an error low pulse is output for a receive error automatically.
Page 638 M16C/64A Group 26. Consumer Electronics Control (CEC) Function 26.3.5.4 ACK Bit Output The output value of the tenth bit (ACK bit) can be selected. When the CRACK bit in the CECC2 register is 0 (inserted by program), the value of the CCRBAO bit in the CCRB2 register is output as ACK data.
Page 639 M16C/64A Group 26. Consumer Electronics Control (CEC) Function 26.3.5.5 Reception Examples Figure 26.10 shows a Reception Example and Figure 26.11 shows a Reception Example (Change from Error Low Pulse Output Disabled to Enabled When an Error Occurs). When a receive error occurs, the CRERRFLG bit in the CECFLG register becomes 1 (receive error). If a reception ends due to the error during reception, set the CRXDEN bit in the CECC3 register to 0 (receive disabled).
Page 640 M16C/64A Group 26. Consumer Electronics Control (CEC) Function Header block Error low pulse Set to 0 by a program Receive error occurs CRXDEN bit CABTEN bit CRFLG bit Become 0 in synchronization with CRSTFLG bit the count source Change in synchronization with the count source Become 0 in synchronization with...
Page 641 M16C/64A Group 26. Consumer Electronics Control (CEC) Function 26.3.6 Transmission 26.3.6.1 Transmit Signal Timing Select Rising or falling timing of the transmit signal can be selected. The rising timing of the transmit signal is selected by bits CRISE2 to CRISE0 in the CECC4 register. Figure 26.12 shows Rising Timing of Transmit Signal.
Page 642 M16C/64A Group 26. Consumer Electronics Control (CEC) Function 26.3.6.2 Arbitration Lost Detection When data is transmitted, an arbitration lost is detected in the following cases: • The CEC output changes from Hi-Z to low by the external source. • When changing the CEC pin from low output to Hi-Z, the pin level remains low even though it is outside the tolerated range.
Page 643 M16C/64A Group 26. Consumer Electronics Control (CEC) Function Header block Data block Set to 0 by Set to 0 by a program a program CTXDEN bit Transmission starts at the rising edge of the count source CTFLG bit CTD8FLG bit Set to 0 by acceptance of an interrupt or by a program IR bit in the...
Page 644 M16C/64A Group 26. Consumer Electronics Control (CEC) Function Header block ..NACK Set to 1 by a program Set to 0 by a program CTXDEN bit Transmission starts at the rising edge of the count source CTFLG bit CTD8FLG bit Becomes 0 in synchronization with...
Page 645 M16C/64A Group 26. Consumer Electronics Control (CEC) Function Arbitration lost occurs H0 EOM ACK Set to 0 by a Set to 1 by a program program CTXDEN bit Transmission starts at the rising edge of the count source CTFLG bit Set to 0 in synchronization CTABTFLG bit...
Page 646 M16C/64A Group 26. Consumer Electronics Control (CEC) Function 26.4 Interrupts The CEC function has CEC1 interrupt and CEC2 interrupt. Table 26.9 and Table 26.10 list CEC Interrupt Sources. These sources generate a CEC1 interrupt or CEC2 interrupt request. When the CRISELM bit in the CISEL register is 1, the eighth/tenth bit receive interrupt request is generated if the received Destination address is either one of the following case: •...
Page 647 M16C/64A Group 26. Consumer Electronics Control (CEC) Function CTISEL0 CEC1 interrupt CTD8FLG (IR bit in the CEC1IC register) CTISEL1 CTISEL2 CTABTFLG CTNACKFLG Broadcast Destination address CRISELM CRISEL0 CEC2 interrupt (IR bit in the CEC2IC register) CRD8FLG CRISEL1 CRERRFLG CRISEL2 CRISELS CRSTFLG CRISELS, CTISEL2, CTISEL1, CTISEL0, CRISELM, CRISEL2, CRISEL1, CRISEL0: Bits in the CISEL register CRSTFLG, CTD8FLG, CRD8FLG, CTNACKFLG, CTABTFLG, CRERRFLG: Bits in the CECFLG register...
Page 648: Notes On Cec
M16C/64A Group 26. Consumer Electronics Control (CEC) Function 26.5 Notes on CEC 26.5.1 Registers and Bit Operation The registers and bits of the CEC function are synchronized with the count source. Therefore, the internal circuit starts to operate from the next count source timing, while the values of the register are changed immediately after rewriting the register.
Page 649 M16C/64A Group 27. A/D Converter 27. A/D Converter 27.1 Introduction The A/D converter consists of one 10-bit successive approximation A/D converter. Table 27.1 lists the A/D Converter Specifications and Figure 27.1 shows an A/D Converter Block Diagram. Table 27.1 A/D Converter Specifications Item Specification A/D conversion...
Page 650 M16C/64A Group 27. A/D Converter VREF Analog circuit AVSS ADSTBY ADCON1 register Successive conversion register ADCON0 register AD0 register AD1 register AD2 register Decoder AD3 register for register AD4 register AD5 register AD6 register AD7 register Data bus ADCON2 register PM00 PM01 Vref...
Page 651 M16C/64A Group 27. A/D Converter Table 27.2 I/O Ports Pin Name Function AN0 to AN7 Input Analog input ANEX0, ANEX1 Input Analog input AN0_0 to AN0_7 Input Analog input AN2_0 to AN2_7 Input Analog input ADTRG Input Trigger input Note: Set the direction bit of the ports sharing a port to 0 (input mode).
Page 652 M16C/64A Group 27. A/D Converter 27.2.1 Port Control Register (PCR) Port Control Register b6 b5 b4 Symbol Address Reset Value 0366h 0000 0XX0b Bit Symbol Bit Name Function Operation performed when the P1 register is read 0 : When the port is set to input, the input levels of pins P1_0 to P1_7 are read.
Page 653 M16C/64A Group 27. A/D Converter 27.2.2 Open-Circuit Detection Assist Function Register (AINRST) Open-Circuit Detection Assist Function Register Symbol Address Reset Value b7 b6 b5 b4 AINRST XX00 XXXXb 03A2h Bit Symbol Bit Name Function — No register bits. If necessary, set to 0. The read value is undefined. —...
Page 654 M16C/64A Group 27. A/D Converter 27.2.3 A/D Register i (ADi) (i = 0 to 7) A/D Register i (i = 0 to 7) Symbol Address Reset Value (b15) (b8) 03C1h to 03C0h 0000 00XX XXXX XXXXb 03C3h to 03C2h 0000 00XX XXXX XXXXb 03C5h to 03C4h 0000 00XX XXXX XXXXb 03C7h to 03C6h...
Page 655 M16C/64A Group 27. A/D Converter 27.2.4 A/D Control Register 2 (ADCON2) A/D Control Register 2 b6 b5 b4 Symbol Address Reset Value ADCON2 0000 X00Xb 03D4h Bit Symbol Bit Name Function — — No register bit. If necessary, set to 0. The read value is undefined. (b0) b2 b1 ADGSEL0...
Page 656 M16C/64A Group 27. A/D Converter 27.2.5 A/D Control Register 0 (ADCON0) A/D Control Register 0 b7 b6 b5 b4 Symbol Address Reset Value ADCON0 0000 0XXXb 03D6h Bit Symbol Bit Name Function In one-shot mode or repeat mode 0 : AN0 1 : AN1 0 : AN2 Analog input pin select bit...
Page 657 M16C/64A Group 27. A/D Converter CKS0 (Frequency select bit 0) (b7) φ AD frequency is selected by a combination of the CKS0 bit in the ADCON0 register, the CKS1 bit in the ADCON1 register, and the CKS2 bit in the ADCON2 register. Table 27.6 lists φ AD Frequency. φ...
Page 658 M16C/64A Group 27. A/D Converter 27.2.6 A/D Control Register 1 (ADCON1) A/D Control Register 1 b7 b6 b5 b4 Symbol Address After Reset ADCON1 03D7h 0000 X000b Bit Symbol Bit Name Function In single sweep mode or repeat sweep mode 0 SCAN0 0: AN0 to AN1 (2 pins) 1: AN0 to AN3 (4 pins)
Page 659 M16C/64A Group 27. A/D Converter 27.3 Operations 27.3.1 A/D Conversion Cycle A/D conversion cycle is based on fAD and φ AD. Divide fAD so φ AD conforms the standard frequency. Figure 27.2 shows fAD and φ AD. CKS1 Select A/D conversion speed CKS2 φAD CKS0...
Page 660 M16C/64A Group 27. A/D Converter Table 27.7 lists Cycles of A/D Conversion Item. A/D conversion time is described below. Start processing time depends on which φ AD is selected. A/D conversion starts after the start processing time elapses by setting the ADST bit in the ADCON0 register to 1 (A/D conversion start).
Page 661 M16C/64A Group 27. A/D Converter 27.3.2 A/D Conversion Start Conditions An A/D conversion start trigger has a software trigger and an external trigger. Figure 27.4 shows A/D Conversion Start Trigger. ADST A/D conversion start trigger ADTRG pin ADST, TRG: Bits in the ADCON0 register Figure 27.4 A/D Conversion Start Trigger 27.3.2.1...
Page 662 M16C/64A Group 27. A/D Converter 27.3.3 A/D Conversion Result When reading the ADi register before A/D conversion is completed, the undefined value is read. Read the ADi register after completing A/D conversion. Use the following procedure to detect the completion of A/D conversion.
Page 663 M16C/64A Group 27. A/D Converter Charge control signal Charge External circuit example Discharge AINRST0 = 1 control signal Analog input Sampling capacitor Open-circuit ANi: ANi (i = 0 to 7), ANEXi, AN0-i, AN2-i AINRST0: Bit in the AINRST register Figure 27.6 A/D Open-Circuit Detection Example on AVCC (Preconversion Charge) Measuring Condition (common) VCC1 = 5.12 V...
Page 664 M16C/64A Group 27. A/D Converter Charge control signal Discharge AINRST1 = 1 control signal External circuit example Analog input Discharge Sampling capacitor Open-circuit ANi: ANi (i = 0 to 7), ANEXi, AN0-i, AN2-i AINRST1: Bit in the AINRST register Figure 27.8 A/D Open-Circuit Detection Example on AVSS (Preconversion discharge) Measuring Condition (common) VCC1 = 5.12 V...
Page 665 M16C/64A Group 27. A/D Converter 27.4 Operational Modes 27.4.1 One-Shot Mode In one-shot mode, the analog voltage applied to a selected pin is converted to a digital code once. Table 27.8 lists One-Shot Mode Specifications. Table 27.8 One-Shot Mode Specifications Item Specification Bits CH2 to CH0 in the ADCON0 register and bits ADGSEL1 to ADGSEL0...
Page 666 M16C/64A Group 27. A/D Converter Table 27.9 Registers and Settings in One-Shot Mode Register Setting Set to 1 ( INT6 input disabled) when using the AN2_4 pin for analog PCR5 input. Set to 1 ( INT7 input disabled) when using the AN2_5 pin for analog PCR6 input.
Page 667 M16C/64A Group 27. A/D Converter 27.4.2 Repeat Mode In repeat mode, the analog voltage applied to a selected pin is repeatedly converted to a digital code. Table 27.10 lists Repeat Mode Specifications. Table 27.10 Repeat Mode Specifications Item Specification Bits CH2 to CH0 in the ADCON0 register and bits ADGSEL1 to ADGSEL0 in the ADCON2 register, or bits ADEX1 to ADEX0 in the ADCON1 register Function are used to select a pin.
Page 668 M16C/64A Group 27. A/D Converter Table 27.11 Registers and Settings in Repeat Mode Register Setting Set to 1 ( INT6 input disabled) when using the AN2_4 pin for PCR5 analog input. Set to 1 ( INT7 input disabled) when using the AN2_5 pin for PCR6 analog input.
Page 669 M16C/64A Group 27. A/D Converter 27.4.3 Single Sweep Mode In single sweep mode, the analog voltage applied to selected pins is converted one-by-one to a digital code. Table 27.12 lists the Single Sweep Mode Specifications. Table 27.12 Single Sweep Mode Specifications Item Specification Bits SCAN1 to SCAN0 in the ADCON1 register and bits ADGSEL1 to...
Page 670 M16C/64A Group 27. A/D Converter Table 27.13 Registers and Settings in Single Sweep Mode Register Setting Set to 1 ( INT6 input disabled) when using the AN2_4 pin for PCR5 analog input. Set to 1 ( INT7 input disabled) when using the AN2_5 pin for PCR6 analog input.
Page 671 M16C/64A Group 27. A/D Converter 27.4.4 Repeat Sweep Mode 0 In repeat sweep mode 0, the analog voltage applied to selected pins is repeatedly converted to a digital code. Table 27.14 lists the Repeat Sweep Mode 0 Specifications. Table 27.14 Repeat Sweep Mode 0 Specifications Item Specification...
Page 672 M16C/64A Group 27. A/D Converter Table 27.15 Registers and Settings in Repeat Sweep Mode 0 Register Setting Set to 1 ( INT6 input disabled) when using the AN2_4 pin for PCR5 analog input. Set to 1 ( INT7 input disabled) when using the AN2_5 pin for PCR6 analog input.
Page 673 M16C/64A Group 27. A/D Converter 27.4.5 Repeat Sweep Mode 1 In repeat sweep mode 1, the analog voltage applied to eight selected pins, including some prioritized pins, is repeatedly converted to a digital code. Table 27.16 lists the Repeat Sweep Mode 1 Specifications.
Page 674 M16C/64A Group 27. A/D Converter Table 27.17 Registers and Settings in Repeat Sweep Mode 1 Register Setting Set to 1 ( INT6 input disabled) when using the AN2_4 pin for PCR5 analog input. Set to 1 ( INT7 input disabled) when using the AN2_5 pin for PCR6 analog input.
Page 675 M16C/64A Group 27. A/D Converter When ANi_0 is prioritized (single pin) Time ANi_0 ANi_1 ANi_2 ANi_3 ANi_4 ANi_5 ANi_6 ANi_7 When ANi_0 and ANi_1 are prioritized (2 pins) ANi_0 ANi_1 ANi_2 ANi_3 ANi_4 ANi_5 ANi_6 ANi_7 When ANi_0 to ANi_2 are prioritized (3 pins) ANi_0 ANi_1 ANi_2...
Page 676 M16C/64A Group 27. A/D Converter 27.5 External Sensor To perform A/D conversion accurately, charging the internal capacitor C shown in Figure 27.16 must be completed within a specified period of time. T: Specified period of time (sampling time) R0: Output impedance of sensor equivalent circuit R: Internal resistance of the MCU X: Precision (error) of the A/D converter Y: Resolution of the A/D converter be Y (Y is 1024)
Page 677 M16C/64A Group 27. A/D Converter 27.6 Interrupt Refer to the operation examples for timing of generating interrupt requests. Also, refer to 14.7 “Interrupt Control” for details. Table 27.18 lists Registers Associated with A/D Converter Interrupt. Table 27.18 Registers Associated with A/D Converter Interrupt Address Register Symbol...
Page 678: Notes On A/D Converter
M16C/64A Group 27. A/D Converter 27.7 Notes on A/D Converter 27.7.1 Analog Input Voltage Set the analog input voltage as follows: analog input voltage (AN_0 to AN_7, ANEX0, and ANEX1) ≤ VCC1 analog input voltage (AN0_0 to AN0_7 and AN2_7 to AN2_7) ≤ VCC2 27.7.2 Analog Input Pin Do not use any pin from AN4 to AN7 as analog input pin if any pin from KI0 to KI3 is used as a key input...
Page 679: State When Forcibly Terminated
M16C/64A Group 27. A/D Converter 27.7.7 State When Forcibly Terminated If A/D conversion in progress is halted by setting the ADST bit in the ADCON0 register to 0 (A/D conversion stopped), the conversion result is undefined. In addition, the unconverted ADi register (i = 0 to 7) may also become undefined.
Page 680 M16C/64A Group 27. A/D Converter 27.7.10 Repeat Mode, Repeat Sweep Mode 0, and Repeat Sweep Mode 1 In repeat mode, repeat sweep mode 0, and repeat sweep mode 1, when reading the ADi register (i = 0 to 7) during the period when the ADi register value is rewritten, an undefined value may be read. Read the ADi register several times to determine whether the read value is valid.
Page 681 M16C/64A Group 28. D/A Converter 28. D/A Converter 28.1 Introduction The D/A converter is an 8-bit, R-2R type converter. There are two independent D/A converters. Table 28.1 lists the D/A Converter Specifications and Figure 28.1 shows the D/A Converter Block Diagram.
Page 682 M16C/64A Group 28. D/A Converter 28.2 Registers Table 28.3 Registers Address Register Symbol Reset Value 03D8h D/A0 Register 03DAh D/A1 Register 03DCh D/A Control Register DACON 28.2.1 D/Ai Register (DAi) (i = 0, 1) D/Ai Register (i = 0, 1) Symbol Address Reset Value...
Page 683 M16C/64A Group 28. D/A Converter 28.3 Operations D/A conversion is performed by writing a value to the DAi register (i = 0, 1). Output analog voltage (V) is determined by the value n (n = decimal) set in the DAi register. V = VREF ×...
Page 684: Notes On D/A Converter
M16C/64A Group 28. D/A Converter 28.4 Notes on D/A Converter 28.4.1 When Not Using the D/A Converter When not using the D/A converter, set the DAiE bit (i = 0, 1) in the DACON register to 0 (output disabled) and the DAi register to 00h in order to minimize unnecessary current consumption and prevent current flow to the R-2R resistor.
Page 685 M16C/64A Group 29. CRC Calculator 29. CRC Calculator 29.1 Introduction The cyclic redundancy check (CRC) calculator detects errors in data blocks. This CRC calculator is enhanced by an additional feature, the CRC snoop, in order to monitor reads from and writes to a certain SFR address, and perform CRC calculations automatically on the data read from and data written to the aforementioned SFR address.
Page 686 M16C/64A Group 29. CRC Calculator 29.2 Registers Table 29.2 Registers Address Register Symbol Reset Value 03B4h XXXX XXXXb SFR Snoop Address Register CRCSAR 03B5h 00XX XXXXb 03B6h CRC Mode Register CRCMR 0XXX XXX0b 03BCh CRC Data Register CRCD 03BDh 03BEh CRC Input Register CRCIN 29.2.1...
Page 687 M16C/64A Group 29. CRC Calculator 29.2.2 CRC Mode Register (CRCMR) CRC Mode Register b7 b6 b5 b4 Symbol Address Reset Value CRCMR 03B6h 0XXX XXX0b Bit Symbol Bit Name Function CRC polynomial select 0: X + 1 (CRC-CCITT) CRCPS 1: X + 1 (CRC-16) —...
Page 688 M16C/64A Group 29. CRC Calculator 29.3 Operations 29.3.1 Basic Operation The CRC (Cyclic Redundancy Check) calculator detects errors in data blocks. The MCU uses two generator polynomials to generate CRC: CRC-CCITT (X + 1) and CRC-16 (X + 1). The CRC code is 16-bit code generated for a given length of a data block in 8-bit units. After setting the default value in the CRCD register, the CRC code is stored in the CRCD register every time 1-byte of data is written to the CRCIN register.
Page 689 M16C/64A Group 29. CRC Calculator When using CRC-CCITT with LSB first: Generator polynomial: X + 1 (1 0001 0000 0010 0001b) Setting procedures (1) Write 0000h (initial value) to the CRCD register. CRCD register 0000h (2) Write 01h to the CRCIN register. CRCIN register After two cycles, the result is stored in the CRCD register.
Page 690 M16C/64A Group 30. Flash Memory 30. Flash Memory 30.1 Introduction This product uses flash memory as ROM. In this chapter, flash memory refers to the flash memory inside the MCU. In this product, the flash memory can perform in three rewrite modes: CPU rewrite mode, standard serial I/O mode, and parallel I/O mode.
Page 691 M16C/64A Group 30. Flash Memory Table 30.2 Flash Memory Rewrite Modes Overview Flash Memory CPU Rewrite Mode Standard Serial I/O Mode Parallel I/O Mode Rewrite Mode The flash memory is rewritten The flash memory is rewritten when the CPU executes software using a dedicated serial commands.
Page 692 M16C/64A Group 30. Flash Memory 30.2 Memory Map The flash memory is used as ROM in this product. The flash memory is comprised of program ROM 1, program ROM 2, and data flash. Figure 30.1 shows the Flash Memory Block Diagram. The flash memory is divided into several blocks, each of which can be protected (locked) from being programmed or erased.
Page 693 M16C/64A Group 30. Flash Memory 00E000h Block A: 4 KB 00EFFFh Data flash 00F000h Block B: 4 KB 00FFFFh 010000h Program ROM 2: 16 KB 013FFFh 080000h Block 7: 64 KB 08FFFFh 090000h Block 6: 64 KB 09FFFFh 0A0000h Block 5: 64 KB 0AFFFFh 0B0000h Block 4: 64 KB...
Page 694 M16C/64A Group 30. Flash Memory 30.3 Registers Table 30.4 Registers Address Register Symbol Reset Value 0000 0001b (Other than user boot mode) 0220h Flash Memory Control Register 0 FMR0 0010 0001b (User boot mode) 0221h Flash Memory Control Register 1 FMR1 00X0 XX0Xb 0222h...
Page 695 M16C/64A Group 30. Flash Memory FMR01 (CPU rewrite mode select bit) (b1) Commands can be accepted by setting the FMR01 bit to 1 (CPU rewrite mode enabled). To set the FMR01 bit to 1, write 0 and then 1 in succession. Do not generate any interrupts or DMA transfers between setting 0 and 1.
Page 696 M16C/64A Group 30. Flash Memory FMR06 (Program status flag) (b6) This bit indicates the auto-program operation state. Condition to become 0: • Execute the clear status command. Condition to become 1: • Refer to 30.8.6.1 “Full Status Check”. Do not execute the following commands when the FMR06 bit is 1: Program, block erase, lock bit program, and block blank check.
Page 697 M16C/64A Group 30. Flash Memory 30.3.2 Flash Memory Control Register 1 (FMR1) Flash Memory Control Register 1 b6 b5 b4 Symbol Address Reset Value FMR1 00X0 XX0Xb 0221h Bit Symbol Bit Name Function — Reserved bit The read value is undefined. (b0) Write to FMR6 register 0 : Disabled...
Page 698 M16C/64A Group 30. Flash Memory 30.3.3 Flash Memory Control Register 2 (FMR2) Flash Memory Control Register 2 b6 b5 b4 Symbol Address Reset Value FMR2 XXXX 0000b 0222h Bit Symbol Bit Name Function — Set to 0 Reserved bits (b1-b0) Slow read mode enable 0 : Disabled FMR22...
Page 699 M16C/64A Group 30. Flash Memory 30.3.4 Flash Memory Control Register 6 (FMR6) Flash Memory Control Register 6 b6 b5 b4 Symbol Address Reset Value FMR6 XX0X XX00b 0230h Bit Symbol Bit Name Function 0 : EW0 mode FMR60 EW1 mode select bit 1 : EW1 mode Reserved bit Set to 1...
Page 700 M16C/64A Group 30. Flash Memory 30.4 Optional Function Select Area In an option function select area, the MCU state after reset and the function to prevent rewrite in parallel I/O mode are selected. The option function select area is not an SFR, and therefore cannot be rewritten by a program. Set an appropriate value when writing a program to the flash memory.
Page 701 M16C/64A Group 30. Flash Memory 30.4.1 Optional Function Select Address 1 (OFS1) Optional Function Select Address 1 b6 b5 b4 Symbol Address OFS1 FFFFFh Bit Symbol Bit Name Function 0 : Watchdog timer starts automatically WDTON Watchdog timer start select bit after reset 1 : Watchdog timer is stopped after reset —...
Page 702 M16C/64A Group 30. Flash Memory 30.5 Flash Memory Rewrite Disable Function This function disables the flash memory from being read, written, and erased. The following are details for each mode: Parallel I/O mode ROM code protect function Standard serial I/O mode ID code check function, forced erase function, and standard serial I/O mode disable function 30.6 Boot Mode...
Page 703 M16C/64A Group 30. Flash Memory Program ROM 2 User Boot Code Area 10000h 13FF0h Boot code User boot start address 13FF8h Address Port information for entry 13FFAh 13FFBh Start level select 13000h 13FFCh On-chip debugger monitor area Reserved space 13FF0h 13FFFh User boot code area 13FFFh...
Page 704 M16C/64A Group 30. Flash Memory Table 30.9 Addresses of Selectable Ports for Entry Address Port 13FF9h 13FF8h Table 30.10 Example Settings of User Boot Code Area When starting up in user boot mode while input level of the port P1_5 is low: Address Setting Value Meaning...
Page 705 M16C/64A Group 30. Flash Memory When the RESET pin changes from low to high, CNVSS = VSS CNVSS = VCC1, P5_5 = Low, and P5_0 = High Single-chip mode Boot mode Meets the condition of user Does not meet the condition boot code area of user boot code area Standard serial I/O...
Page 706 M16C/64A Group 30. Flash Memory 30.8 CPU Rewrite Mode In CPU rewrite mode, the flash memory can be rewritten when the CPU executes software commands. Program ROM 1, program ROM 2, and data flash can be rewritten with the MCU mounted on the board and without using a ROM programmer.
Page 707 M16C/64A Group 30. Flash Memory 30.8.1 EW0 Mode The MCU enters CPU rewrite mode when the FMR01 bit in the FMR0 register is set to 1 (CPU rewrite mode enabled) and is ready to accept commands. EW0 mode is selected by setting the FMR60 bit in the FMR6 register to 0.
Page 708 M16C/64A Group 30. Flash Memory Table 30.12 Modes after Executing Commands (in EW0 Mode) Command Mode after Executing Command Read array Read array mode Clear status register Read array mode Program Block erase Read status register mode Lock bit program Read lock bit status Read lock bit status mode Block blank check...
Page 709 M16C/64A Group 30. Flash Memory 30.8.2 EW1 Mode EW1 mode is selected by setting the FMR60 bit in the FMR6 register to 1 after setting the FMR01 bit in the FMR0 register to 1. Figure 30.6 shows Setting and Resetting of EW1 Mode. When a program or erase operation is initiated, the CPU halts all program execution until the operation is completed.
Page 710 M16C/64A Group 30. Flash Memory Table 30.13 Modes after Executing Commands (in EW1 Mode) Command Mode after Executing Command Read array Clear status register Program Block erase Read array mode Lock bit program Read lock bit status Block blank check R01UH0136EJ0210 Rev.2.10 Page 677 of 800 Jul 31, 2012...
Page 711 M16C/64A Group 30. Flash Memory 30.8.3 Operating Speed Select a CPU clock frequency of 10 MHz or less by setting the CM06 bit in the CM0 register and bits CM17 and CM16 in the CM1 register before entering CPU rewrite mode (EW0 or EW1 mode). Also, set the PM17 bit in the PM1 register to 1 (wait state).
Page 712 M16C/64A Group 30. Flash Memory 30.8.5 Software Commands Table 30.15 lists Software Commands. Read or write commands and data in 16-bit units. When command code is written, the upper 8 bits (D15 to D8) are ignored. Table 30.15 Software Commands First Bus Cycle Second Bus Cycle Third Bus Cycle...
Page 713 M16C/64A Group 30. Flash Memory 30.8.5.2 Read Status Register Command The read status register command is used to read the status register. By writing the command code xx70h in the first bus cycle, the status register can be read in the second bus cycle.
Page 714 M16C/64A Group 30. Flash Memory 30.8.5.4 Program Command The program command is used to write 2 words (4 bytes) of data to the flash memory. By writing xx41h in the first bus cycle and data to the write address in the second and third bus cycles, an auto-program operation (data program and verify) is started.
Page 715 M16C/64A Group 30. Flash Memory 30.8.5.5 Block Erase Command By writing xx20h in the first bus cycle and xxD0h to the highest even address of a block in the second bus cycle, an auto-erase operation (erase and verify) is started on the specified block. The FMR00 bit in the FMR0 register indicates whether the auto-erase operation has been completed.
Page 716 M16C/64A Group 30. Flash Memory 30.8.5.6 Lock Bit Program Command The lock bit program command is used to set the lock bit for a specified block to 0 (locked). By writing xx77h in the first bus cycle and xxD0h to the highest even address of a block in the second bus cycle, the lock bit for the specified block is set to 0.
Page 717 M16C/64A Group 30. Flash Memory 30.8.5.7 Read Lock Bit Status The read lock bit status command is used to read the lock bit state of a specified block. By writing xx71h in the first bus cycle and xxD0h to the highest even address of a block in the second bus cycle, the FMR16 bit in the FMR1 register stores information on the lock bit status of a specified block.
Page 718 M16C/64A Group 30. Flash Memory 30.8.5.8 Block Blank Check Command The block blank check command is used to check whether or not a specified block is blank (state after erase). By writing xx25h in the first bus cycle and xxD0h in the second bus cycle to the highest even address of a block, the check result is stored in the FMR07 bit in the FMR0 register.
Page 719 M16C/64A Group 30. Flash Memory 30.8.6 Status Register The status register indicates flash memory operating state and whether or not an erase or program operation has been completed as expected. Bits FMR00, FMR06, and FMR07 in the FMR0 register indicate status register states. Refer to 30.3.1 “Flash Memory Control Register 0 (FMR0)”...
Page 720 M16C/64A Group 30. Flash Memory 30.8.6.1 Full Status Check If an error occurs, bits FMR06 and FMR07 in the FMR0 register become 1, indicating the occurrence of an error. Therefore, the execution results can be confirmed by checking these status bits (full status check).
Page 721 M16C/64A Group 30. Flash Memory 30.8.6.2 Handling Procedure for Errors When errors occur, follow the procedures below. Do not execute the program, block erase, lock bit program, and block blank check commands when either FMR06 or FMR07 bit is 1 (completed in error). Execute each command after executing the clear status register command.
Page 722 M16C/64A Group 30. Flash Memory 30.9 Standard Serial I/O Mode In standard serial I/O mode, a serial programmer supporting the M16C/64A Group can be used to rewrite program ROM 1, program ROM 2, and data flash while the MCU is mounted on a board. Standard serial I/O mode has following modes: •...
Page 723 M16C/64A Group 30. Flash Memory 30.9.1 ID Code Check Function Use the ID code check function in standard serial I/O mode. This function determines whether the ID codes sent from the serial programmer match those written in the flash memory. If the ID codes do not match, commands sent from the serial programmer are not accepted.
Page 724 M16C/64A Group 30. Flash Memory 30.9.2 Forced Erase Function Use the forced erase function in standard serial I/O mode. When the reserved word, “ALeRASE” in ASCII code, is sent from the serial programmer as an ID code, the contents of program ROM 1 and program ROM 2 will all be erased.
Page 725 M16C/64A Group 30. Flash Memory 30.9.4 Standard Serial I/O Mode 1 In standard serial I/O mode 1, a serial programmer is connected to the MCU using clock synchronous serial I/O. Table 30.21 Pin Functions (Flash Memory Standard Serial I/O Mode 1) Power Name Description...
Page 726 M16C/64A Group 30. Flash Memory Table 30.22 Setting of Standard Serial I/O Mode 1 Signal Input Level CNVSS VCC1 RESET VSS → VCC1 VCC2 SCLK VCC1 VCC1 VCC2 SCLK input P6_5/CLK1 VCC1 P5_0 (CE) P6_7/TXD1 TXD output P5_5 (EPM) VCC1 P6_4/RTS1 BUSY output CNVSS...
Page 727 M16C/64A Group 30. Flash Memory 30.9.5 Standard Serial I/O Mode 2 In standard serial I/O mode 2, a serial programmer is connected to the MCU by using 2-wire clock asynchronous serial I/O. The main clock is used. Table 30.23 Pin Functions (Flash Memory Standard Serial I/O Mode 2) Power Name Description...
Page 728 M16C/64A Group 30. Flash Memory Table 30.24 Setting of Standard Serial I/O Mode 2 Signal Input Level CNVSS VCC1 RESET VSS → VCC1 VCC2 P6_5/CLK1 VCC2 P5_0 (CE) TXD output P6_7/TXD1 P5_5 (EPM) VCC1 P6_4/RTS1 Monitor output P6_6/RXD1 CNVSS RXD input VCC1 Reset input P6_5/CLK1...
Page 729: 30.11 Notes On Flash Memory
M16C/64A Group 30. Flash Memory 30.11 Notes on Flash Memory 30.11.1 OFS1 Address and ID Code Storage Address The OFS1 address and ID code storage address are part of flash memory. When writing a program to flash memory, write an appropriate value to those addresses simultaneously. In the OFS1 address, the MCU state after reset and the function to prevent rewrite in parallel I/O mode are selected.
Page 730: 30.11.3 Cpu Rewrite Mode
M16C/64A Group 30. Flash Memory 30.11.3 CPU Rewrite Mode 30.11.3.1 Operating Speed Select a CPU clock frequency of 10 MHz or less by setting the CM06 bit in the CM0 register and bits CM17 and CM16 in the CM1 register before entering CPU rewrite mode (EW0 or EW1 mode). Also, set the PM17 bit in the PM1 register to 1 (wait state).
Page 731 M16C/64A Group 30. Flash Memory 30.11.3.10 Software Command Observe the notes below when using the following commands. • Program • Block erase • Lock bit program • Read lock bit status • Block blank check (a) The FMR00 bit in the FMR0 register indicates the status while executing these commands. Do not execute other commands while the FMR00 bit is 0 (busy).
Page 732: 30.11.4 User Boot
M16C/64A Group 30. Flash Memory 30.11.4 User Boot 30.11.4.1 User Boot Mode Program Note the following when using user boot mode: • When using user boot mode, make sure to allocate the program to be executed to program ROM 2. •...
Page 733 M16C/64A Group 31. Electrical Characteristics 31. Electrical Characteristics 31.1 Electrical Characteristics (Common to 3 V and 5 V) 31.1.1 Absolute Maximum Rating Table 31.1 Absolute Maximum Ratings Symbol Parameter Condition Rated Value Unit − 0.3 to 6.5 Supply voltage = AV −...
Page 734 M16C/64A Group 31. Electrical Characteristics 31.1.2 Recommended Operating Conditions Table 31.2 Recommended Operating Conditions (1/3) = -20 ° C to 85 ° C/-40 ° C to 85 ° C unless otherwise specified. = 2.7 to 5.5 V at T Standard Symbol Parameter Unit...
Page 735 M16C/64A Group 31. Electrical Characteristics Table 31.3 Recommended Operating Conditions (2/3) = -20 ° C to 85 ° C/-40 ° C to 85 ° C unless otherwise specified. = 2.7 to 5.5 V at T Standard Symbol Parameter Unit Min. Typ.
Page 736 M16C/64A Group 31. Electrical Characteristics 31.1.3 A/D Conversion Characteristics Table 31.5 A/D Conversion Characteristics (1/2) = 3.0 to 5.5 V ≥ V ≥ V = -20 ° C to 85 ° C/-40 ° C to 85 ° C unless otherwise = AV = AV = 0 V at T...
Page 737 M16C/64A Group 31. Electrical Characteristics Table 31.6 A/D Conversion Characteristics (2/2) = 3.0 to 5.5 V ≥ V ≥ V = -20 ° C to 85 ° C/-40 ° C to 85 ° C unless otherwise = AV = AV = 0 V at T specified.
Page 738 Customers desiring program/erase failure rate information should contact a Renesas Electronics sales office. The data hold time includes time that the power supply is off or the clock is not supplied.
Page 739 Customers desiring program/erase failure rate information should contact a Renesas Electronics sales office. The data hold time includes time that the power supply is off or the clock is not supplied.
Page 740 M16C/64A Group 31. Electrical Characteristics 31.1.6 Voltage Detector and Power Supply Circuit Electrical Characteristics Table 31.11 Voltage Detector 0 Electrical Characteristics = -20 ° C to 85 ° C/-40 ° C to 85 ° C, unless otherwise specified. The measurement condition is V = 2.7 to 5.5 V, T Standard Symbol...
Page 741 M16C/64A Group 31. Electrical Characteristics Table 31.13 Voltage Detector 2 Electrical Characteristics = -20 ° C to 85 ° C/-40 ° C to 85 ° C, unless otherwise specified. The measurement condition is V = 2.7 to 5.5 V, T Standard Symbol Parameter...
Page 742 M16C/64A Group 31. Electrical Characteristics Table 31.15 Power Supply Circuit Timing Characteristics ° The measurement condition is V = 2.7 to 5.5 V and T = 25 C, unless otherwise specified. Standard Symbol Parameter Condition Unit Min. Typ. Max. Internal power supply stability time when power is on d(P-R) μ...
Page 743 M16C/64A Group 31. Electrical Characteristics 31.1.7 Oscillator Electrical Characteristics Table 31.16 125 kHz On-Chip Oscillator Electrical Characteristics = − 20 ° C to 85 ° C/ − 40 ° C to 85 ° C, unless otherwise specified. = 2.7 to 5.5 V, T Standard Symbol Parameter...
Page 744 M16C/64A Group 31. Electrical Characteristics 31.2 Electrical Characteristics (V = 5 V) 31.2.1 Electrical Characteristics = 5 V Table 31.17 Electrical Characteristics (1) = − 20 ° C to 85 ° C/ − 40 ° C to 85 ° C, f = 4.2 to 5.5 V, V = 0 V at T = 25 MHz unless otherwise...
Page 745 M16C/64A Group 31. Electrical Characteristics = 5 V Table 31.18 Electrical Characteristics (2) = − 20 ° C to 85 ° C/ − 40 ° C to 85 ° C, f = 4.2 to 5.5 V, V = 0 V at T = 25 MHz unless otherwise specified.
Page 746 M16C/64A Group 31. Electrical Characteristics = 5 V Table 31.19 Electrical Characteristics (3) R5F364A6NFA, R5F364A6NFB, R5F364A6DFA, R5F364A6DFB, R5F364AENFA, R5F364AENFB, R5F364AEDFA, R5F364AEDFB = − 20 ° C to 85 ° C/ − 40 ° C to 85 ° C, f = 4.2 to 5.5 V, V = 0 V at T = 25 MHz unless otherwise specified.
Page 747 M16C/64A Group 31. Electrical Characteristics = 5 V Table 31.20 Electrical Characteristics (4) R5F364AKNFA, R5F364AKNFB, R5F364AKDFA, R5F364AKDFB R5F364AMNFA, R5F364AMNFB, R5F364AMDFA, R5F364AMDFB = − 20 ° C to 85 ° C/ − 40 ° C to 85 ° C, f = 4.2 to 5.5 V, V = 0 V at T = 25 MHz unless otherwise specified.
Page 748 M16C/64A Group 31. Electrical Characteristics = 5 V 31.2.2 Timing Requirements (Peripheral Functions and Others) = -20 ° C to 85 ° C/-40 ° C to 85 ° C unless otherwise specified) = 5 V, V = 0 V, at T 31.2.2.1 Reset Input (RESET Input) Table 31.21...
Page 749 M16C/64A Group 31. Electrical Characteristics = 5 V Timing Requirements = -20 ° C to 85 ° C/-40 ° C to 85 ° C unless otherwise specified) = 5 V, V = 0 V, at T 31.2.2.3 Timer A Input Table 31.23 Timer A Input (Counter Input in Event Counter Mode) Standard...
Page 750 M16C/64A Group 31. Electrical Characteristics = 5 V Timing Requirements = -20 ° C to 85 ° C/-40 ° C to 85 ° C unless otherwise specified) = 5 V, V = 0 V, at T Table 31.27 Timer A Input (Two-Phase Pulse Input in Event Counter Mode) Standard Symbol Parameter...
Page 751 M16C/64A Group 31. Electrical Characteristics = 5 V Timing Requirements ° ° ° ° = 5 V, V = 0 V, at T = -20 C to 85 C/-40 C to 85 C unless otherwise specified) 31.2.2.4 Timer B Input Table 31.28 Timer B Input (Counter Input in Event Counter Mode) Standard...
Page 752 M16C/64A Group 31. Electrical Characteristics = 5 V Timing Requirements = -20 ° C to 85 ° C/-40 ° C to 85 ° C unless otherwise specified) = 5 V, V = 0 V, at T 31.2.2.5 Serial Interface Table 31.31 Serial Interface Standard Symbol...
Page 753 M16C/64A Group 31. Electrical Characteristics = 5 V Timing Requirements = -20 ° C to 85 ° C/-40 ° C to 85 ° C unless otherwise specified) = 5 V, V = 0 V, at T 31.2.2.7 Multi-master I C-bus Table 31.33 Multi-master I C-bus...
Page 754 M16C/64A Group 31. Electrical Characteristics = 5 V Timing Requirements = -20 ° C to 85 ° C/-40 ° C to 85 ° C unless otherwise specified) = 5 V, V = 0 V, at T 31.2.3 Timing Requirements (Memory Expansion Mode and Microprocessor Mode) Table 31.34 Memory Expansion Mode and Microprocessor Mode...
Page 755 M16C/64A Group 31. Electrical Characteristics = 5 V Memory Expansion Mode and Microprocessor Mode (Effective in wait state setting) BCLK (Separate bus) WR , WRL , WRH (Separate bus) (Multiplexed bus) WR , WRL , WRH (Multiplexed bus) RDY input su(RDY-BCLK) h(BCLK-RDY) Measuring conditions...
Page 756 M16C/64A Group 31. Electrical Characteristics = 5 V 31.2.4 Switching Characteristics (Memory Expansion Mode and Microprocessor Mode) = -20 ° C to 85 ° C/-40 ° C to 85 ° C unless otherwise specified) = 5 V, V = 0 V, at T 31.2.4.1 In No Wait State Setting Table 31.35...
Page 757 M16C/64A Group 31. Electrical Characteristics 30 pF Figure 31.14 Ports P0 to P10 Measurement Circuit R01UH0136EJ0210 Rev.2.10 Page 724 of 800 Jul 31, 2012...
Page 758 M16C/64A Group 31. Electrical Characteristics = 5V Memory Expansion Mode and Microprocessor Mode (in no wait state setting) Read timing BCLK d(BCLK-CS) h(BCLK-CS) 25ns(max.) 0ns(min.) d(BCLK-AD) h(BCLK-AD) 25ns(max.) 0ns(min.) h(BCLK-ALE) d(BCLK-ALE) h(RD-AD) -4ns(min.) 15ns(max.) 0ns(min.) h(BCLK-RD) d(BCLK-RD) 0ns(min.) 25ns(max.) ac1(RD-DB) (0.5 ×...
Page 759 M16C/64A Group 31. Electrical Characteristics = 5 V Switching Characteristics = -20 ° C to 85 ° C/-40 ° C to 85 ° C unless otherwise specified) = V CC2 = 5 V, V = 0 V, at T 31.2.4.2 In 1 to 3 Waits Setting and When Accessing External Area Table 31.36 Memory Expansion Mode and Microprocessor Mode (in 1 to 3 Waits Setting and When...
Page 760 M16C/64A Group 31. Electrical Characteristics = 5V Memory Expansion Mode and Microprocessor Mode (in 1 to 3 waits setting and when accessing external area) Read timing BCLK d(BCLK-CS) h(BCLK-CS) 25ns(max.) 0ns(min.) d(BCLK-AD) h(BCLK-AD) 25ns(max.) 0ns(min.) d(BCLK-ALE) h(RD-AD) h(BCLK-ALE) 15ns(max.) 0ns(min.) -4ns(min.) h(BCLK-RD) d(BCLK-RD)
Page 761 M16C/64A Group 31. Electrical Characteristics = 5 V Switching Characteristics = -20 ° C to 85 ° C/-40 ° C to 85 ° C unless otherwise specified) = V CC2 = 5 V, V = 0 V, at T 31.2.4.3 In 2 or 3 Waits Setting, and When Accessing External Area and Using Multiplexed Bus Table 31.37...
Page 762 M16C/64A Group 31. Electrical Characteristics = 5V Memory Expansion Mode and Microprocessor Mode (in 2 or 3 waits setting, and when accessing external area and using multiplexed bus ) Read timing BCLK h(BCLK-CS) d(BCLK-CS) 0ns(min.) h(RD-CS) 25ns(max.) (0.5 × t -10)ns(min.) d(AD-ALE) h(ALE-AD)
Page 763 M16C/64A Group 31. Electrical Characteristics 31.3 Electrical Characteristics (V = 3 V) 31.3.1 Electrical Characteristics VCC1 = VCC2 = 3 V Table 31.38 Electrical Characteristics (1) = -20 ° C to 85 ° C/-40 ° C to 85 ° C, f = 2.7 to 3.3 V, V = 0 V at T = 25 MHz unless otherwise specified.
Page 764 M16C/64A Group 31. Electrical Characteristics = 3 V Table 31.39 Electrical Characteristics (2) R5F364A6NFA, R5F364A6NFB, R5F364A6DFA, R5F364A6DFB, R5F364AENFA, R5F364AENFB, R5F364AEDFA, R5F364AEDFB = −20°C to 85°C/−40°C to 85°C, f = 2.7 to 3.3 V, V = 0 V at T = 25 MHz unless otherwise specified. (BCLK) Standard Symbol...
Page 765 M16C/64A Group 31. Electrical Characteristics = 3 V Table 31.40 Electrical Characteristics (3) R5F364AKNFA, R5F364AKNFB, R5F364AKDFA, R5F364AKDFB R5F364AMNFA, R5F364AMNFB, R5F364AMDFA, R5F364AMDFB = − 20 ° C to 85 ° C/ − 40 ° C to 85 ° C, f = 2.7 to 3.3 V, V = 0 V at T = 25 MHz unless otherwise specified.
Page 766 M16C/64A Group 31. Electrical Characteristics = 3 V 31.3.2 Timing Requirements (Peripheral Functions and Others) = -20 ° C to 85 ° C/-40 ° C to 85 ° C unless otherwise specified) = 3 V, V = 0 V, at T 31.3.2.1 Reset Input (RESET Input) Table 31.41...
Page 767 M16C/64A Group 31. Electrical Characteristics = 3 V Timing Requirements = -20 ° C to 85 ° C/-40 ° C to 85 ° C unless otherwise specified) = 3 V, V = 0 V, at T 31.3.2.3 Timer A Input Table 31.43 Timer A Input (Counter Input in Event Counter Mode) Standard...
Page 768 M16C/64A Group 31. Electrical Characteristics = 3 V Timing Requirements = -20 ° C to 85 ° C/-40 ° C to 85 ° C unless otherwise specified) = 3 V, V = 0 V, at T Table 31.47 Timer A Input (Two-Phase Pulse Input in Event Counter Mode) Standard Symbol Parameter...
Page 769 M16C/64A Group 31. Electrical Characteristics = 3 V Timing Requirements = -20 ° C to 85 ° C/-40 ° C to 85 ° C unless otherwise specified) = 3 V, V = 0 V, at T 31.3.2.4 Timer B Input Table 31.48 Timer B Input (Counter Input in Event Counter Mode) Standard...
Page 770 M16C/64A Group 31. Electrical Characteristics = 3 V Timing Requirements = -20 ° C to 85 ° C/-40 ° C to 85 ° C unless otherwise specified) = 3 V, V = 0 V, at T 31.3.2.5 Serial Interface Table 31.51 Serial Interface Standard Symbol...
Page 771 M16C/64A Group 31. Electrical Characteristics = 3 V Timing Requirements = -20 ° C to 85 ° C/-40 ° C to 85 ° C unless otherwise specified) = 3 V, V = 0 V, at T 31.3.2.7 Multi-master I C-bus Table 31.53 Multi-master I C-bus...
Page 772 M16C/64A Group 31. Electrical Characteristics = 3 V Timing Requirements = -20 ° C to 85 ° C/-40 ° C to 85 ° C unless otherwise specified) = 3 V, V = 0 V, at T 31.3.3 Timing Requirements (Memory Expansion Mode and Microprocessor Mode) Table 31.54 Memory Expansion Mode and Microprocessor Mode...
Page 773 M16C/64A Group 31. Electrical Characteristics = 3 V Memory Expansion Mode and Microprocessor Mode (Effective in wait state setting) BCLK (Separate bus) WR , WRL , WRH (Separate bus) (Multiplexed bus) WR , WRL , WRH (Multiplexed bus) RDY input su(RDY-BCLK) h(BCLK-RDY) Measuring conditions...
Page 774 M16C/64A Group 31. Electrical Characteristics = 3 V 31.3.4 Switching Characteristics (Memory Expansion Mode and Microprocessor Mode) = -20 ° C to 85 ° C/-40 ° C to 85 ° C unless otherwise specified) = 3 V, V = 0 V, at T 31.3.4.1 In No Wait State Setting Table 31.55...
Page 775 M16C/64A Group 31. Electrical Characteristics 30 pF Figure 31.27 Ports P0 to P10 Measurement Circuit R01UH0136EJ0210 Rev.2.10 Page 742 of 800 Jul 31, 2012...
Page 776 M16C/64A Group 31. Electrical Characteristics = 3V Memory Expansion Mode and Microprocessor Mode (in no wait state setting) Read timing BCLK d(BCLK-CS) h(BCLK-CS) 30ns(max.) 0ns(min.) d(BCLK-AD) h(BCLK-AD) 30ns(max.) 0ns(min.) h(BCLK-ALE) d(BCLK-ALE) h(RD-AD) -4ns(min.) 25ns(max.) 0ns(min.) h(BCLK-RD) d(BCLK-RD) 0ns(min.) 30ns(max.) ac1(RD-DB) (0.5 ×...
Page 777 M16C/64A Group 31. Electrical Characteristics = 3 V Switching Characteristics = -20 ° C to 85 ° C/-40 ° C to 85 ° C unless otherwise specified) = 3 V, V = 0 V, at T 31.3.4.2 In 1 to 3 Waits Setting and When Accessing External Area Table 31.56 Memory Expansion Mode and Microprocessor Mode (in 1 to 3 Waits Setting and When Accessing External Area)
Page 778 M16C/64A Group 31. Electrical Characteristics = 3V Memory Expansion Mode and Microprocessor Mode (in 1 to 3 waits setting and when accessing external area) Read timing BCLK d(BCLK-CS) h(BCLK-CS) 30ns(max.) 0ns(min.) h(BCLK-AD) d(BCLK-AD) 30ns(max.) 0ns(min.) d(BCLK-ALE) h(RD-AD) h(BCLK-ALE) 25ns(max.) 0ns(min.) -4ns(min.) h(BCLK-RD) d(BCLK-RD)
Page 779 M16C/64A Group 31. Electrical Characteristics = 3 V Switching Characteristics = -20 ° C to 85 ° C/-40 ° C to 85 ° C unless otherwise specified) = 3 V, V = 0 V, at T 31.3.4.3 In 2 or 3 Waits Setting, and When Accessing External Area and Using Multiplexed Bus Table 31.57 Memory Expansion Mode and Microprocessor Mode (in 2 or 3 Waits Setting, and When...
Page 780 M16C/64A Group 31. Electrical Characteristics = 3V Memory Expansion Mode and Microprocessor Mode (in 2 or 3 waits setting, and when accessing external area and using multiplexed bus ) Read timing BCLK h(BCLK-CS) d(BCLK-CS) 0ns(min.) h(RD-CS) 50ns(max.) (0.5 × t -10)ns(min.) d(AD-ALE) h(ALE-AD)
Page 781 M16C/64A Group 32. Usage Notes 32. Usage Notes 32.1 Notes on Noise Connect a bypass capacitor (approximately 0.1 µF) across pins VCC1 and VSS, and pins VCC2 and VSS using the shortest and thickest possible wiring. Figure 32.1 shows the Bypass Capacitor Connection. Bypass capacitor Connecting pattern Connecting pattern...
Page 782 M16C/64A Group 32. Usage Notes 32.2 Notes on SFRs 32.2.1 Register Settings Table 32.1 lists Registers with Write-Only Bits and registers whose function differs between reading and writing. Set these registers with immediate values. Do not use read-modify-write instructions. When establishing the next value by altering the existing value, write the existing value to the RAM as well as to the register.
Page 783 M16C/64A Group 32. Usage Notes Table 32.2 Read-Modify-Write Instructions Function Mnemonic Transfer MOV Dir Bit processing BCLR, BM Cnd , BNOT, BSET, BTSTC, and BTSTS Shifting ROLC, RORC, ROT, SHA, and SHL ABS, ADC, ADCF, ADD, DEC, DIV, DIVU, DIVX, EXTS, INC, MUL, MULU, NEG, Arithmetic operation SBB, and SUB Decimal operation...
Page 784 M16C/64A Group 32. Usage Notes 32.3 Notes on Protection After setting the PRC2 bit to 1 (write enabled), by writing to a given SFR, the PRC2 bit becomes 0 (write disabled). Change the registers protected by the PRC2 bit in the next instruction after setting the PRC2 bit to 1.
Page 785 M16C/64A Group 32. Usage Notes 32.4 Notes on Resets 32.4.1 Power Supply Rising Gradient When supplying power to the MCU, make sure that the power supply voltage applied to the VCC1 pin meets the SVCC conditions. Standard Symbol Parameter Unit Min.
Page 786 M16C/64A Group 32. Usage Notes 32.4.3 OSDR Bit (Oscillation Stop Detect Reset Detect Flag) When an oscillator stop detect reset is generated, the MCU is reset and then stopped. This state is canceled by hardware reset or voltage monitor 0 reset. Note that the OSDR bit in the RSTFR register is not affected by a hardware reset, but becomes 0 (not detected) from a voltage monitor 0 reset.
Page 787 M16C/64A Group 32. Usage Notes 32.5 Notes on Clock Generator 32.5.1 Oscillator Using a Crystal or a Ceramic Resonator To connect a crystal/ceramic resonator follow the instructions below: • The oscillation characteristics are tied closely to the user’s board design. Perform a careful evalua- tion of the board before connecting an oscillator.
Page 788 M16C/64A Group 32. Usage Notes 32.5.2 Noise Countermeasure 32.5.2.1 Clock I/O Pin Wiring • Connect the shortest possible wiring to the clock I/O pin. • Connect (a) the capacitor's ground lead connected to the crystal/ceramic resonator, and (b) the MCU's VSS pin, with the shortest possible wiring (maximum 20 mm). Noise XOUT XOUT...
Page 789 M16C/64A Group 32. Usage Notes 32.5.2.3 Signal Line Whose Level Changes at a High-Speed For a signal line whose level changes at a high-speed, wire it as far away from the crystal/ceramic resonator and its wiring pattern as possible. Do not wire it across or extend it parallel to a clock- related signal line or other signal lines which are sensitive to noise.
Page 790 M16C/64A Group 32. Usage Notes 32.5.5 PLL Frequency Synthesizer To use the PLL frequency synthesizer, stabilize the supply voltage within the acceptable range of power supply ripple. Table 32.4 Acceptable Range of Power Supply Ripple Standard Symbol Parameter Unit Min. Typ.
Page 791 M16C/64A Group 32. Usage Notes 32.5.6 Starting PLL Clock Oscillation (Technical update number: 16C-A177A/E) Adhere to the following restrictions when using the following products: R5F364AENFA, R5F364AENFB, R5F364AEDFA, R5F364AEDFB, R5F364A6NFA, R5F364A6NFB, R5F364A6DFA, R5F364A6DFB 32.5.6.1 When Using Voltage Detector 0, 1, or 2 Do not change the PLC07 bit in the PLC0 register from 0 to 1 when any bit from VC25 to VC27 in the VCR2 register is 1.
Page 792 M16C/64A Group 32. Usage Notes 32.6 Notes on Power Control 32.6.1 CPU Clock When switching the CPU clock source, wait until oscillation of the switched clock source is stable. After exiting stop mode, wait until oscillation stabilizes before changing the division. 32.6.2 Wait Mode •...
Page 793 M16C/64A Group 32. Usage Notes The following is an example program for entering stop mode: Program Example: FSET BSET 0, CM1 ; Enter stop mode JMP.B ; Insert a JMP.B instruction ; At least four NOP instructions • Do not enter stop mode from PLL operating mode. To enter stop mode from PLL operating mode, first enter medium-speed mode, then set the PLC07 bit to 0 (PLL off).
Page 794 M16C/64A Group 32. Usage Notes 32.7 Notes on Bus 32.7.1 Reading Data Flash When 2.7 V ≤ VCC1 ≤ 3.0 V and f(BCLK) ≥ 16 MHz, or when 3.0 V < VCC1 ≤ 5.5 V and f(BCLK) ≥ 20 MHz, one wait must be inserted to read the data flash. Use the PM17 bit or the FMR17 bit to insert one wait.
Page 795 M16C/64A Group 32. Usage Notes 32.8 Notes on Programmable I/O Ports Influence of SD 32.8.1 When a low-level signal is applied to the SD pin while the IVPCR1 bit in the TB2SC register is 1 (three- phase output forcible cutoff by input on SD pin enabled), the following pins become high-impedance: P7_2/CLK2/TA1OUT/V, P7_3/ CTS2 / RTS2 /TA1IN/ V , P7_4/TA2OUT/W, P7_5/TA2IN/ W , P8_0/TA4OUT/RXD5/SCL5/U, P8_1/TA4IN/ CTS5 / RTS5 / U 32.8.2...
Page 796 M16C/64A Group 32. Usage Notes 32.9 Notes on Interrupts 32.9.1 Reading Address 00000h Do not read address 00000h by a program. When a maskable interrupt request is accepted, the CPU reads interrupt information (interrupt number and interrupt request priority level) from address 00000h during the interrupt sequence.
Page 797 M16C/64A Group 32. Usage Notes 32.9.4 Changing an Interrupt Source When the interrupt source is changed, the IR bit in the interrupt control register may become 1 (interrupt requested). To use an interrupt, change the interrupt source, and then set the IR bit to 0 (interrupt not requested).
Page 798 M16C/64A Group 32. Usage Notes 32.9.5 Rewriting the Interrupt Control Register To modify the interrupt control register, follow either of the procedures below: • Modify in places where no interrupt requests corresponding to the interrupt control register may occur. • If an interrupt request can be generated, disable that interrupt and then rewrite the interrupt control register.
Page 799 M16C/64A Group 32. Usage Notes INT Interrupt 32.9.7 • Either a low level of at least tw(INL) width or a high level of at least tw(INH) width is necessary for the signal input to pins INT0 through INT7 , regardless of the CPU operation clock. •...
Page 800 M16C/64A Group 32. Usage Notes 32.10 Notes on the Watchdog Timer After the watchdog timer interrupt is generated, use the WDTR register to refresh the watchdog timer counter. R01UH0136EJ0210 Rev.2.10 Page 767 of 800 Jul 31, 2012...
Page 801 M16C/64A Group 32. Usage Notes 32.11 Notes on DMAC 32.11.1 Write to the DMAE Bit in the DMiCON Register (i = 0 to 3) (Technical update number: TN-M16C-92-0306) When both of the following conditions are met, follow steps (1) and (2) below. Conditions •...
Page 802 M16C/64A Group 32. Usage Notes 32.12 Notes on Timer A 32.12.1 Common Notes on Multiple Modes 32.12.1.1 Register Setting The timer stops after reset. Set the mode, count source, counter value, etc., using registers TAiMR, TAi, TAi1, UDF, TRGSR, PWMFS, TACS0 to TACS2, TAPOFS, PCLKR, and bits TAZIE, TA0TGL, and TA0TGH in the ONSF register before setting the TAiS bit in the TABSR register to 1 (count started) (i = 0 to 4).
Page 803 M16C/64A Group 32. Usage Notes 32.12.2 Timer A (Timer Mode) 32.12.2.1 Reading the Timer The counter value can be read from the TAi register at any time while counting. However, if the coun- ter is read at the same time as it is reloaded, the read value is FFFFh. Also, if the counter is read before it starts counting, or after a value is set in the TAi register while not counting, the set value is read.
Page 804 M16C/64A Group 32. Usage Notes 32.12.5 Timer A (Pulse Width Modulation Mode) 32.12.5.1 Changing Operating Modes The IR bit becomes 1 when setting a timer operating mode with any of the following: • Selecting PWM mode or programmable output mode after reset •...
Page 805 M16C/64A Group 32. Usage Notes 32.12.6 Timer A (Programmable Output Mode) 32.12.6.1 Changing the Operating Mode The IR bit becomes 1 when setting a timer operating mode with any of the following: • Selecting PWM mode or programmable output mode after reset •...
Page 806 M16C/64A Group 32. Usage Notes 32.13 Notes on Timer B 32.13.1 Common Notes on Multiple Modes 32.13.1.1 Register Setting The timer is stopped after reset. Set the mode, count source, etc., using registers TBiMR, TBCS0 to TBCS3, TBi, PCLKR, PPWFS1, and PPWFS2 before setting the TBiS bit in the TABSR or TBSR register to 1 (count started) (i = 0 to 5).
Page 807 M16C/64A Group 32. Usage Notes 32.13.4 Timer B (Pulse Period/Pulse Width Measurement Modes) 32.13.4.1 MR3 Bit in the TBiMR Register To clear the MR3 bit to 0 by writing to the TBiMR register while the TBiS bit is 1 (count started), be sure to set the same value as previously set to bits TMOD0, TMOD1, MR0, MR1, TCK0, and TCK1, and set bit 4 to 0.
Page 808 M16C/64A Group 32. Usage Notes 32.14 Notes on Three-Phase Motor Control Timer Function 32.14.1 Timer A and Timer B Refer to 17.5 “Notes on Timer A” and 18.5 “Notes on Timer B”. 32.14.2 Influence of SD When a low-level signal is applied to the SD pin while the IVPCR1 bit in the TB2SC register is 1 (three- phase output forcible cutoff by input on SD pin enabled), the following pins become high-impedance: P7_2/CLK2/TA1OUT/V, P7_3/ CTS2 / RTS2 /TA1IN/ V , P7_4/TA2OUT/W, P7_5/TA2IN/ W , P8_0/TA4OUT/RXD5/SCL5/U, P8_1/TA4IN/ CTS5 / RTS5 / U...
Page 809 M16C/64A Group 32. Usage Notes 32.15 Notes on Real-Time Clock 32.15.1 Starting and Stopping the Count The real-time clock uses the TSTART bit for instructing the count to start or stop, and the TCSTF bit which indicates count started or stopped. Bits TSTART and TCSTF are in the RTCCR1 register. The real-time clock starts counting and the TCSTF bit becomes 1 (count started) when the TSTART bit is set to 1 (count started).
Page 810 M16C/64A Group 32. Usage Notes 32.15.4 Time Reading Procedure in Real-Time Clock Mode In real-time clock mode, read time data bits when the BSY bit in the RTCSEC register is 0 (not while data is updated). When reading multiple registers, if data is rewritten between reading registers, an errant time will be read.
Page 811 M16C/64A Group 32. Usage Notes 32.16 Notes on Remote Control Signal Receiver 32.16.1 Starting/Stopping PMCi The EN bit in the PMCiCON0 register controls the start/stop of PMCi. The ENFLG bit in the PMCiCON2 register indicates that operation started/stopped. The PMCi circuit starts operating by setting the EN bit to 1 (operation enabled) and the ENFLG bit becomes 1 (operating).
Page 812 M16C/64A Group 32. Usage Notes 32.16.4 Combined Operation When using combined operation, set same value to bits TYP1 to TYP0 in the PMC0CON1 register and bits TYP1 to TYP0 in the PMC1CON1 register. R01UH0136EJ0210 Rev.2.10 Page 779 of 800 Jul 31, 2012...
Page 813 M16C/64A Group 32. Usage Notes 32.17 Notes on Serial Interface UARTi (i = 0 to 2, 5 to 7) 32.17.1 Common Notes on Multiple Modes 32.17.1.1 Influence of SD When a low-level signal is applied to the SD pin while the IVPCR1 bit in the TB2SC register is 1 (three- phase output forcible cutoff by input on SD pin enabled), the following pins become high-impedance: P7_2/CLK2/TA1OUT/V, P7_3/ CTS2 / RTS2 /TA1IN/ V , P7_4/TA2OUT/W, P7_5/TA2IN/ W , P8_0/TA4OUT/RXD5/SCL5/U, P8_1/TA4IN/ CTS5 / RTS5 / U...
Page 814 M16C/64A Group 32. Usage Notes 32.17.2.3 Reception In clock synchronous serial I/O mode, a shift clock is generated by activating a transmitter. Set the UARTi-associated registers for a transmit operation even if the MCU is used for a receive operations only.
Page 815 M16C/64A Group 32. Usage Notes 32.17.3.3 Low/High-level Input Voltage and Low-level Output Voltage The low-level input voltage, high-level input voltage, and low-level output voltage differ from the I bus specification. Refer to the recommended operating conditions for I/O ports which share the pins with SCL and SDA.
Page 816 M16C/64A Group 32. Usage Notes 32.17.3.5 Restrictions on the Bit Rate When Using the UiBRG Count Source In I C mode, set the UiBRG register to a value of 03h or greater. A maximum of three UiBRG count source cycles are necessary until the internal circuit acknowledges the SCL clock level.
Page 817 M16C/64A Group 32. Usage Notes 32.18 Notes on SI/O3 and SI/O4 32.18.1 SOUTi Pin Level When SOUTi Output Is Disabled When the SMi2 bit in the SiC register is set to 1 (SOUTi output disabled), the target pin becomes high- impedance regardless of which pin function being used.
Page 818 M16C/64A Group 32. Usage Notes 32.19 Notes on Multi-master I C-bus Interface 32.19.1 Limitation on CPU Clock When the CM07 bit in the CM0 register is 1 (CPU clock is a sub clock), do not access the registers listed in Table 25.4 “Registers”. Set the CM07 bit to 0 (main clock, PLL clock, or on-chip oscillator clock) to access these registers.
Page 819 M16C/64A Group 32. Usage Notes 32.19.4 Generating Stop Condition (Technical update number: TN-16C-A176A/E) In the multi-master I C-bus interface, when the slave device and/or other master devices drive the SCLMM line low, no normal stop condition is generated. This is because the SDAMM line is released while the SCLMM line is still driven low.
Page 820 M16C/64A Group 32. Usage Notes Generate a stop condition Save the flag register on the stack and disable interrupts Change P7_0 pin (SDAMM) to forcibly output low Wait for t SU;DAT Change P7_1 pin (SCLMM) to forcibly output high (Hi-Z) P7_1 = 1 ? (SCLMM is line high?) Set an interrupt request source as rising edge of the SCLMM...
Page 821 M16C/64A Group 32. Usage Notes 32.20 Notes on CEC 32.20.1 Registers and Bit Operation The registers and bits of the CEC function are synchronized with the count source. Therefore, the internal circuit starts to operate from the next count source timing, while the values of the register are changed immediately after rewriting the register.
Page 822 M16C/64A Group 32. Usage Notes 32.21 Notes on A/D Converter 32.21.1 Analog Input Voltage Set the analog input voltage as follows: analog input voltage (AN_0 to AN_7, ANEX0, and ANEX1) ≤ VCC1 analog input voltage (AN0_0 to AN0_7 and AN2_7 to AN2_7) ≤ VCC2 32.21.2 Analog Input Pin Do not use any pin from AN4 to AN7 as analog input pin if any pin from KI0 to KI3 is used as a key input interrupt.
Page 823 M16C/64A Group 32. Usage Notes 32.21.7 State When Forcibly Terminated If A/D conversion in progress is halted by setting the ADST bit in the ADCON0 register to 0 (A/D conversion stopped), the conversion result is undefined. In addition, the unconverted ADi register (i = 0 to 7) may also become undefined.
Page 824 M16C/64A Group 32. Usage Notes 32.21.10 Repeat Mode, Repeat Sweep Mode 0, and Repeat Sweep Mode 1 In repeat mode, repeat sweep mode 0, and repeat sweep mode 1, when reading the ADi register (i = 0 to 7) during the period when the ADi register value is rewritten, an undefined value may be read. Read the ADi register several times to determine whether the read value is valid.
Page 825 M16C/64A Group 32. Usage Notes 32.22 Notes on D/A Converter 32.22.1 When Not Using the D/A Converter When not using the D/A converter, set the DAiE bit (i = 0, 1) in the DACON register to 0 (output disabled) and the DAi register to 00h in order to minimize unnecessary current consumption and prevent current flow to the R-2R resistor.
Page 826 M16C/64A Group 32. Usage Notes 32.23 Notes on Flash Memory 32.23.1 OFS1 Address and ID Code Storage Address The OFS1 address and ID code storage address are part of flash memory. When writing a program to flash memory, write an appropriate value to those addresses simultaneously. In the OFS1 address, the MCU state after reset and the function to prevent rewrite in parallel I/O mode are selected.
Page 827 M16C/64A Group 32. Usage Notes 32.23.3 CPU Rewrite Mode 32.23.3.1 Operating Speed Select a CPU clock frequency of 10 MHz or less by setting the CM06 bit in the CM0 register and bits CM17 and CM16 in the CM1 register before entering CPU rewrite mode (EW0 or EW1 mode). Also, set the PM17 bit in the PM1 register to 1 (wait state).
Page 828 M16C/64A Group 32. Usage Notes 32.23.3.10 Software Command Observe the notes below when using the following commands. • Program • Block erase • Lock bit program • Read lock bit status • Block blank check (a) The FMR00 bit in the FMR0 register indicates the status while executing these commands. Do not execute other commands while the FMR00 bit is 0 (busy).
Page 829 M16C/64A Group 32. Usage Notes 32.23.4 User Boot 32.23.4.1 User Boot Mode Program Note the following when using user boot mode: • When using user boot mode, make sure to allocate the program to be executed to program ROM 2. •...
Page 830 M16C/64A Group Appendix 1. Package Dimensions Appendix 1. Package Dimensions The information on the latest package dimensions or packaging may be obtained from “Packages“ on the Renesas Electronics website. JEITA Package Code RENESAS Code Previous Code MASS[Typ.] P-QFP100-14x20-0.65 PRQP0100JD-B 100P6F-A 1.8g...
Page 831 M16C/64A Group REGISTER INDEX REGISTER INDEX ..........111, 661 FMR0 ............664 FMR1 ..........112, 665 FMR2 ............666 FMR6 ..........621 AD0 to AD7 ..........623 ADCON0 ..........625 ADCON1 ..........622 ADCON2 ............337 ICTB2 ............195 ADIC ..........
Page 832 M16C/64A Group REGISTER INDEX ........... 195 PMC0IC ......... 415 PMC0INT, PMC1INT ......... 195 TA0IC to TA4IC ..........419 PMC0RBIT ........266 TA0MR to TA4MR ....... 412 PMC0STS, PMC1STS ..........261 TA0 to TA4 ........ 419 PMC0TIM, PMC1TIM ........... 331 TA1, TA2, TA4 ...........
Page 833 M16C/64A Group REGISTER INDEX ............66 VD1LS ............67 VW0C ............68 VW1C ..........70, 225 VW2C ............65 VWCE ............228 ............. 227 WDTR ............. 227 WDTS R01UH0136EJ0210 Rev.2.10 Page 800 of 800 Jul 31, 2012...
Page 834 Items revised or added in this version REVISION HISTORY M16C/64A Group User's Manual: Hardware Description Rev. Date Page Summary 2.10 Jul 31, 2012 Resets 6.2.1 Processor Mode Register 0 (PM0): Added the description regarding PM02, PM04 to PM07 to the register explanation. 6.4.3 Power-On Reset Function: Changed “the rise gradient is trth or more”...
Page 835 REVISION HISTORY M16C/64A Group User's Manual: Hardware Description Rev. Date Page Summary 2.10 Jul 31, 2012 32.19.3 Low/High-level Input Voltage and Low-level Output Voltage: Added Refer to 2. “Items revised or added in previous versions” for the items revised or added in previous versions. C - 2...
Page 836 Items revised or added in previous versions REVISION HISTORY M16C/64A Group Hardware Manual Description Rev. Date Page Summary 1.01 Feb 03, 2009 First Edition issued. Watchdog Timer Reset Register → Watchdog Timer Refresh Register 1.10 Jul 15, 2009 Table 1.2 "Specifications for the 100-Pin Package (2/2)" partially modified Table 1.3 "Product List"...
Page 837 REVISION HISTORY M16C/64A Group Hardware Manual Description Rev. Date Page Summary 1.10 Jul 15, 2009 Table 17.3 "I/O Ports" partially modified 17.2.3 "Timer A Count Source Select Register i (TACSi) (i = 0 to 2)" partially modified Table 17.8 "Event Counter Mode Specifications (When Not Processing Two-Phase Pulse Signal)" partially modified Table 17.10 "Event Counter Mode Specifications (When Processing Two-Phase Pulse Signal with Timers A2, A3, and A4)"...
Page 838 REVISION HISTORY M16C/64A Group Hardware Manual Description Rev. Date Page Summary 1.10 Jul 15, 2009 25.5.3 "Generating Stop Condition" added 577, 578 Figure 25.22 "Generating a Stop Condition" and Figure 25.23 "Abnormal Waveform" added 26.2.1 "CEC Function Control Register 1 (CECC1)" partially modified 26.2.2 "CEC Function Control Register 2 (CECC2)"...
Page 839 REVISION HISTORY M16C/64A Group Hardware Manual Description Rev. Date Page Summary 1.10 Jul 15, 2009 Table 31.14 "Power-On Reset Circuit" partially modified Figure 31.3 "Power-On Reset Circuit Electrical Characteristics" partially modified Table 31.16 "125 kHz On-Chip Oscillator Circuit Electrical Characteristics" partially modified Table 31.19 "Electrical Characteristics (3)"...
Page 840 REVISION HISTORY M16C/64A Group Hardware Manual Description Rev. Date Page Summary 2.00 Feb 07, 2011 Figure 6.1 Reset Circuit Block Diagram: • Deleted register/bit names included in each group of SFRs. • Added the NOR gate next to SFR (A). Table 6.2 Classification of SFRs Which are Reset: Added.
Page 841 REVISION HISTORY M16C/64A Group Hardware Manual Description Rev. Date Page Summary 2.00 Feb 07, 2011 76, 79 Table 7.7 Procedures for Setting Voltage Monitor 1 Interrupt/Reset Related Bits and Table 7.8 Procedure for Setting Voltage Monitor 2 Interrupt/Reset Related Bits: •...
Page 842 REVISION HISTORY M16C/64A Group Hardware Manual Description Rev. Date Page Summary 2.00 Feb 07, 2011 9.6.5 Slow Read Mode: Added. Processor Mode 10.2.1 Processor Mode Register 0 (PM0): Added the technical update number to the explanation of bits PM01 to PM00. Figure 10.1 Memory Map in Single-Chip Mode: Added the 384 KB row to Address YYYYYh.
Page 843 REVISION HISTORY M16C/64A Group Hardware Manual Description Rev. Date Page Summary 2.00 Feb 07, 2011 17.3.7 Programmable Output Mode (Timers A1, A2, and A4): Added “when the MR2 bit is 1” to the MR1 bit explanation of the Programmable Output Mode Timer Ai Mode Register (i = 1, 2, 4).
Page 844 REVISION HISTORY M16C/64A Group Hardware Manual Description Rev. Date Page Summary 2.00 Feb 07, 2011 Figure 22.8 Receive Buffer and Compare Function: Deleted the arrows from the PMC0RBIT register. 22.3.3 Pattern Match Mode (Combined Operation of PMC0 and PMC1): Changed “detected in PM1” in line 2 to “detected in PM0”. 433, 441 22.3.3.1 Setting Procedure, 22.3.5.1 Setting Procedure: Changed the procedure.
Page 845 REVISION HISTORY M16C/64A Group Hardware Manual Description Rev. Date Page Summary 2.00 Feb 07, 2011 Table 23.18 I C Mode Functions: • Deleted the description that the I C mode functions vary depending on the CKPH bit in the UiSMR3 register. •...
Page 846 REVISION HISTORY M16C/64A Group Hardware Manual Description Rev. Date Page Summary 2.00 Feb 07, 2011 25.2.5 I2C0 Clock Control Register (S20): • Changed the last lines of the explanations of bits CCR4 to CCR0 and FASTMODE. • Added the slave address content when the MSLAD bit in the S4D0 register is 0 to Table 25.5. 25.2.8 I2C0 Control Register 2 (S4D0): •...
Page 847 REVISION HISTORY M16C/64A Group Hardware Manual Description Rev. Date Page Summary 2.00 Feb 07, 2011 628, 628 Figure 27.6 A/D Open-Circuit Detection Example on AVCC (Preconversion Charge) Figure 27.7 A/D Open-Circuit Detection (Charge) Characteristics (Standard Characteristics): Added the switch right to the Analog input ANi. 629, 629 Figure 27.8 A/D Open-Circuit Detection Example on AVSS (Preconversion discharge) Figure 27.9 A/D Open-Circuit Detection (Discharge) Characteristics (Standard Characteristics): Added the measuring condition (common) and explanation for the horizontal axis.
Page 848 REVISION HISTORY M16C/64A Group Hardware Manual Description Rev. Date Page Summary 2.00 Feb 07, 2011 Figure 30.13 Read Lock Bit Status Command: • Changed “FMR16 = 0?” to “Read the FMR16 bit”. • Changed “Block is locked” and “Block is not locked” to “Read lock bit status completed”. 30.8.5.8 Block Blank Check Command: Added the explanation below Figure 30.14.
Page 849 REVISION HISTORY M16C/64A Group Hardware Manual Description Rev. Date Page Summary 2.00 Feb 07, 2011 Table 31.38 Electrical Characteristics (1): • Added rows for the CEC value to Leakage current in powered-off state, V , and V • Added “ZP, IDU, IDV, IDW” to the V row.
Page 850 REVISION HISTORY M16C/64A Group Hardware Manual Description Rev. Date Page Summary 2.00 Feb 07, 2011 32.17.4 Special Mode 4 (SIM Mode): • Added the technical update number. • Changed the conditions to generate a transmit interrupt request. 32.18.5 Pin Function Switch When Using the Internal Clock: Added the technical update number. 32.20.2 VIH of the CEC pin: Added.
Page 851 M16C/64A Group User’s Manual: Hardware Publication Date: Rev.1.01 Feb 03, 2009 Rev.2.10 Jul 31, 2012 Published by: Renesas Electronics Corporation...
Page 852 SALES OFFICES Refer to "http://www.renesas.com/" for the latest and detailed information. Renesas Electronics America Inc. 2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A. Tel: +1-408-588-6000, Fax: +1-408-588-6130 Renesas Electronics Canada Limited 1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada...
Page 853 M16C/64A Group R01UH0136EJ0210...

Renesas M16C/64A Series User Manual

Quick Reference

1 Overview

2 Central Processing Unit (CPU)

3 Address Space

4 Special Function Registers (Sfrs)

5 Protection

6 Resets

7 Voltage Detector

8 Clock Generator

9 Power Control

10 Processor Mode

11 Bus

12 Memory Space Expansion Function

13 Programmable I/O Ports

14 Interrupts

15 Watchdog Timer

16 Dmac

17 Timer a

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Summary of Contents for Renesas M16C/64A Series