Renesas M16C/64A Series User Manual page 758

M16C/64A Group
Memory Expansion Mode and Microprocessor Mode
(in no wait state setting)
Read timing
BCLK
CSi
ADi
BHE
ALE
RD
DBi
Write timing
BCLK
CSi
ADi
BHE
ALE
WR , WRL ,
WRH
DBi
t =
cyc
Measuring conditions
V
CC1
Input timing voltage: V = 0.8 V, V
Output timing voltage: V = 0.4 V, V
Figure 31.15 Timing Diagram
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
t
d(BCLK-CS)
25ns(max.)
t
cyc
t
d(BCLK-AD)
25ns(max.)
t
t
h(BCLK-ALE)
d(BCLK-ALE)
-4ns(min.)
15ns(max.)
t
d(BCLK-RD)
25ns(max.)
t
ac1(RD-DB)
(0.5 × t - 45)ns(max.)
cyc
Hi-Z
t
su(DB-RD)
40ns(min.)
t
d(BCLK-CS)
25ns(max.)
t
cyc
t
d(BCLK-AD)
25ns(max.)
t
t
h(BCLK-ALE)
d(BCLK-ALE)
-4ns(min.)
15ns(max.)
t
d(BCLK-WR)
25ns(max.)
Hi-Z
(0.5 × t
1
f
(BCLK)
= V = 5V
CC2
IL IH
OL
t
h(BCLK-CS)
0ns(min.)
t
h(BCLK-AD)
0ns(min.)
t
h(RD-AD)
0ns(min.)
t
h(BCLK-RD)
0ns(min.)
t
h(RD-DB)
0ns(min.)
t
h(BCLK-AD)
0ns(min.)
t
h(WR-AD)
(0.5 × t - 10)ns(min.)
cyc
t
h(BCLK-WR)
0ns(min.)
t
d(BCLK-DB)
40ns(max.)
t t
d(DB-WR) h(WR-DB)
- 40)ns(min.) (0.5 × t - 10)ns(min.)
cyc cyc
= 2.0 V
= 2.4 V
OH
31. Electrical Characteristics
V = V
CC1 CC2
t
h(BCLK-CS)
0ns(min.)
t
h(BCLK-DB)
0ns(min.)
Page 725 of 800
= 5V