Renesas M16C/64A Series User Manual page 847

REVISION HISTORY
Rev. Date
Page
2.00 Feb 07, 2011 628, 628 Figure 27.6 A/D Open-Circuit Detection Example on AVCC (Preconversion Charge)
629, 629 Figure 27.8 A/D Open-Circuit Detection Example on AVSS (Preconversion discharge)
631, 633,
635, 637,
639, 640
643
643
D/A Converter
648
CRC Calculator
Chap. 29. Changed the order of the registers.
651
Flash Memory
Chap.30. 30.11.1 Functions to Prevent Flash Memory from Being Rewritten in the previous version: Deleted.
657
659
661
663
665
666
668
668
670
670
671
672
673
674, 676 Table 30.12 and Table 30.13 Modes after Executing Commands: Added.
675
678
680, 681
M16C/64A Group Hardware Manual
Figure 27.7 A/D Open-Circuit Detection (Charge) Characteristics (Standard Characteristics):
Added the switch right to the Analog input ANi.
Figure 27.9 A/D Open-Circuit Detection (Discharge) Characteristics (Standard Characteristics):
Added the measuring condition (common) and explanation for the horizontal axis.
Figure 27.10 to Figure 27.14 Operation Example and Figure 27.15 Transition Diagram of Pins
Used during A/D Conversion in Repeat Sweep Mode 1:
Minor addition to the figure contents.
27.7.1 Analog Input Voltage:
• Section title added.
• Deleted "When VCC1 ≥ VCC2".
27.7.2 Analog Input Pin: Partially changed the description.
Figure 28.2 D/A Converter Equivalent Circuit:
Changed the direction of the DAiE bit in the DACON register.
29.2.1 SFR Snoop Address Register (CRCSAR): Changed the explanation of bits CRCSR and
CRCSW.
Table 30.2 Flash Memory Rewrite Modes Overview:
Added "CPU operating mode" and "On-board rewrite" rows.
Figure 30.1 Flash Memory Block Diagram: Added "Program ROM 1 size 384 KB".
30.3.1 Flash Memory Control Register 0 (FMR0):
• Added the conditions to become 0 in the FMR00 bit explanation.
• Changed "low is input" to "high is input" in the FMR01 bit explanation.
• Added the last line in the FMR02 explanation.
• Added the description for the FMR22 bit to the last paragraph of the FMSTP bit explanation.
30.3.2 "Flash Memory Control Register 1 (FMR1)":
Changed "low is input" to "high is input" in the FMR11 bit explanation.
30.3.4 Flash Memory Control Register 6 (FMR6):
Changed "low is input" to "high is input" and added the last line in the FMR60 bit explanation.
Figure 30.2 Option Function Select Area: Added the reserved area.
30.7 User Boot Mode: Added.
30.7.1 User Boot Function
Deleted "The content of the OFS1 address is valid." from the third paragraph below Table 30.6.
Table 30.9 Addresses of Selectable Ports for Entry:
Divided the Address column into columns "13FF9h" and "13FF8h".
Table 30.10 Example Settings of User Boot Code Area: Added.
Figure 30.4 Program Starting Address in User Boot Mode: Added.
Table 30.11 EW0 Mode and EW1 Mode:
• Changed the EW1 Mode column in the State during auto write and auto erase row.
• Changed note 1.
30.8.1 EW0 Mode:
• Deleted "the flash memory is reset. The flash memory restarts after a certain period of time" from
the second bullet below Figure 30.5.
• Changed the last paragraph.
30.8.2 EW1 Mode:
• Deleted "the flash memory is reset. The flash memory restarts after a certain period of time" from
the third bullet below Figure 30.6.
• Added the description for the CSPRO bit to the last paragraph.
Table 30.15 Software Commands: Added note 1.
30.8.5.4 Program Command and 30.8.5.5 Block Erase Command:
Deleted the description for the status register in EW0 mode.
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Description
Summary