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M16C/64A Group
CM04
S
Q
CM10 = 1
(stop mode)
R
S
Q
WAIT
R
instruction
RESET
Software reset
NMI
PM24
Interrupt request level judgment
output
Voltage monitor 0 reset
Voltage monitor 1 reset
Voltage monitor 2 reset
Voltage monitor 1 interrupt
Voltage monitor 2 interrupt
Watchdog timer reset
Oscillator stop detect reset
CM00 to CM02, CM04 to CM07
CM10, CM11, CM14, CM16, CM17
PCLK5
: Bit in the PCLKR register
CM21, CM27
: Bits in the CM2 register
PM00, PM01
: Bits in the PM0 register
PM24
: Bit in the PM2 register
Main
Clock
PLL Frequency Synthesizer
Main
Clock
Figure 8.1
System Clock Generator
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
Sub clock oscillator
XCIN
XCOUT
Sub clock
125 kHz
fOCO-S
CM14
on-chip
oscillator
Oscillator
stop/restart
Main clock
detector
PLL frequency
XIN
XOUT
synthesizer
PLL clock
CM11
1
0
Main clock
oscillator
CM05
a
: Bits in the CM0 register
: Bits in the CM1 register
Oscillator Stop/Restart Detector
Clock edge
detector,
Charge/
pulse generator
discharge
for charge/
circuit
discharge control
1/32 or 1/48
Phase
comparator
Reference
clock divider
I/O ports
PM01 to PM00 = 00b, CM01 to CM00 = 01b, PCLK5 = 0
fC
1/32
CM21
1
a
0
CM02
1/2
1/2
1/2
1/4
CM06 = 0
CM06 = 0
CM17 to CM16
CM17 to
= 10b
CM16 = 01b
CM06 = 0, CM17 to CM16 = 00b
CM27 = 0
Reset
generator
Oscillator stop/
restart detect
CM27 = 1
interrupt
generator
Charge
pump
8. Clock Generator
CM01 to CM00 = 00b, PCLK5 = 0
PM01 to PM00 = 00b,
CM01 to CM00 = 10b, PCLK5 = 0
f8
PM01 to PM00 = 00b,
PM01 to PM00 = 00b,
CM01 to CM00 = 00b,
CM01 to CM00 = 11b, PCLK5 = 0
PCLK5 = 1
f32
fC32
fOCO-S
f1
CM07
b
c
1
d
Divider
0
b
1/2
1/2
1/2
1/8
1/16
CM06 = 0
CM17 to CM16 = 11b
CM06 = 1
Divider Details
Oscillator stop
detect reset
Oscillator stop/
restart detect
interrupt signal
CM21 switch signal
Divider
Voltage
control
oscillator
(VCO)
Internal
lowpass filter
CLKOUT
fC
Peripheral
function
clock
CPU clock
BCLK
c
1/32
d
PLL clock
Page 84 of 800
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