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M16C/64A Group
(1) Example of Transmit Timing (Internal Clock Selected)
Transmit/receive
clock
1
TE bit in the
UiC1 register
0
1
TI bit in the
UiC1 register
0
High
CTSi
Low
CLKi
TXDi
TXEPT flag in
1
the UiC0
0
register
1
IR bit in the
SiTIC register
0
i = 0 to 2, 5 to 7
The above assumes the following:
• The CKDIR bit in the UiMR register is 0 (internal clock).
• The CRD bit in the UiC0 register is 0 ( CTS / RTS enabled), the CRS bit is 0 ( CTS selected).
• The CKPOL bit in the UiC0 register is 0 (transmit data output at the falling edge and receive data
taken in at the rising edge of the transmit/receive clock).
• The UiIRS bit in the UiC1 or UCON register is 0 (an interrupt request occurs when the UiTB
register becomes empty).
(2) Example of Receive Timing (External Clock Selected)
1
RE bit in the
UiC1 register 0
TE bit in the
1
UiC1 register
0
1
TI bit in the
UiC1 register
0
High
RTSi
Low
CLKi
RXDi
Data is transferred from the UARTi
RI bit in the
1
receive register to the UiRB register
UiC1 register
0
IR bit in
1
SiRIC register
0
OER flag in the
1
UiRB register
0
i = 0 to 2, 5 to 7
The above assumes the following:
• The CKDIR bit in the UiMR register is 1 (external clock).
• The CRD bit in the UiC0 register is 0 ( CTS / RTS enabled), the CRS bit is 1
( RTS selected).
• The CKPOL bit in the UiC0 register is 0 (transmit data output at the falling edge and
receive data taken in at the rising edge of the transmit/receive clock).
fEXT: Frequency of the external clock
Figure 23.5
Transmit and Receive Operation during Clock Synchronous Serial I/O Mode
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
Tc
Set the data in the UiTB register.
T
CLK
D0 D1 D2 D3 D4 D5 D6 D7
Set the dummy data in the UiTB
register.
Data is transferred from the UiTB register to the UARTi transmit register.
1/fEXT
Received data is taken in
D0 D1 D2 D3 D4 D5 D6 D7
Set to 0 by an interrupt request acknowledgment or by a program.
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
Data is transferred from the UiTB register
to the UARTi transmit register.
Pulse stops because a high-level signal
is applied to CTSi
D0 D1 D2 D3 D4 D5 D6 D7
Set to 0 by an interrupt request acknowledgment or by a program.
A low-level signal is applied when the UiRB register is read.
D0 D1 D2 D3 D4 D5
D6
D7
Read the UiRB register
Make sure the following conditions are met when input
to the CLKi pin before receiving data is high:
· The TE bit in the UiC1 register = 1 (transmit enabled)
· The RE bit in the UiC1 register = 1 (receive enabled)
· Write dummy data to the UiTB register
Pulse stops because the TE bit is set to 0
D0 D1 D2 D3 D4 D5 D6 D7
T
= T
= 2(n + 1)/fj
C
CLK
fj: Frequency of UiBRG count source
(f1SIO, f2SIO, f8SIO, f32SIO)
n: Value set to the UiBRG register
D0 D1 D2 D3 D4 D5
D6
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