Renesas M16C/64A Series User Manual page 813

M16C/64A Group
32.17 Notes on Serial Interface UARTi (i = 0 to 2, 5 to 7)
32.17.1 Common Notes on Multiple Modes
32.17.1.1 Influence of SD
When a low-level signal is applied to the SD pin while the IVPCR1 bit in the TB2SC register is 1 (three-
phase output forcible cutoff by input on SD pin enabled), the following pins become high-impedance:
P7_2/CLK2/TA1OUT/V, P7_3/ CTS2 / RTS2 /TA1IN/ V , P7_4/TA2OUT/W,
P7_5/TA2IN/ W , P8_0/TA4OUT/RXD5/SCL5/U, P8_1/TA4IN/ CTS5 / RTS5 / U
32.17.1.2 CLKi Output
(Technical update number: TN-16C-A178A/E)
When using the N-channel open drain output as an output mode of the CLKi pin, use following
procedure to change the pin function:
When changing the pin function from the port to CLKi.
(1) Set bits SMD2 to SMD0 in the UiMR register to a value other than 000b to select serial interface
mode.
(2) Set the NODC bit in the UiSMR3 register to 1.
When changing the pin function from CLKi to the port.
(1) Set the NODC bit to 0.
(2) Set bits SMD2 to SMD0 to 000b to disable the serial interface.
32.17.2 Clock Synchronous Serial I/O Mode
32.17.2.1 Transmission/Reception
When the RTS function is used with an external clock, the RTSi pin (i = 0 to 2, 5 to 7) outputs a low-
level signal, which informs the transmitting side that the MCU is ready for a receive operation. The
RTSi pin outputs a high-level signal when a receive operation starts. Therefore, transmit timing and
receive timing can be synchronized by connecting the RTSi pin to the CTSi pin on the transmitting
side. The RTS function is disabled when an internal clock is selected.
32.17.2.2 Transmission
If the transmission is started while an external clock is selected and the TXEPT bit in the UiC0
register (i = 0 to 2, 5 to 7) is 1 (no data present in transmit register), meet the last requirement at
either of the following timings:
External clock level:
•
The CKPOL bit in the UiC0 register is 0 (transmit data is output at the falling edge of
transmit/receive clock and receive data is input at the rising edge) and the external clock is high.
•
The CKPOL bit is 1 (transmit data is output at the rising edge of transmit/receive clock and receive
data is input at the falling edge) and the external clock is low.
Requirements to start transmission (in no particular order):
•
The TE bit in the UiC1 register is 1 (transmission enabled).
•
The TI bit in the UiC1 register is 0 (data present in the UiTB register).
When the CTS function is selected, input on the CTSi pin is low.
•
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
32. Usage Notes
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