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M16C/64A Group
When setting the WIT bit to 1 in receive mode, and the ACK clock is present:
2
(I
C-bus interrupt is enabled at eighth clock)
SCLMM
SDAMM
ACKBIT bit in the
S20 register
PIN bit in the S10 register
Internal WAIT flag
IR bit in the IICIC register
Write signal to the
S00 register
When setting the WIT bit to 0 in receive mode, and the ACK clock is present:
2
(I
C-bus interrupt is disabled at eighth clock)
SCLMM
SDAMM
ACKBIT bit in the
S20 register
PIN bit in the S10 register
Internal WAIT flag
IR bit in the IICIC register
Write signal to the
S00 register
Figure 25.4
Interrupt Request Generation Timing in Receive Mode
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
7
8
Write by a program
Set to 0 by an interrupt acceptance or by a program
7
8
0
0
Set to 0 by an interrupt acceptance or
by a program
25. Multi-master I
9
ACK
clock
(1)
9
ACK
clock
ACK bit
(2)
2
C-bus Interface
(2)
1
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