Renesas M16C/64A Series User Manual page 82

M16C/64A Group
ROMCR (ROM code protect cancel bit) (b2)
ROMCP1 (ROM code protect bit) (b3)
These bits prevent the flash memory from being read or changed in parallel I/O mode.
Table 6.6 ROM Code Protection
Bit Setting
ROMCR bit
0
0
1
1
VDSEL1 (Vdet0 select bit 1) (b5)
Set this bit to 0 (Vdet0_2) when using the power-on reset or voltage monitor 0 reset. Refer to 6.4.10
"Cold/Warm Start Discrimination".
This bit is enabled in single-chip mode, while disabled in boot mode.
LVDAS (Voltage detector 0 start bit) (b6)
Set this bit to 0 (voltage monitor 0 reset enabled after hardware reset) when using the power-on reset.
This bit is enabled in single-chip mode, while disabled in boot mode.
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
ROM Code Protection
ROMCP1 bit
0
1
0
1
Cancelled
Enabled
Cancelled
6. Resets
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