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M16C/64A Group
Table 22.9
Registers and Setting Values in Pattern Match Mode (Independent Operation) (1/2)
Register
PMCiCON0
PMCiCON1
PMCiCON2
PMCiCON3
PMCiSTS
i = 0, 1
-: Unimplemented bits in PMC1
Note:
1.
This table does not describe a procedure.
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
Bit
EN
Set to 1.
SINV
Select input signal polarity.
Select filter enabled or
FIL
disabled.
Select receive error holding
EHOLD
period.
Select header enabled or
HDEN
disabled.
Select special data enabled or
SDEN
disabled.
DRINT0
Select receive interrupt
generating condition.
DRINT1
TYP0
Select measuring object.
TYP1
CSS
Set to 0.
EXSDEN
Set to 0.
EXHDEN
Set to 0.
Flag indicating PMC0
ENFLG
operated/stopped.
INFLG
Input signal flag
CEFLG
Not used.
CEINT
Set to 0.
PSEL0
Set to 01b.
PSEL1
CRE
Set to 0.
CFR
Set to 0.
CST
Set to 0.
PD
Set to 0.
CSRC0
Select clock source
CSRC1
CDIV0
Select count source divisor.
CDIV1
CPFLG
Compare match flag
REFLG
Receive error flag
DRFLG
Data receiving flag
BFULFLG
Receive buffer full flag
PTHDFLG
Header pattern match flag
PTD0FLG
Data 0 pattern match flag
PTD1FLG
Data 1 pattern match flag
SDFLG
Special pattern match flag
22. Remote Control Signal Receiver
Function
PMC0
Set to 1.
Select input signal polarity.
Select filter enabled or
disabled.
Select header enabled or
disabled.
Select measuring object.
Flag indicating PMC1
operated/stopped.
Input signal flag
Not used.
Set to 0.
Select input pin.
Set to 0.
Set to 0.
Set to 0.
Set to 0.
Select clock source
Select count source divisor.
Receive error flag
Data receiving flag
Header pattern match flag
Data 0 pattern match flag
Data 1 pattern match flag
(1)
PMC1
-
-
-
-
-
-
-
-
-
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