Page 1 On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding.
Page 2 Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as “Specific”...
Page 3 User’s Manual V850E/SJ3-H, V850E/SK3-H 32-bit Single-Chip Microcontrollers Hardware V850E/SJ3-H: μ μ μ PD70F3474 PD70F3475 PD70F3476 μ μ μ PD70F3477 PD70F3478 PD70F3479 μ μ μ PD70F3931 PD70F3932 PD70F3933 μ μ μ PD70F3934 PD70F3935 PD70F3936 μ μ μ PD70F3937 PD70F3938 PD70F3939 V850E/SK3-H: μ...
Page 4 [MEMO] User’s Manual U19201EJ3V0UD...
Page 5 NOTES FOR CMOS DEVICES (1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction.
Page 6 ® Caution: This product uses SuperFlash technology licensed from Silicon Storage Technology, Inc. IECUBE is a registered trademark of NEC Electronics Corporation in Japan and Germany. MINICUBE is a registered trademark of NEC Electronics Corporation in Japan and Germany or a trademark in the United States of America.
Page 7 PREFACE Readers This manual is intended for users who wish to understand the functions of the V850E/SJ3-H and V850E/SK3-H and design application systems using the V850E/SJ3-H and V850E/SK3-H. Purpose This manual is intended to give users an understanding of the hardware functions of the V850E/SJ3-H and V850E/SK3-H shown in the Organization below.
Page 8 The mark <R> shows major revised points. The revised points can be easily searched by copying an “<R>” in the PDF file and specifying it in the “Find what:” field. Conventions Data significance: Higher digits on the left and lower digits on the right Active low representation: xxx (overscore over pin or signal name) Memory map address:...
Page 9 Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents related to V850E/SJ3-H, V850E/SK3-H Document Name Document No. V850E1 Architecture User’s Manual U14559E V850E/SJ3-H, V850E/SK3-H Hardware User’s Manual This manual Documents related to development tools Document Name...
Page 10: Table Of Contents
CONTENTS CHAPTER 1 INTRODUCTION ........................ 22 General ............................22 Features .............................25 Application Fields ........................27 Ordering Information ........................28 1.4.1 V850E/SJ3-H..........................28 1.4.2 V850E/SK3-H ..........................29 Pin Configuration (Top View)....................29 1.5.1 V850E/SJ3-H..........................29 1.5.2 V850E/SK3-H ..........................32 Function Block Configuration....................35 1.6.1 Internal block diagram .........................35 1.6.2 Internal units ..........................39 CHAPTER 2 PIN FUNCTIONS .......................
Page 11 4.2.1 V850E/SJ3-H..........................134 4.2.2 V850E/SK3-H ..........................135 Port Configuration ........................136 4.3.1 Port 0............................141 4.3.2 Port 1............................145 4.3.3 Port 2 (V850E/SK3-H only) ....................... 146 4.3.4 Port 3............................148 4.3.5 Port 4............................157 4.3.6 Port 5............................161 4.3.7 Port 6............................167 4.3.8 Port 7............................
Page 12 Wait Function...........................311 5.6.1 Programmable wait function ......................311 5.6.2 External wait function ........................314 5.6.3 Relationship between programmable wait and external wait .............315 5.6.4 Programmable address wait function..................316 Idle State Insertion Function....................318 Bus Hold Function ........................319 5.8.1 Functional outline ........................319 5.8.2 Bus hold procedure ........................320 5.8.3 Operation in power save mode....................320 Bus Priority ..........................321...
Page 13 7.6.8 Encoder count function (only for TMP7 and TMP8)..............477 7.6.9 Encoder compare mode (TPmMD3 to TPmMD0 bits = 1000) ........... 491 Selector Function........................499 Cautions...........................501 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) ..............502 Overview ..........................502 Functions ..........................502 Configuration ..........................503 Registers..........................506 Timer Output Operations .......................521 Operation ..........................522 8.6.1...
Page 14 CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2 ..............661 11.1 Functions ..........................661 11.2 Configuration...........................662 11.3 Registers ..........................663 11.4 Operation ..........................667 CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO)..............668 12.1 Function ...........................668 12.2 Configuration...........................669 12.3 Registers ..........................671 12.4 Operation ..........................673 12.5 Usage............................674 12.6 Cautions ...........................674 CHAPTER 13 A/D CONVERTER ......................
Page 15 15.6.2 SBF transmission/reception format ................... 735 15.6.3 SBF transmission ........................737 15.6.4 SBF reception..........................738 15.6.5 UART transmission ........................739 15.6.6 Continuous transmission procedure ..................740 15.6.7 UART reception......................... 742 15.6.8 Reception errors........................743 15.6.9 Parity types and operations ....................... 745 15.6.10 Receive data noise filter ......................
Page 16 17.6.10 Continuous transfer mode (slave mode, transmission mode)............861 17.6.11 Continuous transfer mode (slave mode, reception mode) ............863 17.6.12 Continuous transfer mode (slave mode, transmission/reception mode) ........866 17.6.13 Reception error..........................870 17.6.14 Clock timing ..........................871 17.7 Output Pins ..........................873 17.8 Baud Rate Generator ......................874 17.8.1 Baud rate generation .........................876 17.9 Cautions ...........................877...
Page 17 19.10 Error Detection........................987 19.11 Extension Code........................988 19.12 Arbitration..........................989 19.13 Wakeup Function ........................990 19.14 Communication Reservation ....................991 19.14.1 When communication reservation function is enabled (IICFn.IICRSVn bit = 0)......991 19.14.2 When communication reservation function is disabled (IICFn.IICRSVn bit = 1) ......995 19.15 Cautions...........................996 19.16 Communication Operations....................998 19.16.1 Master operation in single master system .................
Page 18 21.2.4 Error frame ..........................1094 21.2.5 Overload frame........................1095 21.3 Functions ..........................1096 21.3.1 Determining bus priority......................1096 21.3.2 Bit stuffing..........................1096 21.3.3 Multi masters ...........................1096 21.3.4 Multi cast ..........................1096 21.3.5 CAN sleep mode/CAN stop mode function................1097 21.3.6 Error control function .......................1097 21.3.7 Baud rate control function......................1104 21.4 Connection with Target System ..................
Page 19 21.15 Baud Rate Settings .......................1216 21.15.1 Bit rate setting conditions ......................1216 21.15.2 Representative examples of baud rate settings............... 1220 21.16 Operation of CAN Controller ....................1224 CHAPTER 22 DMA FUNCTION (DMA CONTROLLER) ..............1250 22.1 Features ..........................1250 22.2 Configuration ........................1251 22.3 Registers..........................1252 22.4 Transfer Targets........................1261 22.5 Transfer Modes ........................1261 22.6 Transfer Types ........................1262...
Page 20 24.5.2 Debug trap..........................1310 24.6 External Interrupt Request Input Pins (NMI and INTP0 to INTP9) ........1312 24.6.1 Noise elimination ........................1312 24.6.2 Edge detection.........................1312 24.7 Interrupt Acknowledge Time of CPU.................. 1323 24.8 Periods in Which Interrupts Are Not Acknowledged by CPU.......... 1325 24.9 Cautions ..........................
Page 21 CHAPTER 28 CLOCK MONITOR .......................1370 28.1 Functions ..........................1370 28.2 Configuration ........................1370 28.3 Register..........................1371 28.4 Operation ..........................1372 CHAPTER 29 LOW-VOLTAGE DETECTOR..................1375 29.1 Functions ..........................1375 29.2 Configuration ........................1375 29.3 Registers..........................1376 29.4 Operation ..........................1378 29.4.1 To use for internal reset signal (LVIRES) ................1378 29.4.2 To use for interrupt (INTLVI) ....................
Page 22 33.2 Option Byte (0000007BH) ....................1423 CHAPTER 34 ON-CHIP DEBUG FUNCTION ................... 1425 34.1 Debugging with DCU ......................1426 34.1.1 Connection circuit example......................1426 34.1.2 Interface signals ........................1427 <R> 34.1.3 Maskable functions........................1429 34.1.4 Register ...........................1429 34.1.5 Operation..........................1431 34.1.6 Cautions ..........................1432 <R> 34.2 Debugging Without Using DCU ..................
Page 23 Control Software ........................1497 Debugging Tools (Hardware)....................1498 A.4.1 When using IECUBE QB-V850ESX3H..................1498 A.4.2 When using on-chip debug emulator IE-V850E1-CD-NW ............1501 A.4.3 When using MINICUBE QB-V850MINI..................1502 <R> A.4.4 When using MINICUBE2 QB-MINI2 ..................1503 Debugging Tools (Software) ....................1504 Embedded Software ......................1505 Flash Memory Writing Tools....................1506 APPENDIX B REGISTER INDEX......................1507 APPENDIX C INSTRUCTION SET LIST....................1527...
Page 24: Chapter 1 Introduction
CHAPTER 1 INTRODUCTION The V850E/SJ3-H and V850E/SK3-H are the products in the NEC Electronics V850 single-chip microcontrollers designed for real-time control applications. General The V850E/SJ3-H and V850E/SK3-H are 32-bit single-chip microcontrollers that include the V850E1 CPU core and peripheral functions such as ROM/RAM, a timer/counter, serial interfaces, an A/D converter, and a D/A converter. As for automotive LAN, the V850E/SJ3-H and V850E/SK3-H are provided with IEBus (Inter Equipment Bus ), and...
Page 25 CHAPTER 1 INTRODUCTION Table 1-1. V850E/SJ3-H and V850E/SK3-H Products (1/2) (a) V850E/SJ3-H (144-pin plastic LQFP (20 × 20)) Function RAM Size Operating Automotive LAN Maskable Interrupts Non- (+ Expanded Frequency Maskable Type Size External Internal Internal RAM (MAX.) Interrupts Part Number Size) μ...
Page 26 CHAPTER 1 INTRODUCTION Table 1-1. V850E/SJ3-H and V850E/SK3-H Products (2/2) (b) V850E/SK3-H (176-pin plastic LQFP (24 × 24)) Function RAM Size Operating Automotive LAN Maskable Interrupts Non- (+ Expanded Frequency Maskable Type Size External Internal Internal RAM (MAX.) Interrupts Part Number Size) μ...
Page 27: Features
CHAPTER 1 INTRODUCTION Table 1-2. V850ES/SJ3 Products Function RAM Size Operating Automotive LAN Maskable Interrupts Non- Frequency Maskable Type Size External Internal (MAX.) Interrupts Part Number μ PD70F3344 Flash 384 KB 32 KB 32 MHz On-chip IEBus: 1 ch memory μ...
Page 28 CHAPTER 1 INTRODUCTION Interrupts and exceptions: Non-maskable interrupts: 2 sources <R> Maskable interrupts: 98/102/104/106/108/112 sources (see Table 1-1) Software exceptions: 32 sources Exception trap: 2 sources I/O lines: I/O ports: 128 (V850E/SJ3-H) 156 (V850E/SK3-H) Timer function: 16-bit interval timer M (TMM): 3 channels 16-bit timer/event counter P (TMP): 9 channels (TMP7 and TMP8 include the encoder count function)
Page 29: Application Fields
CHAPTER 1 INTRODUCTION UARTA/CSIB/I μ 1 channel (Other than PD70F3931 (V850E/SJ3-H), 70F3932 (V850E/SJ3-H), and 70F3933 (V850E/SJ3-H)) μ <R> 0 channels ( PD70F3931 (V850E/SJ3-H), 70F3932 (V850E/SJ3-H), and 70F3933 (V850E/SJ3-H) only) Note These channels can also be used in the following combinations. CSIB: 2 channels UARTA/I C: 1 ch...
Page 30: Ordering Information
CHAPTER 1 INTRODUCTION Ordering Information 1.4.1 V850E/SJ3-H Part Number Package Internal ROM Quality Grade (Flash Memory) μ PD70F3474GJA-GAE-G 144-pin plastic LQFP 1280 KB (fine pitch) (20 × 20) μ PD70F3475GJA-GAE-G μ PD70F3476GJA-GAE-G μ PD70F3477GJA-GAE-G 1536 KB μ PD70F3478GJA-GAE-G μ PD70F3479GJA-GAE-G μ...
Page 31: V850E/Sk3-H
CHAPTER 1 INTRODUCTION 1.4.2 V850E/SK3-H Part Number Package Internal ROM Quality Grade (Flash Memory) μ PD70F3480GMA-GAR-G 176-pin plastic LQFP 1536 KB (fine pitch) (24 × 24) μ PD70F3481GMA-GAR-G μ PD70F3482GMA-GAR-G μ PD70F3486GMA-GAR-G 1280 KB μ PD70F3487GMA-GAR-G μ PD70F3488GMA-GAR-G μ PD70F3925GMA-GAR-G 1024 KB μ...
Page 32 CHAPTER 1 INTRODUCTION PDL3/AD3 REF0 PDL2/AD2 P10/ANO0 PDL1/AD1 P11/ANO1 PDL0/AD0 REF1 Note 1 P00/TIP61/TOP61/SDA04 Note 1 P01/TIP60/TOP60/SCL04 PCT7 Note 2 FLMD0 PCT6/ASTB PCT5 Note 3 REGC PCT4/RD PCT3 PCT2 PCT1/WR1 RESET PCT0/WR0 PCS7 PCS6 P02/NMI PCS5 P03/INTP0/ADTRG PCS4 P04/INTP1 PCM5 Note 4 P05/INTP2/DRST PCM4...
Page 33 CHAPTER 1 INTRODUCTION Pin names A0 to A23: Address bus Read strobe AD0 to AD15: Address/data bus REGC: Regulator control ADTRG: A/D trigger input RESET: Reset ANI0 to ANI15: Analog input RTP00 to RTP05, ANO0, ANO1: Analog output RTP10 to RTP15: Real-time output port ASCKA0: Asynchronous serial clock...
Page 34: V850E/Sk3-H
CHAPTER 1 INTRODUCTION 1.5.2 V850E/SK3-H 176-pin plastic LQFP (fine pitch) (24 × 24) μ μ μ PD70F3480GMA-GAR-G PD70F3481GMA-GAR-G PD70F3482GMA-GAR-G μ μ μ PD70F3486GMA-GAR-G PD70F3487GMA-GAR-G PD70F3488GMA-GAR-G μ μ μ PD70F3925GMA-GAR-G PD70F3926GMA-GAR-G PD70F3927GMA-GAR-G User’s Manual U19201EJ3V0UD...
Page 35 CHAPTER 1 INTRODUCTION PDL3/AD3 REF0 PDL2/AD2 P10/ANO0 PDL1/AD1 P11/ANO1 PDL0/AD0 P133 REF1 P00/TIP61/TOP61/SDA04 P132 P01/TIP60/TOP60/SCL04 P131 P20/SDA04 P130 P21/SCL04 Note 1 FLMD0 PCT7 Note 2 REGC PCT6/ASTB PCT5 PCT4/RD PCT3 RESET PCT2 PCT1/WR1 PCT0/WR0 P02/NMI PCS7 P03/INTP0/ADTRG PCS6 P04/INTP1 PCS5 Note 3 P05/INTP2/DRST PCS4...
Page 36 CHAPTER 1 INTRODUCTION Pin names A0 to A23: Address bus PDL0 to PDL15: Port DL AD0 to AD15: Address/data bus RC1CK1HZ, RC1CKDIV, ADTRG: A/D trigger input RC1CKO: Real-time counter clock output ANI0 to ANI15: Analog input Read strobe ANO0, ANO1: Analog output REGC: Regulator control...
Page 37: Function Block Configuration
CHAPTER 1 INTRODUCTION Function Block Configuration 1.6.1 Internal block diagram (1) V850E/SJ3-H V850E1 CPU MEMC INTC INTP0 to INTP9 HLDRQ Instruction 16-bit timer/ HLDAK TIQ00 to TIQ03 DMAC queue counter Q: ASTB TOQ00 to TOQ03 1 ch Multiplier WAIT 32-bit barrel TIP00 to TIP80, 32 →...
Page 38 CHAPTER 1 INTRODUCTION Notes 7. Another type of the block diagram is available in accordance with the combination of port sharing. TXDA0/SOB4 RXDA0/SIB4 UARTA0 CSIB4 ASCKA0/SCKB4 TXDA1/SDA02 UARTA1 I RXDA1/SCL02 Note 8 TXDA2/SIB2/SDA00 UARTA2 CSIB2 RXDA2/SCKB2/SCL00 Note 3 TXDA5/SCKB5/SCL05 Note 3 Note 3 UARTA5 CSIB5...
Page 39 CHAPTER 1 INTRODUCTION (2) V850E/SK3-H V850E1 CPU MEMC INTC INTP0 to INTP9 HLDRQ Instruction 16-bit timer/ HLDAK TIQ00 to TIQ03 DMAC queue counter Q: ASTB TOQ00 to TOQ03 1 ch Multiplier 32-bit barrel WAIT TIP00 to TIP80, 32 → 64 ×...
Page 40 CHAPTER 1 INTRODUCTION Note 6. An example of port sharing combinations is shown in the following block diagram. TXDA0/SOB4 RXDA0/SIB4 UARTA0 CSIB4 ASCKA0/SCKB4 SIB0/SDA01 CSIB0 I SOB0/SCL01 SCKB0 SIB2/SDA00 CSIB2 I SOB2/SCL00 SCKB2 TXDA1 to TXDA5 UARTA1 to UARTA5 RXDA1 to RXDA5 TXDB0, TXDB1 UARTB0, UARTB1...
Page 41: Internal Units
CHAPTER 1 INTRODUCTION 1.6.2 Internal units (1) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as a multiplier (32 bits × 32 bits → 64 bits) and a barrel shifter (32 bits) contribute to faster complex processing.
Page 42 CHAPTER 1 INTRODUCTION (8) Internal oscillator An internal oscillator is provided on chip. The oscillation frequency is 220 kHz (TYP.). An internal oscillator supplies the clock for watchdog timer 2 and timer M. (9) Timer/counter Nine-channel 16-bit timer/event counter P (TMP) (encoder count function is provided for TMP7 and TMP8), one-channel 16-bit timer/event counter Q (TMQ), and three-channel 16-bit interval timer M (TMM) are provided on chip.
Page 43 CHAPTER 1 INTRODUCTION (16) A/D converter This 10-bit A/D converter includes 16 analog input pins. Conversion is performed using the successive approximation method. (17) D/A converter A two-channel, 8-bit-resolution D/A converter that uses the R-2R ladder method is provided on chip. (18) DMA controller A 4-channel DMA controller is provided on chip.
Page 44 CHAPTER 1 INTRODUCTION (24) Ports The general-purpose port functions and control pin functions are listed below. Port Alternate Function <R> Note 2 7-bit I/O Timer I/O, serial interface , NMI, external interrupt, A/D converter trigger, debug reset 2-bit I/O D/A converter analog output Note 1 2-bit I/O (V850E/SK3-H) Serial interface...
Page 45: Chapter 2 Pin Functions
CHAPTER 2 PIN FUNCTIONS List of Pin Functions The names and functions of the pins of the V850E/SJ3-H and V850E/SK3-H are described below. There are four types of pin I/O buffer power supplies: AV , AV , BV , and EV .
Page 46 CHAPTER 2 PIN FUNCTIONS (1) Port pins (1/6) Pin Name Pin No. Function Alternate Function SJ3-H SK3-H Note 3 <R> Port 0 TIP61/TOP61/SDA04 7-bit I/O port Note 3 <R> TIP60/TOP60/SCL04 Input/output can be specified in 1-bit units. N-ch open-drain output can be specified in 1-bit units. INTP0/ADTRG 5 V tolerant.
Page 47 CHAPTER 2 PIN FUNCTIONS (2/6) Pin Name Pin No. Function Alternate Function SJ3-H SK3-H Port 4 SIB0/SDA01 V850E/SJ3-H: 3-bit I/O port SOB0/SCL01 V850E/SK3-H: 6-bit I/O port SCKB0/INTP2 Input/output can be specified in 1-bit units. − − Note 1 N-ch open-drain output can be specified in 1-bit units. 5 V tolerant.
Page 48 CHAPTER 2 PIN FUNCTIONS (3/6) Pin Name Pin No. Function Alternate Function SJ3-H SK3-H Port 7 ANI0 16-bit I/O port ANI1 Input/output can be specified in 1-bit units. ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ANI8 ANI9 P710 ANI10 P711 ANI11 P712 ANI12 P713...
Page 49 CHAPTER 2 PIN FUNCTIONS (4/6) Pin Name Pin No. Function Alternate Function SJ3-H SK3-H Port 9 A0/KR6/TXDA1/SDA02 16-bit I/O port A1/KR7/RXDA1/KR7/SCL02 Input/output can be specified in 1-bit units. A2/TIP41/TOP41 N-ch open-drain output can be specified in 1-bit units. A3/TIP40/TOP40/INTP8 5 V tolerant. A4/TIP31/TOP31 A5/TIP30/TOP30/INTP5 A6/TIP21/TOP21...
Page 50 CHAPTER 2 PIN FUNCTIONS (5/6) Pin Name Pin No. Function Alternate Function SJ3-H SK3-H PCD0 Port CD RXDB0 4-bit I/O port PCD1 TXDB0 Input/output can be specified in 1-bit units. PCD2 RXDB1 PCD3 TXDB1 Port CM PCM0 WAIT 6-bit I/O port PCM1 CLKOUT Input/output can be specified in 1-bit units.
Page 51 CHAPTER 2 PIN FUNCTIONS (6/6) Pin Name Pin No. Function Alternate Function SJ3-H SK3-H PDL0 Port DH 16-bit I/O port PDL1 Input/output can be specified in 1-bit units. PDL2 PDL3 PDL4 PDL5 AD5/FLMD1 PDL6 PDL7 PDL8 PDL9 PDL10 AD10 PDL11 AD11 PDL12 AD12...
Page 52 CHAPTER 2 PIN FUNCTIONS (2) Non-port pins (1/10) Pin Name Pin No. Function Alternate Function SJ3-H SK3-H Address bus for external memory Output P90/KR6/TXDA1/SDA02 (when using separate bus) P91/KR7/RXDA1/KR7/SCL02 Port 9 cannot be used as port pins or other alternate- P92/TIP41/TOP41 function pins when the A0 to A15 pins are used in the P93/TIP40/TOP40/INTP8...
Page 53 CHAPTER 2 PIN FUNCTIONS (2/10) Pin Name Pin No. Function Alternate Function SJ3-H SK3-H Address/data bus for external memory PDL0 PDL1 PDL2 PDL3 PDL4 PDL5/FLMD1 PDL6 PDL7 PDL8 PDL9 AD10 PDL10 AD11 PDL11 AD12 PDL12 AD13 PDL13 AD14 PDL14 AD15 PDL15 ADTRG Input...
Page 54 CHAPTER 2 PIN FUNCTIONS (3/10) Pin Name Pin No. Function Alternate Function SJ3-H SK3-H − − Reference voltage input for A/D converter, REF0 positive power supply for port 7 − Reference voltage input for D/A converter, REF1 positive power supply for port 1 −...
Page 55 CHAPTER 2 PIN FUNCTIONS (4/10) Pin Name Pin No. Function Alternate Function SJ3-H SK3-H INTP0 Input External interrupt request input (maskable, analog noise P03/ADTRG elimination). Analog noise elimination/digital noise INTP1 elimination selectable for the INTP3 pin. INTP2 P05/DRST 5 V tolerant P42/SCKB0 INTP3 INTP4...
Page 56 CHAPTER 2 PIN FUNCTIONS (5/10) Pin Name Pin No. Function Alternate Function SJ3-H SK3-H Note 1 Input Key interrupt input (on-chip analog noise eliminator) P54/SOB2/RTP04/DCK 5 V tolerant <R> Note 4 P63/RTP13/SIE1 Note 1 P55/SCKB2/RTP05/DMS Note 4 <R> P64/RTP14/SOE1 Note 1 P90/A0/TXDA1/SDA02 Notes 1, 2 P91/A1/RXDA1/KR7/SCL02...
Page 57 CHAPTER 2 PIN FUNCTIONS (6/10) Pin Name Pin No. Function Alternate Function SJ3-H SK3-H RXDA0 Input Serial receive data input (UARTA0 to UARTA5) P31/INTP7/SIB4 5 V tolerant Note1 RXDA1 P91/A1/KR7/KR7/SCL02 − Note 4 Note 4 P150 /KR7 RXDA2 P39/SCL00/SCKB2 − Note 4 P312 Note 2...
Page 58 CHAPTER 2 PIN FUNCTIONS (7/10) Pin Name Pin No. Function Alternate Function SJ3-H SK3-H Note 1 <R> SCL05 Serial clock I/O (I C00 to I C05) P68/SCKB5/TXDA5 N-ch open-drain output selectable − Note 2 5 V tolerant SDA00 Serial transmit/receive data I/O (I C00 to I C05) P38/TXDA2/SIB2...
Page 59 CHAPTER 2 PIN FUNCTIONS (8/10) Pin Name Pin No. Function Alternate Function SJ3-H SK3-H TIP00 Input External event count input/capture trigger input/external P32/ASCKA0/SCKB4/TOP00 trigger input (TMP0) 5 V tolerant Note 1 TIP01 Capture trigger input (TMP0) P33/TOP01/CTXD1 5V tolerant Note 1 TIP10 External event count input/capture trigger input/external P34/TOP10/CRXD1...
Page 60 CHAPTER 2 PIN FUNCTIONS (9/10) Pin Name Pin No. Function Alternate Function SJ3-H SK3-H TIP70 Input External event count input/capture trigger input/external P69/TOP70/TENC70 trigger input (TMP7) 5 V tolerant TIP71 Capture trigger input (TMP7) P610/TENC71 5V tolerant TIP80 External event count input/capture trigger input/external P612/TOP80/TENC80 trigger input (TMP8) 5 V tolerant...
Page 61 CHAPTER 2 PIN FUNCTIONS (10/10) Pin Name Pin No. Function Alternate Function SJ3-H SK3-H TOP50 Output Timer output (TMP5) P915/A15/INTP6/TIP50 N-ch open-drain output selectable, 5 V tolerant TOP51 P914/A14/INTP5/TIP51 Note 1 <R> TOP60 Output Timer output (TMP6) P01/TIP60/SCL04 N-ch open-drain output selectable, 5 V tolerant Note 1 <R>...
Page 62: Port Sharing Of Alternate Functions
CHAPTER 2 PIN FUNCTIONS Port Sharing of Alternate Functions The V850E/SJ3-H and V850E/SK3-H have the same alternate functions that are assigned to two ports. Which port is used for the alternate function can be selected at the port setup. Caution When using an alternate function that is assigned to two ports, always use the alternate function at only one of the ports.
Page 63 CHAPTER 2 PIN FUNCTIONS Table 2-2. Port Sharing of Alternate Functions (1/2) (a) V850E/SJ3-H Function Alternate Port <1> Port <2> Function Pin No. Port Pin No. Port Function Function External interrupt INTP2 Input INTP5 P914 INTP7 INTP8 CSIB2 SIB2 Input SCKB2 Key interrupt Input...
Page 64 CHAPTER 2 PIN FUNCTIONS Table 2-2. Port Sharing of Alternate Functions (2/2) (b) V850E/SK3-H Function Alternate Port <1> Port <2> Function Pin No. Port Pin No. Port Function Function External interrupt INTP2 Input INTP5 P914 INTP6 P915 P153 INTP7 INTP8 INTP9 P152 SCL04...
Page 65 CHAPTER 2 PIN FUNCTIONS The following shows a port sharing assignment diagram of alternate functions. Figure 2-1. Alternate-Function Port Sharing Assignment Diagram for V850E/SJ3-H (144-Pin Plastic LQFP (Fine Pitch) (20 × 20)) PDL3/AD3 REF0 PDL2/AD2 P10/ANO0 PDL1/AD1 P11/ANO1 PDL0/AD0 REF1 Note 1 P00/TIP61/TOP61/SDA04 Note 1...
Page 66 CHAPTER 2 PIN FUNCTIONS Figure 2-2 Alternate-Function Port Sharing Assignment Diagram for V850E/SK3-H (176-Pin Plastic LQFP (Fine Pitch) (24 × 24)) PDL3/AD3 REF0 PDL2/AD2 P10/ANO0 PDL1/AD1 P11/ANO1 PDL0/AD0 P133 REF1 P00/TIP61/TOP61/SDA04 P132 P01/TIP60/TOP60/SCL04 P131 P20/SDA04 P130 P21/SCL04 Note 1 FLMD0 PCT7 Note 2 REGC...
Page 67: Pin States
CHAPTER 2 PIN FUNCTIONS Pin States The operation states of pins in the various operation modes are described below. Table 2-3. Pin Operation States in Various Modes Note 3 Pin Name During Reset During Reset HALT IDLE1, STOP Idle State Bus Hold Note 2 Note 2...
Page 68: Pin I/O Circuit Types, I/O Buffer Power Supplies And Connection Of Unused Pins
CHAPTER 2 PIN FUNCTIONS Pin I/O Circuit Types, I/O Buffer Power Supplies and Connection of Unused Pins (1/6) Alternate Function Pin No. I/O Circuit Type Recommended Connection SJ3-H SK3-H <R> Note 2 TIP61/TOP61/SDA04 10-D Input: Independently connect to EV or EV via a resistor.
Page 69 CHAPTER 2 PIN FUNCTIONS (2/6) Alternate Function Pin No. I/O Circuit Type Recommended Connection SJ3-H SK3-H SIB0/SDA01 10-D Input: Independently connect to EV or EV a resistor. SOB0/SCL01 Output: Leave open. SCKB0/INTP2 − − Note 1 10-G − Note 1 Note 1 IETX0 −...
Page 70 CHAPTER 2 PIN FUNCTIONS (3/6) Alternate Function Pin No. I/O Circuit Type Recommended Connection SJ3-H SK3-H ANI0 11-G Input: Independently connect to AV or AV REF0 a resistor. ANI1 Output: Leave open. ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ANI8 ANI9 P710 ANI10 P711...
Page 71 CHAPTER 2 PIN FUNCTIONS (4/6) Alternate Function Pin No. I/O Circuit Type Recommended Connection SJ3-H SK3-H P912 A12/SCKB3 10-D Input: Independently connect to EV or EV via a resistor. P913 A13/INTP4 Output: Leave open. P914 A14/INTP5/TIP51/TOP51 P915 A15/INTP6/TIP50/TOP50 − − Note P130 Input:...
Page 72 CHAPTER 2 PIN FUNCTIONS (5/6) Alternate Function Pin No. I/O Circuit Type Recommended Connection SJ3-H SK3-H PCT0 Input: Independently connect to BV or BV via a resistor. PCT1 Output: Leave open. − PCT2 − PCT3 PCT4 − PCT5 PCT6 ASTB −...
Page 73 CHAPTER 2 PIN FUNCTIONS (6/6) Alternate Function Pin No. I/O Circuit Type Recommended Connection SJ3-H SK3-H − − Always connect this pin to the power supply (also in REF0 the standby mode). − REF1 − − Always connect this pin directly to the ground (also in the standby mode).
Page 74 CHAPTER 2 PIN FUNCTIONS Figure 2-3. Pin I/O Circuits Type 10-N Type 2 Data P-ch IN/OUT IN/OUT Open drain N-ch Output disable Schmitt-triggered input with hysteresis characteristics Note Input Type 5 enable OCDM0 bit N-ch Data P-ch IN/OUT Type 11-G Output N-ch REF0...
Page 75: Cautions
CHAPTER 2 PIN FUNCTIONS Cautions (1) Cautions on power application When the power is turned on, the following pins may momentarily output an undefined level. • P53/SIB2/KR3/TIQ00/TOQ00/RTP03/DDO pin User’s Manual U19201EJ3V0UD...
Page 76: Chapter 3 Cpu Function
CHAPTER 3 CPU FUNCTION The CPU of the V850E/SJ3-H and V850E/SK3-H is based on RISC architecture and executes almost all instructions with one clock by using a 5-stage pipeline. Features Minimum instruction execution time: 20.8 ns (operating with 48 MHz) μ...
Page 77: Cpu Register Set
CHAPTER 3 CPU FUNCTION CPU Register Set The registers of the V850E/SJ3-H and V850E/SK3-H can be classified into two types: general-purpose program registers and dedicated system registers. All the registers are 32 bits wide. For details, refer to the V850E1 Architecture User’s Manual. (1) Program register set (2) System register set (Zero register)
Page 78: Program Register Set
CHAPTER 3 CPU FUNCTION 3.2.1 Program register set The program registers include general-purpose registers and a program counter. (1) General-purpose registers (r0 to r31) Thirty-two general-purpose registers, r0 to r31, are available. Any of these registers can be used to store a data variable or an address variable.
Page 79: System Register Set
CHAPTER 3 CPU FUNCTION 3.2.2 System register set The system registers control the status of the CPU and hold interrupt information. These registers can be read or written by using system register load/store instructions (LDSR and STSR), using the system register numbers listed below. Table 3-2.
Page 80 CHAPTER 3 CPU FUNCTION (1) Interrupt status saving registers (EIPC and EIPSW) EIPC and EIPSW are used to save the status when an interrupt occurs. If a software exception or a maskable interrupt occurs, the contents of the program counter (PC) are saved to EIPC, and the contents of the program status word (PSW) are saved to EIPSW (these contents are saved to the NMI status saving registers (FEPC and FEPSW) if a non-maskable interrupt occurs).
Page 81 CHAPTER 3 CPU FUNCTION (2) NMI status saving registers (FEPC and FEPSW) FEPC and FEPSW are used to save the status when a non-maskable interrupt (NMI) occurs. If an NMI occurs, the contents of the program counter (PC) are saved to FEPC, and those of the program status word (PSW) are saved to FEPSW.
Page 82 CHAPTER 3 CPU FUNCTION (4) Program status word (PSW) The program status word (PSW) is a collection of flags that indicate the status of the program (result of instruction execution) and the status of the CPU. If the contents of a bit of this register are changed by using the LDSR instruction, the new contents are validated immediately after completion of LDSR instruction execution.
Page 83 CHAPTER 3 CPU FUNCTION (2/2) Note The result of the operation that has performed saturation processing is determined by the contents of the OV and S flags. The SAT flag is set to 1 only when the OV flag is set to 1 when a saturation operation is performed.
Page 84 CHAPTER 3 CPU FUNCTION (6) Exception/debug trap status saving registers (DBPC and DBPSW) DBPC and DBPSW are exception/debug trap status registers. If an exception trap or debug trap occurs, the contents of the program counter (PC) are saved to DBPC, and those of the program status word (PSW) are saved to DBPSW.
Page 85 CHAPTER 3 CPU FUNCTION (8) Program ID register (ASID) ASID sets the ID of the program in progress. Bits 31 to 8 of this register are reserved for future function expansion (fixed to 0). Caution To use the V850E/SJ3-H or V850E/SK3-H, initialize the ASID register to 00H in its initialization routine.
Page 86: Operation Modes
CHAPTER 3 CPU FUNCTION Operation Modes The V850E/SJ3-H and V850E/SK3-H have the following operation modes. (1) Normal operation mode In this mode, each pin related to the bus interface is set to the port mode after system reset has been released. Execution branches to the reset entry address of the internal ROM, and then instruction processing is started.
Page 87: Address Space
CHAPTER 3 CPU FUNCTION Address Space 3.4.1 CPU address space For instruction addressing, up to a combined total of 32 MB of external memory area and internal ROM area, plus an internal RAM area, are supported in a linear address space (program space) of up to 64 MB. For operand addressing (data access), up to 4 GB of a linear address space (data space) is supported.
Page 88: Wraparound Of Cpu Address Space
CHAPTER 3 CPU FUNCTION 3.4.2 Wraparound of CPU address space (1) Program space Of the 32 bits of the PC (program counter), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid. The higher 6 bits ignore a carry or borrow from bit 25 to 26 during branch address calculation. Therefore, the highest address of the program space, 03FFFFFFH, and the lowest address, 00000000H, are contiguous addresses.
Page 89: Memory Map
CHAPTER 3 CPU FUNCTION 3.4.3 Memory map The areas shown below are reserved in the V850E/SJ3-H and V850E/SK3-H. Figure 3-2. Data Memory Map (Physical Addresses) (1/2) (a) When using expanded internal RAM 0 3 F F F F F F H 0 3 F F F F F F H On-chip peripheral I/O area (4 KB)
Page 90 CHAPTER 3 CPU FUNCTION Figure 3-2. Data Memory Map (Physical Addresses) (2/2) <R> (b) When not using expanded internal RAM 0 3 F F F F F F H 0 3 F F F F F F H On-chip peripheral I/O area (4 KB) 0 3 F F F 0 0 0 H (80 KB)
Page 91 CHAPTER 3 CPU FUNCTION Figure 3-3. Program Memory Map (1/2) (a) When using expanded internal RAM 0 3 F F F F F F H Use prohibited (program fetch prohibited area) 0 3 F F F 0 0 0 H 0 3 F F E F F F H Internal RAM area (60 KB) 0 3 F F 0 0 0 0 H...
Page 92 CHAPTER 3 CPU FUNCTION Figure 3-3. Program Memory Map (2/2) <R> (b) When not using expanded internal RAM 0 3 F F F F F F H Use prohibited (program fetch prohibited area) 0 3 F F F 0 0 0 H 0 3 F F E F F F H Internal RAM area (60 KB) 0 3 F F 0 0 0 0 H...
Page 93: Areas
CHAPTER 3 CPU FUNCTION 3.4.4 Areas (1) Internal ROM area Up to 4 MB is reserved as an internal ROM area. <R> (a) Internal ROM (512 KB) 512 KB are allocated to addresses 00000000H to 0007FFFFH in the following versions. Accessing addresses 00080000H to 003FFFFFH is prohibited.
Page 94 CHAPTER 3 CPU FUNCTION (b) Internal ROM (768 KB) <R> 768 KB are allocated to addresses 00000000H to 000BFFFFH in the following versions. Accessing addresses 000C0000H to 003FFFFFH is prohibited. • μ PD70F3934 (V850E/SJ3-H), 70F3935 (V850E/SJ3-H), 70F3936 (V850E/SJ3-H) Figure 3-5. Internal ROM Area (768 KB) 0 0 3 F F F F F H Access-prohibited area...
Page 95 CHAPTER 3 CPU FUNCTION (d) Internal ROM (1280 KB) 1280 KB are allocated to addresses 00000000H to 0013FFFFH in the following versions. Accessing addresses 00140000H to 003FFFFFH is prohibited. • μ PD70F3474 (V850E/SJ3-H), 70F3475 (V850E/SJ3-H), 70F3476 (V850E/SJ3-H), 70F3486 (V850E/SK3-H), 70F3487 (V850E/SK3-H), 70F3488 (V850E/SK3-H) Figure 3-7.
Page 96 CHAPTER 3 CPU FUNCTION (2) Internal RAM area 60 KB are allocated to addresses 03FF0000H to 03FFEFFFH in the internal RAM area. Figure 3-9. Internal RAM Area (60 KB) Physical address space Logical address space 0 3 F F E F F F H F F F F E F F F H Internal (60 KB)
Page 97 CHAPTER 3 CPU FUNCTION (3) On-chip peripheral I/O area 4 KB of addresses 03FFF000H to 03FFFFFFH are reserved as the on-chip peripheral I/O area. Figure 3-10. On-Chip Peripheral I/O Area Physical address space Logical address space 0 3 F F F F F F H F F F F F F F F H On-chip peripheral I/O area (4 KB)
Page 98 CHAPTER 3 CPU FUNCTION (5) External memory area <R> Up to 30 MB (00400000H to 01FFFFFFH, 03E00000H to 03FEBFFFH) are allocated as the external memory area. For details, see CHAPTER 5 BUS CONTROL FUNCTION. (6) Expanded internal RAM area The 32 KB area from addresses 03FE4000H to 03FEBFFFH is reserved as an expanded internal RAM area. The expanded internal RAM area is accessed via the external bus interface.
Page 99 CHAPTER 3 CPU FUNCTION (b) Expanded internal RAM (32 KB) 32 KB are allocated to addresses 03FE4000H to 03FEBFFFH in the following versions. μ • PD70F3474 (V850E/SJ3-H), 70F3475 (V850E/SJ3-H), 70F3476 (V850E/SJ3-H), 70F3477 (V850E/SJ3-H), 70F3478 (V850E/SJ3-H), 70F3479 (V850E/SJ3-H), 70F3480 (V850E/SK3-H), 70F3481 (V850E/SK3-H), 70F3482 (V850E/SK3-H), 70F3486 (V850E/SK3-H), 70F3487 (V850E/SK3-H), 70F3488 (V850E/SK3-H) Figure 3-13.
Page 100 CHAPTER 3 CPU FUNCTION (d) Initial settings for expanded internal RAM The initial settings for the expanded internal RAM are shown below. Caution If the expanded internal RAM is used with any but the following initial settings, operation is not guaranteed. •...
Page 101 CHAPTER 3 CPU FUNCTION (7) Product selection register (PRDSEL) The PRDSEL register is a register to identify the product name and the internal RAM area. This register is used divided into two 16-bit registers, PRDSELH and PRDSELL. This register is read-only, in 16-bit units. After reset: Depends on product Address: PRDSELL FFFFFCC8H, PRDSELH FFFFFCCAH ×...
Page 102: Recommended Use Of Address Space
CHAPTER 3 CPU FUNCTION Table 3-3. Product Name Setting Examples (2/2) Product Name PRDSELL Register Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 μ <R>...
Page 103 CHAPTER 3 CPU FUNCTION (2) Data space With the V850E/SJ3-H and V850E/SK3-H, it seems that there are sixty-four 64 MB address spaces on the 4 GB CPU address space. Therefore, the least significant bit (bit 25) of a 26-bit address is sign-extended to 32 bits and allocated as an address.
Page 104 CHAPTER 3 CPU FUNCTION Figure 3-14. Recommended Memory Map (1/2) (a) When using expanded internal RAM Program space Data space F F F F F F F F H On-chip peripheral I/O F F F F F 0 0 0 H F F F F E F F F H Internal RAM F F F F 0 0 0 0 H...
Page 105 CHAPTER 3 CPU FUNCTION Figure 3-14. Recommended Memory Map (2/2) (b) When not using expanded internal RAM <R> Program space Data space F F F F F F F F H On-chip peripheral I/O F F F F F 0 0 0 H F F F F E F F F H Internal RAM F F F F 0 0 0 0 H...
Page 106: Peripheral I/O Registers
CHAPTER 3 CPU FUNCTION 3.4.6 Peripheral I/O registers (1/19) Address Function Register Name Symbol Manipulatable Bits Default Value √ Note 1 FFFFF004H Port DL register 0000H √ √ Note 1 FFFFF004H Port DLL register PDLL √ √ Note 1 FFFFF005H Port DLH register PDLH √...
Page 107 CHAPTER 3 CPU FUNCTION (2/19) Address Function Register Name Symbol Manipulatable Bits Default Value √ FFFFF094H DMA destination address register 2L DDA2L Undefined √ FFFFF096H DMA destination address register 2H DDA2H Undefined √ FFFFF098H DMA source address register 3L DSA3L Undefined √...
Page 108 CHAPTER 3 CPU FUNCTION (3/19) Address Function Register Name Symbol Manipulatable Bits Default Value √ √ FFFFF114H Interrupt control register PIC1 √ √ FFFFF116H Interrupt control register PIC2 √ √ FFFFF118H Interrupt control register PIC3 √ √ FFFFF11AH Interrupt control register PIC4 √...
Page 109 CHAPTER 3 CPU FUNCTION (4/19) Address Function Register Name Symbol Manipulatable Bits Default Value √ √ FFFFF168H Interrupt control register UA1TIC √ √ FFFFF16AH Interrupt control register UA2RIC √ √ FFFFF16CH Interrupt control register UA2TIC √ √ FFFFF16EH Interrupt control register ADIC √...
Page 110 CHAPTER 3 CPU FUNCTION (5/19) Address Function Register Name Symbol Manipulatable Bits Default Value √ √ FFFFF1BEH Interrupt control register PIC9 √ √ FFFFF1C0H Interrupt control register TP7IECIC √ √ FFFFF1C2H Interrupt control register TP8IECIC √ √ FFFFF1C4H Interrupt control register TM1EQIC0 √...
Page 111 CHAPTER 3 CPU FUNCTION (6/19) Address Function Register Name Symbol Manipulatable Bits Default Value √ FFFFF214H A/D conversion result register 2 ADA0CR2 Undefined √ FFFFF215H A/D conversion result register 2H ADA0CR2H Undefined √ FFFFF216H A/D conversion result register 3 ADA0CR3 Undefined √...
Page 112 CHAPTER 3 CPU FUNCTION (7/19) Address Function Register Name Symbol Manipulatable Bits Default Value √ √ FFFFF328H BRG3 prescaler mode register PRSM3 √ FFFFF329H BRG3 prescaler compare register PRSCM3 √ FFFFF340H IIC division clock select register 0 OCKS0 √ FFFFF344H IIC division clock select register 1 OCKS1 √...
Page 113 CHAPTER 3 CPU FUNCTION (8/19) Address Function Register Name Symbol Manipulatable Bits Default Value √ Note 1 FFFFF412H Port 9 register 0000H √ √ Note 1 FFFFF412H Port 9L register √ √ Note 1 FFFFF413H Port 9H register √ √ Note 2 Note 1 FFFFF41AH...
Page 114 CHAPTER 3 CPU FUNCTION (9/19) Address Function Register Name Symbol Manipulatable Bits Default Value √ √ Note FFFFF45EH Port 15 mode control register PMC15 √ √ FFFFF460H Port 0 function control register PFC0 √ FFFFF466H Port 3 function control register PFC3 0000H √...
Page 115 CHAPTER 3 CPU FUNCTION (10/19) Address Function Register Name Symbol Manipulatable Bits Default Value √ √ FFFFF5A3H TMP1 I/O control register 1 TP1IOC1 √ √ FFFFF5A4H TMP1 I/O control register 2 TP1IOC2 √ √ FFFFF5A5H TMP1 option register 0 TP1OPT0 √...
Page 116 CHAPTER 3 CPU FUNCTION (11/19) Address Function Register Name Symbol Manipulatable Bits Default Value √ √ FFFFF5F0H TMP6 control register 0 TP6CTL0 √ √ FFFFF5F1H TMP6 control register 1 TP6CTL1 √ √ FFFFF5F2H TMP6 I/O control register 0 TP6IOC0 √ √...
Page 117 CHAPTER 3 CPU FUNCTION (12/19) Address Function Register Name Symbol Manipulatable Bits Default Value √ FFFFF6C0H Oscillation stabilization time select register OSTS √ FFFFF6C1H PLL lockup time specification register PLLS √ FFFFF6D0H Watchdog timer mode register 2 WDTM2 √ FFFFF6D1H Watchdog timer enable register WDTE √...
Page 118 CHAPTER 3 CPU FUNCTION (13/19) Address Function Register Name Symbol Manipulatable Bits Default Value √ FFFFF848H Correction address register 2 CORAD2 00000000H √ FFFFF848H Correction address register 2L CORAD2L 0000H √ FFFFF84AH Correction address register 2H CORAD2H 0000H √ FFFFF84CH Correction address register 3 CORAD3 00000000H...
Page 119 CHAPTER 3 CPU FUNCTION (14/19) Address Function Register Name Symbol Manipulatable Bits Default Value √ Note 1 <R> FFFFF942H CSIE1 receive data buffer register CE1RX0 0000H √ Note 1 FFFFF942H CSIE1 receive data buffer register L CE1RX0L <R> √ Note 1 <R>...
Page 120 CHAPTER 3 CPU FUNCTION (15/19) Address Function Register Name Symbol Manipulatable Bits Default Value √ FFFFFA41H UARTA4 control register 1 UA4CTL1 √ FFFFFA42H UARTA4 control register 2 UA4CTL2 √ √ FFFFFA43H UARTA4 option control register 0 UA4OPT0 √ √ FFFFFA44H UARTA4 status register UA4STR √...
Page 121 CHAPTER 3 CPU FUNCTION (16/19) Address Function Register Name Symbol Manipulatable Bits Default Value √ FFFFFAD4H Hour count register RC1HOUR √ FFFFFAD5H Week count register RC1WEEK √ FFFFFAD6H Day count register RC1DAY √ FFFFFAD7H Month count register RC1MONTH √ FFFFFAD8H Year count register RC1YEAR √...
Page 122 CHAPTER 3 CPU FUNCTION (17/19) Address Function Register Name Symbol Manipulatable Bits Default Value √ FFFFFC6CH Port 6 function register 0000H √ √ FFFFFC6CH Port 6 function register L PF6L √ √ FFFFFC6DH Port 6 function register H PF6H √ √...
Page 123 CHAPTER 3 CPU FUNCTION (18/19) Address Function Register Name Symbol Manipulatable Bits Default Value √ FFFFFD36H CSIB3 transmit data register CB3TX 0000H √ FFFFFD36H CSIB3 transmit data register L CB3TXL √ √ FFFFFD40H CSIB4 control register 0 CB4CTL0 √ √ FFFFFD41H CSIB4 control register 1 CB4CTL1...
Page 124 CHAPTER 3 CPU FUNCTION (19/19) Address Function Register Name Symbol Manipulatable Bits Default Value √ √ FFFFFDB4H IIC clock select register 3 IICCL3 √ √ FFFFFDB5H IIC function expansion register 3 IICX3 √ √ FFFFFDB6H IIC status register 3 IICS3 √...
Page 125: Programmable Peripheral I/O Registers
CHAPTER 3 CPU FUNCTION 3.4.7 Programmable peripheral I/O registers The BPC register is used for programmable peripheral I/O register area selection. (1) Peripheral I/O area select control register (BPC) The BPC register can be read or written in 16-bit units. Reset sets this register to 0000H.
Page 126: Special Registers
CHAPTER 3 CPU FUNCTION 3.4.8 Special registers Special registers are registers that are protected from being written with illegal data due to a program hang-up. The V850E/SJ3-H and V850E/SK3-H have the following ten special registers. • Power save control register (PSC) •...
Page 127 CHAPTER 3 CPU FUNCTION (1) Setting data to special registers Set data to the special registers in the following sequence. <1> Disable DMA operation. <2> Prepare data to be set to the special register in a general-purpose register. <3> Write the data prepared in <2> to the PRCMD register. <4>...
Page 128 CHAPTER 3 CPU FUNCTION (2) Command register (PRCMD) The PRCMD register is an 8-bit register that protects the registers that may seriously affect the application system from being written, so that the system does not inadvertently stop due to a program hang-up. The first write access to a special register is valid after data has been written in advance to the PRCMD register.
Page 129 CHAPTER 3 CPU FUNCTION (3) System status register (SYS) Status flags that indicate the operation status of the overall system are allocated to this register. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H Address: FFFFF802H <...
Page 130: Cautions
CHAPTER 3 CPU FUNCTION 3.4.9 Cautions (1) Registers to be set first Be sure to set the following registers first when using the V850E/SJ3-H and V850E/SK3-H. • System wait control register (VSWC) • On-chip debug mode register (OCDM) • Watchdog timer mode register 2 (WDTM2) •...
Page 131 CHAPTER 3 CPU FUNCTION (d) Registers related to expanded internal RAM The expanded internal RAM is accessed via the external bus interface. Before accessing the expanded internal RAM, be sure to set the registers related to the external bus interface (initial settings for the expanded internal RAM).
Page 132 CHAPTER 3 CPU FUNCTION (1/2) Peripheral Function Register Name Access 16-bit timer/event counter P (TMP) TPnCNT Read 1 or 2 (n = 0 to 8) • 1st access: No wait TPnCCR0, TPnCCR1 Write • Continuous write: 0 to 3 Read 1 or 2 16-bit timer/event counter Q (TMQ) TQ0CNT...
Page 133 CHAPTER 3 CPU FUNCTION (2/2) Peripheral Function Register Name Access Note 1 Note 1 Note 2 CAN controller CnGMABT Read/write + 1)/(2 + j) (MIN.) CANMOD (2 × f Note 1 Note 2 (n = 0, 1, m = 0 to 31, a = 1 CnGMABTD + 1)/(2 + j) (MAX.) CANMOD...
Page 134 CHAPTER 3 CPU FUNCTION (3) Restriction on conflict between sld instruction and interrupt request (a) Description If a conflict occurs between the decode operation of an instruction in <2> immediately before the sld instruction following an instruction in <1> and an interrupt request before the instruction in <1> is complete, the execution result of the instruction in <1>...
Page 135: Chapter 4 Port Functions
CHAPTER 4 PORT FUNCTIONS Features 4.1.1 V850E/SJ3-H I/O ports: 128 • 5 V tolerant/N-ch open-drain output switchable: 60 (ports 0, 3 to 6, 8, 9) Input/output specifiable in 1-bit units 4.1.2 V850E/SK3-H I/O ports: 156 • 5 V tolerant/N-ch open-drain output switchable: 78 (ports 0, 2 to 6, 8, 9, 15) Input/output specifiable in 1-bit units User’s Manual U19201EJ3V0UD...
Page 136: Basic Port Configuration
CHAPTER 4 PORT FUNCTIONS Basic Port Configuration 4.2.1 V850E/SJ3-H The V850E/SJ3-H features a total of 128 I/O ports consisting of ports 0, 1, 3 to 9, CD, CM, CS, CT, DH, and DL. The port configuration is shown below. Figure 4-1. Port Configuration Diagram PCD0 Port 0 Port CD...
Page 137: V850E/Sk3-H
CHAPTER 4 PORT FUNCTIONS 4.2.2 V850E/SK3-H The V850E/SK3-H features a total of 156 I/O ports consisting of ports 0 to 9, 13 to 15, CD, CM, CS, CT, DH, and The port configuration is shown below. Figure 4-2. Port Configuration Diagram P130 Port 0 Port 13...
Page 138: Port Configuration
CHAPTER 4 PORT FUNCTIONS Port Configuration Table 4-3. Port Configuration (V850E/SJ3-H) Item Configuration Control register Port n mode register (PMn: n = 0, 1, 3 to 9, CD, CM, CS, CT, DH, DL) Port n mode control register (PMCn: n = 0, 3 to 6, 8, 9, CD, CM, CS, CT, DH, DL) Port n function control register (PFCn: n = 0, 3 to 6, 8, 9, CD) <R>...
Page 139 CHAPTER 4 PORT FUNCTIONS (2) Port n mode register (PMn) The PMn register specifies the input or output mode of the corresponding port pin. Each bit of this register corresponds to one pin of port n, and the input or output mode can be specified in 1-bit units.
Page 140 CHAPTER 4 PORT FUNCTIONS (4) Port n function control register (PFCn) The PFCn register specifies the alternate function of a port pin to be used if the pin has two alternate functions. Each bit of this register corresponds to one pin of port n, and the alternate function of a port pin can be specified in 1-bit units.
Page 141 CHAPTER 4 PORT FUNCTIONS (6) Port n function register (PFn) The PFn register specifies normal output or N-ch open-drain output. Each bit of this register corresponds to one pin of port n, and the output mode of the port pin can be specified in 1-bit units.
Page 142 CHAPTER 4 PORT FUNCTIONS (7) Port setting Set a port as illustrated below. Figure 4-3. Setting of Each Register and Pin Function Port mode Output mode “0” PMn register Input mode “1” Alternate function (when two alternate functions are available) “0”...
Page 143: Port 0
CHAPTER 4 PORT FUNCTIONS 4.3.1 Port 0 Port 0 is a 7-bit port for which I/O settings can be controlled in 1-bit units. Port 0 includes the following alternate-function pins. Table 4-6. Port 0 Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name Remark Block Type...
Page 144 CHAPTER 4 PORT FUNCTIONS (2) Port 0 mode register (PM0) After reset: FFH Address: FFFFF420H PM06 PM05 PM04 PM03 PM02 PM01 PM00 PM0n I/O mode control (n = 0 to 6) Output mode Input mode (3) Port 0 mode control register (PMC0) After reset: 00H Address: FFFFF440H PMC0...
Page 145 CHAPTER 4 PORT FUNCTIONS (4) Port 0 function control register (PFC0) After reset: 00H Address: FFFFF460H PFC0 PFC03 PFC01 PFC00 Remark For details of alternate function specification, see 4.3.1 (6) Port 0 alternate function specifications. μ <R> (5) Port 0 function control expansion register (PFCE0) (Not included in the PD70F3931 (V850E/SJ3-H), 70F3932 (V850E/SJ3-H), and 70F3933 (V850E/SJ3-H).) After reset: 00H...
Page 146 CHAPTER 4 PORT FUNCTIONS (7) Port 0 function register (PF0) After reset: 00H Address: FFFFFC60H PF06 PF05 PF04 PF03 PF02 PF01 PF00 PF0n Control of normal output or N-ch open-drain output (n = 0 to 6) Normal output (CMOS output) N-ch open drain output Caution To pull up an output pin at EV or higher, be sure to set the appropriate PF0n bit to 1.
Page 147: Port 1
CHAPTER 4 PORT FUNCTIONS 4.3.2 Port 1 Port 1 is a 2-bit port for which I/O settings can be controlled in 1-bit units. Port 1 includes the following alternate-function pins. Table 4-7. Port 1 Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name Remark Block Type...
Page 148: Port 2 (V850E/Sk3-H Only)
CHAPTER 4 PORT FUNCTIONS 4.3.3 Port 2 (V850E/SK3-H only) Port 2 is a 2-bit port for which I/O settings can be controlled in 1-bit units. Port 2 includes the following alternate-function pins. Table 4-8. Port 2 Alternate-Function Pins Pin Name Pin No.
Page 149 CHAPTER 4 PORT FUNCTIONS (3) Port 2 mode control register (PMC2) After reset: 00H Address: FFFFF444H PMC2 PMC21 PMC20 PMC21 Specification of P21 pin operation mode I/O port SCL04 I/O PMC20 Specification of P20 pin operation mode I/O port SDA04 I/O (4) Port 2 function register (PF2) After reset: 00H Address: FFFFFC64H...
Page 150: Port 3
CHAPTER 4 PORT FUNCTIONS 4.3.4 Port 3 Port 3 is a 10-bit (V850E/SJ3-H) or 13-bit (V850E/SK3-H) port for which I/O settings can be controlled in 1-bit units. Port 3 includes the following alternate-function pins. Table 4-9. Port 3 Alternate-Function Pins Pin Name Pin No.
Page 151 CHAPTER 4 PORT FUNCTIONS (1) Port 3 register (P3) After reset: 0000H (output latch) Address: P3 FFFFF406H, P3L FFFFF406H, P3H FFFFF407H P3 (P3H) Note Note Note P312 P311 P310 (P3L) Output data control (in output mode) Outputs 0. Outputs 1. Note Valid for the V850E/SK3-H only.
Page 152 CHAPTER 4 PORT FUNCTIONS (2) Port 3 mode register (PM3) After reset: FFFFH Address: PM3 FFFFF426H, PM3L FFFFF426H, PM3H FFFFF427H PM3 (PM3H) Note Note Note PM312 PM311 PM310 PM39 PM38 (PM3L) PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 PM3n I/O mode control Output mode Input mode...
Page 153 CHAPTER 4 PORT FUNCTIONS (3) Port 3 mode control register (PMC3) (1/2) After reset: 0000H Address: PMC3 FFFFF446H, PMC3L FFFFF446H, PMC3H FFFFF447H PMC3 (PMC3H) Note 1 Note 1 Note 1 PMC312 PMC311 PMC310 PMC39 PMC38 (PMC3L) PMC37 PMC36 PMC35 PMC34 PMC33 PMC32 PMC31...
Page 154 CHAPTER 4 PORT FUNCTIONS (2/2) PMC34 Specification of P34 pin operation mode I/O port Note TIP10 input/TOP10 output/CRXD1 input PMC33 Specification of P33 pin operation mode I/O port Note TIP01 input/TOP01 output/CTXD1 output PMC32 Specification of P32 pin operation mode I/O port ASCKA0 input/SCKB4 I/O/TIP00 input/TOP00 output PMC31...
Page 155 CHAPTER 4 PORT FUNCTIONS (4) Port 3 function control register (PFC3) After reset: 0000H Address: PFC3 FFFFF466H, PFC3L FFFFF466H, PFC3L FFFFF467H PFC3 (PFC3H) Note PFC310 PFC39 PFC38 (PFC3L) PFC37 PFC36 PFC35 PFC34 PFC33 PFC32 PFC31 PFC30 Note Valid for the V850E/SK3-H only. Be sure to clear this bit to 0 in the V850E/SJ3-H.
Page 156 CHAPTER 4 PORT FUNCTIONS (6) Port 3 alternate function specifications PFCE310 PFC310 Specification of P310 pin alternate function Note 1 SOB2 output Other than above Setting prohibited PFCE39 PFC39 Specification of P39 pin alternate function RXDA2 input SCL00 I/O SCKB2 I/O Setting prohibited PFCE38 PFC38...
Page 157 CHAPTER 4 PORT FUNCTIONS PFCE34 PFC34 Specification of P34 pin alternate function TIP10 input TOP10 output Note 1 CRXD1 input Setting prohibited PFCE33 PFC33 Specification of P33 pin alternate function TIP01 input TOP01 output Note 1 CTXD1 output Setting prohibited PFCE32 PFC32 Specification of P32 pin alternate function...
Page 158 CHAPTER 4 PORT FUNCTIONS (7) Port 3 function register (PF3) After reset: 0000H Address: PF3 FFFFFC66H, PF3L FFFFFC66H, PF3H FFFFFC67H Note Note Note PF3 (PF3H) PF312 PF311 PF310 PF39 PF38 (PF3L) PF37 PF36 PF35 PF34 PF33 PF32 PF31 PF30 PF3n Control of normal output or N-ch open-drain output Normal output (CMOS output) N-ch open-drain output...
Page 159: Port 4
CHAPTER 4 PORT FUNCTIONS 4.3.5 Port 4 Port 4 is a 3-bit (V850E/SJ3-H) or 6-bit (V850E/SK3-H) port that controls I/O in 1-bit units. Port 4 includes the following alternate-function pins. Table 4-10. Port 4 Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name Remark Block Type...
Page 160 CHAPTER 4 PORT FUNCTIONS (1) Port 4 register (P4) After reset: 00H (output latch) Address: FFFFF408H Note Note Note Output data control (in output mode) Outputs 0. Outputs 1. Note Valid for the V850E/SK3-H only. Be sure to clear this bit to 0 in the V850E/SJ3-H. However, the read value becomes undefined. Caution Be sure to clear bits 6 and 7 to “0”.
Page 161 CHAPTER 4 PORT FUNCTIONS (3) Port 4 mode control register (PMC4) After reset: 00H Address: FFFFF448H Note 1 Note 1 PMC4 PMC45 PMC44 PMC42 PMC41 PMC40 Note 1 PMC45 Specification of P45 pin operation mode I/O port Note 2 IERX0 input Note 1 PMC44...
Page 162 CHAPTER 4 PORT FUNCTIONS (4) Port 4 function control register (PFC4) After reset: 00H Address: FFFFF468H PFC4 PFC42 PFC41 PFC40 PFC42 Specification of P42 pin alternate function SCKB0 I/O INTP2 input PFC41 Specification of P41 pin alternate function SOB0 output SCL01 I/O PFC40 Specification of P40 pin alternate function...
Page 163: Port 5
CHAPTER 4 PORT FUNCTIONS 4.3.6 Port 5 Port 5 is a 6-bit (V850E/SJ3-H) or 8-bit (V850E/SK3-H) port that controls I/O in 1-bit units. Port 5 includes the following alternate-function pins. Table 4-11. Port 5 Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name Remark Block Type...
Page 164 CHAPTER 4 PORT FUNCTIONS (1) Port 5 register (P5) After reset: 00H (output latch) Address: FFFFF40AH Note Note Output data control (in output mode) Outputs 0. Outputs 1. Note Valid for the V850E/SK3-H only. Be sure to clear this bit to 0 in the V850E/SJ3-H. However, the read value becomes undefined. Remark V850E/SJ3-H: n = 0 to 5 V850E/SK3-H: n = 0 to 7...
Page 165 CHAPTER 4 PORT FUNCTIONS (3) Port 5 mode control register (PMC5) After reset: 00H Address: FFFFF44AH Note 1 Note 1 PMC5 PMC57 PMC56 PMC55 PMC54 PMC53 PMC52 PMC51 PMC50 Note 1 PMC57 Specification of P57 pin operation mode I/O port Note 2 TXDA4 output...
Page 166 CHAPTER 4 PORT FUNCTIONS (4) Port 5 function control register (PFC5) After reset: 00H Address: FFFFF46AH PFC5 PFC55 PFC54 PFC53 PFC52 PFC51 PFC50 Remark For details of alternate function specification, see 4.3.6 (6) Port 5 alternate function specifications. (5) Port 5 function control expansion register (PFCE5) After reset: 00H Address: FFFFF70AH PFCE5...
Page 167 CHAPTER 4 PORT FUNCTIONS PFCE53 PFC53 Specification of P53 pin alternate function SIB2 input Note input/TIQ00 input TOQ00 output RTP03 output PFCE52 PFC52 Specification of P52 pin alternate function Setting prohibited Note input/TIQ03 input TOQ03 input RTP02 output PFCE51 PFC51 Specification of P51 pin alternate function INTP7 input Note...
Page 168 CHAPTER 4 PORT FUNCTIONS (7) Port 5 function register (PF5) After reset: 00H Address: FFFFFC6AH Note Note PF57 PF56 PF55 PF54 PF53 PF52 PF51 PF50 PF5n Control of normal output or N-ch open-drain output Normal output (CMOS output) N-ch open-drain output Note Valid for the V850E/SK3-H only.
Page 169: Port 6
CHAPTER 4 PORT FUNCTIONS 4.3.7 Port 6 Port 6 is a 16-bit port for which I/O settings can be controlled in 1-bit units. Port 6 includes the following alternate-function pins. Table 4-12. Port 6 Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name Remark Block Type...
Page 170 CHAPTER 4 PORT FUNCTIONS (1) Port 6 register (P6) After reset: 0000H (output latch) Address: P6 FFFFF40CH P6L FFFFF40CH, P6LH FFFFF40DH P6 (P6H) P615 P614 P613 P612 P611 P610 (P6L) Output data control (in output mode) (n = 0 to 15) Outputs 0.
Page 171 CHAPTER 4 PORT FUNCTIONS (3) Port 6 mode control register (PMC6) (1/2) After reset: 0000H Address: PMC6 FFFFF44CH PMC6L FFFFF44CH, PMC6H FFFFF44DH PMC6 (PMC6H) PMC615 PMC614 PMC613 PMC612 PMC611 PMC610 PMC69 PMC68 PMC67 PMC66 PMC65 PMC64 PMC63 PMC62 PMC61 PMC60 (PMC6L) PMC615 Specification of P615 pin operation mode...
Page 172 CHAPTER 4 PORT FUNCTIONS (2/2) PMC64 Specification of P64 pin operation mode I/O port <R> Note RTP14 output/SOE1 output/KR5 input PMC63 Specification of P63 pin operation mode I/O port <R> Note RTP13 output/SIE1 input/KR4 input PMC62 Specification of P62 pin operation mode I/O port Note <R>...
Page 173 CHAPTER 4 PORT FUNCTIONS (4) Port 6 function control register (PFC6) After reset: 0000H Address: PFC6 FFFFF46CH, PFC6L FFFFF46CH, PFC6H FFFFF46DH PFC6 (PFC6H) PFC614 PFC613 PFC612 PFC611 PFC610 PFC69 PFC68 Note <R> (PFC6L) PFC67 PFC66 PFC65 PFC64 PFC63 PFC62 PFC61 PFC60 μ...
Page 174 CHAPTER 4 PORT FUNCTIONS (6) Port 6 alternate function specifications PFCE614 PFC614 Specification of P614 pin alternate function SDA03 I/O Setting prohibited TECR8 input Setting prohibited PFCE613 PFC613 Specification of P613 pin alternate function TIP81 input TOP81 output TENC81 input Setting prohibited PFCE612 PFC612...
Page 175 CHAPTER 4 PORT FUNCTIONS Note 1 <R> PFCE67 PFC67 Specification of P67 pin alternate function SOB5 output RXDA5 input <R> Note 2 SDA05 Setting prohibited PFCE66 PFC66 Specification of P66 pin alternate function SIB5 input INTP9 input Note 3 input/TIQ00 input TOQ00 output PFCE65 PFC65...
Page 176 CHAPTER 4 PORT FUNCTIONS Note 1 <R> PFCE60 PFC60 Specification of P60 pin alternate function RTP10 output RXDA4 input Note 2 <R> SIE0 input Setting prohibited μ Notes 1. Valid for other than the PD70F3931 (V850E/SJ3-H), 70F3932 (V850E/SJ3-H), and 70F3933 <R>...
Page 177: Port 7
CHAPTER 4 PORT FUNCTIONS 4.3.8 Port 7 Port 7 is a 16-bit port for which I/O settings can be controlled in 1-bit units. Port 7 includes the following alternate-function pins. Table 4-13. Port 7 Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name Remark Block Type...
Page 178 CHAPTER 4 PORT FUNCTIONS (1) Port 7 register H, port 7 register L (P7H, P7L) After reset: 00H (output latch) Address: P7L FFFFF40EH, P7H FFFFF40FH P715 P714 P713 P712 P711 P710 Output data control (in output mode) (n = 0 to 15) Outputs 0.
Page 179: Port 8
CHAPTER 4 PORT FUNCTIONS 4.3.9 Port 8 Port 8 is a 2-bit (V850E/SJ3-H) or 6-bit (V850E/SK3-H) port for which I/O settings can be controlled in 1-bit units. Port 8 includes the following alternate-function pins. Table 4-14. Port 8 Alternate-Function Pins Pin Name Pin No.
Page 180 CHAPTER 4 PORT FUNCTIONS (2) Port 8 mode register (PM8) After reset: FFH Address: FFFFF430H Note Note Note Note PM85 PM84 PM83 PM82 PM81 PM80 PM8n I/O mode control Output mode Input mode Note Valid for the V850E/SK3-H only. Be sure to set this bit to 1 in the V850E/SJ3-H. Caution Be sure to set bits 6 and 7 to “1”.
Page 181 CHAPTER 4 PORT FUNCTIONS (3) Port 8 mode control register (PMC8) After reset: 00H Address: FFFFF450H Note 1 Note 1 Note 1 Note 1 PMC8 PMC85 PMC84 PMC83 PMC82 PMC81 PMC80 Note 1 PMC85 Specification of P85 pin operation mode I/O port Note 2 TXDA5...
Page 182 CHAPTER 4 PORT FUNCTIONS (4) Port 8 function control register (PFC8) After reset: 00H Address: FFFFF470H PFC8 PFC81 PFC80 Remark For details of alternate function specification, see 4.3.9 (6) Port 8 alternate function specifications. (5) Port 8 function control expansion register (PFCE8) After reset: 00H Address: FFFFF710H PFCE8...
Page 183 CHAPTER 4 PORT FUNCTIONS (7) Port 8 function register (PF8) After reset: 00H Address: FFFFFC70H Note Note Note Note PF85 PF84 PF83 PF82 PF81 PF80 PF8n Control of normal output or N-ch open-drain output Normal output (CMOS output) N-ch open-drain output Note Valid for the V850E/SK3-H only.
Page 184: Port 9
CHAPTER 4 PORT FUNCTIONS 4.3.10 Port 9 Port 9 is a 16-bit port for which I/O settings can be controlled in 1-bit units. Port 9 includes the following alternate-function pins. Table 4-15. Port 9 Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name Remark Block Type...
Page 185 CHAPTER 4 PORT FUNCTIONS (1) Port 9 register (P9) After reset: 0000H (output latch) Address: P9 FFFFF412H, P9L FFFFF412H, P9H FFFFF413H P9 (P9H) P915 P914 P913 P912 P911 P910 (P9L) Output data control (in output mode) (n = 0 to 15) Outputs 0.
Page 186 CHAPTER 4 PORT FUNCTIONS (3) Port 9 mode control register (PMC9) (1/2) After reset: 0000H Address: PMC9 FFFFF452H, PMC9L FFFFF452H, PMC9H FFFFF453H PMC9 (PMC9H) PMC915 PMC914 PMC913 PMC912 PMC911 PMC910 PMC99 PMC98 (PMC9L) PMC97 PMC96 PMC95 PMC94 PMC93 PMC92 PMC91 PMC90 PMC915 Specification of P915 pin operation mode...
Page 187 CHAPTER 4 PORT FUNCTIONS (2/2) PMC98 Specification of P98 pin operation mode I/O port A8 output/SOB1 output PMC97 Specification of P97 pin operation mode I/O port A7 output/SIB1 input/TIP20 input/TOP20 output PMC96 Specification of P96 pin operation mode I/O port A6 output/TIP21 input/TOP21 output PMC95 Specification of P95 pin operation mode...
Page 188 CHAPTER 4 PORT FUNCTIONS (4) Port 9 function control register (PFC9) Caution Port 9 pins cannot be used as port pins or other alternate-function pins if even one of the A0 to A15 pins is used in the separate bus mode. After setting the PFC9 and PFCE9 registers to 0000H, therefore, set all 16 bits of the PMC9 register to FFFFH at once.
Page 189 CHAPTER 4 PORT FUNCTIONS (6) Port 9 alternate function specifications PFCE915 PFC915 Specification of P915 pin alternate function A15 output INTP6 input TIP50 input TOP50 output PFCE914 PFC914 Specification of P914 pin alternate function A14 output INTP5 input TIP51 input TOP51 output PFC913 Specification of P913 pin alternate function...
Page 190 CHAPTER 4 PORT FUNCTIONS PFCE96 PFC96 Specification of P96 pin alternate function A6 output Setting prohibited TIP21 input TOP21 output PFCE95 PFC95 Specification of P95 pin alternate function A5 output TIP30 input TOP30 output INTP5 input PFCE94 PFC94 Specification of P94 pin alternate function A4 output TIP31 input TOP31 output...
Page 191 CHAPTER 4 PORT FUNCTIONS (7) Port 9 function register (PF9) After reset: 0000H Address: PF3 FFFFFC72H, PF9L FFFFFC72H, PF9H FFFFFC73H PF9 (PF9H) PF915 PF914 PF913 PF912 PF911 PF910 PF99 PF98 (PF9L) PF97 PF96 PF95 PF94 PF93 PF92 PF91 PF90 PF9n Control of normal output or N-ch open-drain output (n = 0 to 15) Normal output (CMOS output) N-ch open-drain output...
Page 192: Port 13 (V850E/Sk3-H Only)
CHAPTER 4 PORT FUNCTIONS 4.3.11 Port 13 (V850E/SK3-H only) Port 13 is a 4-bit port for which I/O settings can be controlled in 1-bit units. Port 13 includes the following alternate-function pins. Table 4-16. Port 13 Alternate-Function Pins Pin Name Pin No.
Page 193: Port 14 (V850E/Sk3-H Only)
CHAPTER 4 PORT FUNCTIONS 4.3.12 Port 14 (V850E/SK3-H only) Port 14 is a 6-bit port for which I/O settings can be controlled in 1-bit units. Port 14 includes the following alternate-function pins. Table 4-17. Port 14 Alternate-Function Pins Pin Name Pin No.
Page 194: Port 15 (V850E/Sk3-H Only)
CHAPTER 4 PORT FUNCTIONS 4.3.13 Port 15 (V850E/SK3-H only) Port 15 is a 6-bit port for which I/O settings can be controlled in 1-bit units. Port 15 includes the following alternate-function pins. Table 4-18. Port 15 Alternate-Function Pins Pin Name Pin No.
Page 195 CHAPTER 4 PORT FUNCTIONS (3) Port 15 mode control register (PMC15) After reset: 00H Address: FFFFF45EH PMC15 PMC153 PMC152 PMC151 PMC150 PMC153 Specification of P153 pin operation mode I/O port INTP6 input PMC152 Specification of P152 pin operation mode I/O port INTP9 input PMC151 Specification of P151 pin operation mode...
Page 196: Port Cd
CHAPTER 4 PORT FUNCTIONS 4.3.14 Port CD Port CD is a 4-bit port for which I/O settings can be controlled in 1-bit units. Port CD includes the following alternate-function pins. Table 4-19. Port CD Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name Remark Block Type...
Page 197 CHAPTER 4 PORT FUNCTIONS (3) Port CD mode control register (PMCCD) After reset: 00H Address: FFFFF04EH PMCCD PMCCD3 PMCCD2 PMCCD1 PMCCD0 PMCCD3 Specification of PCD3 pin operation mode I/O port TXDB1 output PMCCD2 Specification of PCD2 pin operation mode I/O port RXDB1 input PMCCD1 Specification of PCD1 pin operation mode...
Page 198: Port Cm
CHAPTER 4 PORT FUNCTIONS 4.3.15 Port CM Port CM is a 6-bit port for which I/O settings can be controlled in 1-bit units. Port CM includes the following alternate-function pins. Table 4-20. Port CM Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name Remark Block Type...
Page 199 CHAPTER 4 PORT FUNCTIONS (3) Port CM mode control register (PMCCM) After reset: 00H Address: FFFFF04CH PMCCM PMCCM3 PMCCM2 PMCCM1 PMCCM0 PMCCM3 Specification of PCM3 pin operation mode I/O port HLDRQ input PMCCM2 Specification of PCM2 pin operation mode I/O port HLDAK output PMCCM1 Specification of PCM1 pin operation mode...
Page 200: Port Cs
CHAPTER 4 PORT FUNCTIONS 4.3.16 Port CS Port CS is an 8-bit port for which I/O settings can be controlled in 1-bit units. Port CS includes the following alternate-function pins. Table 4-21. Port CS Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name Remark Block Type...
Page 201 CHAPTER 4 PORT FUNCTIONS (3) Port CS mode control register (PMCCS) After reset: 00H Address: FFFFF048H PMCCS PMCCS3 PMCCS2 PMCCS1 PMCCS3 Specification of PCS3 pin operation mode I/O port CS3 output PMCCS2 Specification of PCS2 pin operation mode I/O port CS2 output PMCCS1 Specification of PCS1 pin operation mode...
Page 202: Port Ct
CHAPTER 4 PORT FUNCTIONS 4.3.17 Port CT Port CT is an 8-bit port for which I/O settings can be controlled in 1-bit units. Port CT includes the following alternate-function pins. Table 4-22. Port CT Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name Remark Block Type...
Page 203 CHAPTER 4 PORT FUNCTIONS (3) Port CT mode control register (PMCCT) After reset: 00H Address: FFFFF04AH PMCCT PMCCT6 PMCCT4 PMCCT1 PMCCT0 PMCCT6 Specification of PCT6 pin operation mode I/O port ASTB output PMCCT4 Specification of PCT4 pin operation mode I/O port RD output PMCCT1 Specification of PCT1 pin operation mode...
Page 204: Port Dh
CHAPTER 4 PORT FUNCTIONS 4.3.18 Port DH Port DH is an 8-bit port for which I/O settings can be controlled in 1-bit units. Port DH includes the following alternate-function pins. Table 4-23. Port DH Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name Remark Block Type...
Page 205 CHAPTER 4 PORT FUNCTIONS (3) Port DH mode control register (PMCDH) After reset: 00H Address: FFFFF046H PMCDH PMCDH7 PMCDH6 PMCDH5 PMCDH4 PMCDH3 PMCDH2 PMCDH1 PMCDH0 PMCDHn Specification of PDHn pin operation mode (n = 0 to 7) I/O port Am output (address bus output) (m = 16 to 23) User’s Manual U19201EJ3V0UD...
Page 206: Port Dl
CHAPTER 4 PORT FUNCTIONS 4.3.19 Port DL Port DL is a 16-bit port for which I/O settings can be controlled in 1-bit units. Port DL includes the following alternate-function pins. Table 4-24. Port DL Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name Remark Block Type...
Page 207 CHAPTER 4 PORT FUNCTIONS (1) Port DL register (PDL) After reset: 0000H (output latch) Address: PDL FFFFF004H, PDLL FFFFF004H, PDLH FFFFF005H PDL (PDLH) PDL15 PDL14 PDL13 PDL12 PDL11 PDL10 PDL9 PDL8 (PDLL) PDL7 PDL6 PDL5 PDL4 PDL3 PDL2 PDL1 PDL0 PDLn Output data control (in output mode) (n = 0 to 15) Outputs 0.
Page 208 CHAPTER 4 PORT FUNCTIONS (3) Port DL mode control register (PMCDL) After reset: 0000H Address: PMCDL FFFFF044H, PMCDLL FFFFF044H, PMCDLH FFFFF045H PMCDL (PMCDLH) PMCDL15 PMCDL14PMCDL13 PMCDL12 PMCDL11PMCDL10 PMCDL9 PMCDL8 (PMCDLL) PMCDL7 PMCDL6 PMCDL5 PMCDL4 PMCDL3 PMCDL2 PMCDL1 PMCDL0 PMCDLn Specification of PDLn pin operation mode (n = 0 to 15) I/O port ADn I/O (address/data bus I/O) Caution When the EXIMC.SMSEL bit = 1 (separate mode) and the BSC.BS30 to BSC.BS00 bits...
Page 209: Block Diagrams
CHAPTER 4 PORT FUNCTIONS Block Diagrams Figure 4-4. Block Diagram of Type A-1 PMmn PORT Address P-ch A/D input signal N-ch User’s Manual U19201EJ3V0UD...
Page 210 CHAPTER 4 PORT FUNCTIONS Figure 4-5. Block Diagram of Type A-2 PMmn PORT Address P-ch D/A input signal N-ch Figure 4-6. Block Diagram of Type B-1 PMmn PORT Address User’s Manual U19201EJ3V0UD...
Page 211 CHAPTER 4 PORT FUNCTIONS Figure 4-7. Block Diagram of Type C-1 PFmn PMmn PORT P-ch N-ch Note Address Note Hysteresis characteristics are not available in port mode. User’s Manual U19201EJ3V0UD...
Page 212 CHAPTER 4 PORT FUNCTIONS Figure 4-8. Block Diagram of Type D-1 PMCmn PMmn PORT Address Input signal when alternate function is used User’s Manual U19201EJ3V0UD...
Page 213 CHAPTER 4 PORT FUNCTIONS Figure 4-9. Block Diagram of Type D-2 PMCmn PMmn Output signal when alternate function is used PORT Address User’s Manual U19201EJ3V0UD...
Page 214 CHAPTER 4 PORT FUNCTIONS Figure 4-10. Block Diagram of Type D-3 PMCmn Output enable signal of address/data bus Output buffer off signal PMmn Output signal when alternate function is used PORT Address Input enable signal of address/data bus Input signal when alternate function is used User’s Manual U19201EJ3V0UD...
Page 215 CHAPTER 4 PORT FUNCTIONS Figure 4-11. Block Diagram of Type E-1 PFmn PMCmn PMmn PORT P-ch N-ch Note Address Input signal when alternate function is used Note Hysteresis characteristics are not available in port mode. User’s Manual U19201EJ3V0UD...
Page 216 CHAPTER 4 PORT FUNCTIONS Figure 4-12. Block Diagram of Type E-2 PFmn PMCmn PMmn Output signal when alternate function is used PORT P-ch N-ch Address User’s Manual U19201EJ3V0UD...
Page 217 CHAPTER 4 PORT FUNCTIONS Figure 4-13. Block Diagram of Type E-3 PFmn PMCmn PMmn Output signal when alternate function is used P-ch PORT N-ch Note Address Input signal when alternate function is used Note Hysteresis characteristics are not available in port mode. User’s Manual U19201EJ3V0UD...
Page 218 CHAPTER 4 PORT FUNCTIONS Figure 4-14. Block Diagram of Type E-4 PFmn PMCmn PMmn PORT P-ch N-ch Note Address Input signal 1-1 when Noise alternate function is used elimination Input signal 1-2 when alternate function is used Note Hysteresis characteristics are not available in port mode. User’s Manual U19201EJ3V0UD...
Page 219 CHAPTER 4 PORT FUNCTIONS Figure 4-15. Block Diagram of Type F-1 PFCmn PMCmn PMmn PORT P-ch N-ch Note Address Input signal when alternate function is used Note Hysteresis characteristics are not available in port mode. User’s Manual U19201EJ3V0UD...
Page 220 CHAPTER 4 PORT FUNCTIONS Figure 4-16. Block Diagram of Type F-2 PFCmn PMCmn PMmn Output signal when alternate function is used PORT P-ch N-ch Address User’s Manual U19201EJ3V0UD...
Page 221 CHAPTER 4 PORT FUNCTIONS Figure 4-17. Block Diagram of Type G-1 PFmn PFCmn PMCmn PMmn Output signal when alternate function is used PORT P-ch N-ch Note Address Input signal when alternate function is used Note Hysteresis characteristics are not available in port mode. User’s Manual U19201EJ3V0UD...
Page 222 CHAPTER 4 PORT FUNCTIONS Figure 4-18. Block Diagram of Type G-2 PFmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used P-ch PORT N-ch Address User’s Manual U19201EJ3V0UD...
Page 223 CHAPTER 4 PORT FUNCTIONS Figure 4-19. Block Diagram of Type G-3 PFmn PFCmn PMCmn PMmn PORT P-ch N-ch Note Address Input signal 1 when alternate function is used Input signal 2 when alternate function is used Note Hysteresis characteristics are not available in port mode. User’s Manual U19201EJ3V0UD...
Page 224 CHAPTER 4 PORT FUNCTIONS Figure 4-20. Block Diagram of Type G-4 PFmn Output signal when alternate function is used PFCmn PMCmn PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used P-ch PORT N-ch Note Address...
Page 225 CHAPTER 4 PORT FUNCTIONS Figure 4-21. Block Diagram of Type G-5 PFmn PFCmn PMCmn PMmn Output signal when alternate function is used P-ch PORT N-ch Note Address Input signal 1 when alternate function is used Input signal 2 when alternate function is used Note Hysteresis characteristics are not available in port mode.
Page 226 CHAPTER 4 PORT FUNCTIONS Figure 4-22. Block Diagram of Type G-6 PFmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used P-ch PORT N-ch Note Address Input signal when alternate function is used Note Hysteresis characteristics are not available in port mode.
Page 227 CHAPTER 4 PORT FUNCTIONS <R> Figure 4-23. Block Diagram of Type G-7 PFmn Output enable signal when alternate function is used PFCmn PMCmn PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used P-ch PORT N-ch...
Page 228 CHAPTER 4 PORT FUNCTIONS Figure 4-24. Block Diagram of Type L-1 PFmn INTR Note 1 INTRmn INTF Note 1 INTFmn PMCmn PMmn PORT P-ch N-ch Note 2 Address Input signal 1 when Edge Noise detection elimination alternate function is used Notes 1.
Page 229 CHAPTER 4 PORT FUNCTIONS Figure 4-25. Block Diagram of Type N-1 PFmn INTR Note 1 INTRmn INTF Note 1 INTFmn PFCmn PMCmn PMmn PORT P-ch N-ch Note 2 Address Input signal 1 when Noise Edge alternate function is used elimination detection Input signal 2 when alternate function is used...
Page 230 CHAPTER 4 PORT FUNCTIONS Figure 4-26. Block Diagram of Type N-2 PFmn INTR Note 1 INTRmn INTF Note 1 INTFmn PFCmn PMCmn PMmn Output signal when alternate function is used PORT P-ch N-ch Note 2 Address Input signal when Edge Noise detection elimination...
Page 231 CHAPTER 4 PORT FUNCTIONS Figure 4-27. Block Diagram of Type N-3 PFmn INTR Note 1 INTRmn INTF Note 1 INTFmn PFCmn PMCmn PMmn PORT P-ch N-ch Note 2 Address Input signal 1-1 when Edge Noise alternate function is used detection elimination Input signal 1-2 when alternate function is used...
Page 232 CHAPTER 4 PORT FUNCTIONS Figure 4-28. Block Diagram of Type N-4 PFmn INTR Note 1 INTRmn INTF Note 1 INTFmn Output signal when alternate function is used PFCmn PMCmn PMmn Output signal when alternate function is used PORT P-ch N-ch Note 2 Address Input signal 1 when...
Page 233 CHAPTER 4 PORT FUNCTIONS Figure 4-29. Block Diagram of Type U-1 PFmn Output enable signal when alternate PFCE function is used PFCEmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used PORT P-ch N-ch...
Page 234 CHAPTER 4 PORT FUNCTIONS Figure 4-30. Block Diagram of Type U-2 PFmn PFCE PFCEmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used P-ch PORT N-ch Note Address Input signal when alternate function is used Note Hysteresis characteristics are not available in port mode.
Page 235 CHAPTER 4 PORT FUNCTIONS Figure 4-31. Block Diagram of Type U-3 PFmn PFCE PFCEmn PFCmn PMCmn PMmn Output signal when alternate function is used PORT P-ch N-ch Note Address Input signal 1 when alternate function is used Input signal 2 when alternate function is used Note Hysteresis characteristics are not available in port mode.
Page 236 CHAPTER 4 PORT FUNCTIONS Figure 4-32. Block Diagram of Type U-4 PFmn PFCmn PMCmn PMmn Output signal when alternate function is used P-ch PORT N-ch Note Address Input signal when alternate function is used Note Hysteresis characteristics are not available in port mode. User’s Manual U19201EJ3V0UD...
Page 237 CHAPTER 4 PORT FUNCTIONS Figure 4-33. Block Diagram of Type U-5 PFmn PFCE PFCEmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used P-ch PORT N-ch Note Address Input signal 1-1 when alternate function is used Input signal 1-2 when Noise...
Page 238 CHAPTER 4 PORT FUNCTIONS Figure 4-34. Block Diagram of Type U-6 PFmn OCDM0 OCDM0 PFCE PFCEmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used P-ch PORT N-ch Note Address Input signal 1-1 when alternate function is used Input signal 1-2 when...
Page 239 CHAPTER 4 PORT FUNCTIONS Figure 4-35. Block Diagram of Type U-7 PFmn OCDM0 OCDM0 PFCE PFCEmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used Input signal when on-chip debugging P-ch PORT N-ch...
Page 240 CHAPTER 4 PORT FUNCTIONS Figure 4-36. Block Diagram of Type U-8 PFmn OCDM0 OCDM0 PFCE PFCEmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used P-ch PORT N-ch Address Note Input signal when Noise alternate function is used...
Page 241 CHAPTER 4 PORT FUNCTIONS Figure 4-37. Block Diagram of Type U-9 PFmn OCDM0 OCDM0 Output enable signal when alternate function is used PFCE PFCEmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used P-ch PORT N-ch...
Page 242 CHAPTER 4 PORT FUNCTIONS Figure 4-38. Block Diagram of Type U-10 PFmn PFCE PFCEmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used Output signal 3 when alternate function is used P-ch PORT N-ch...
Page 243 CHAPTER 4 PORT FUNCTIONS Figure 4-39. Block Diagram of Type U-11 PFmn PFCE PFCEmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used PORT P-ch N-ch Address Note Input signal 1 when Noise alternate function is used elimination...
Page 244 CHAPTER 4 PORT FUNCTIONS Figure 4-40. Block Diagram of Type U-12 PFmn PFCE PFCEmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used P-ch PORT N-ch Address Note Input signal when alternate function is used Note Hysteresis characteristics are not available in port mode.
Page 245 CHAPTER 4 PORT FUNCTIONS Figure 4-41. Block Diagram of Type U-13 PFmn PFCE PFCEmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used P-ch PORT N-ch Note Address Input signal when alternate function is used Note Hysteresis characteristics are not available in port mode.
Page 246 CHAPTER 4 PORT FUNCTIONS Figure 4-42. Block Diagram of Type U-14 PFmn PFCE PFCEmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used P-ch PORT N-ch Note Address Input signal 1 when alternate function is used Input signal 2 when alternate function is used...
Page 247 CHAPTER 4 PORT FUNCTIONS Figure 4-43. Block Diagram of Type U-15 PFmn INTR Note 1 INTRmn INTF Note 1 INTFmn PFCE PFCEmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used P-ch PORT N-ch...
Page 248 CHAPTER 4 PORT FUNCTIONS Figure 4-44. Block Diagram of Type U-16 PFmn PFCE PFCEmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used P-ch PORT N-ch Note Address Input signal 1 when alternate function is used Input signal 2 when alternate function is used...
Page 249 CHAPTER 4 PORT FUNCTIONS Figure 4-45. Block Diagram of Type U-17 PFmn PFCE PFCEmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used P-ch PORT N-ch Note Address Input signal 1 when alternate function is used Input signal 2 when alternate function is used...
Page 250 CHAPTER 4 PORT FUNCTIONS Figure 4-46. Block Diagram of Type U-18 PFmn Output enable signal when alternate PFCE function is used PFCEmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used PORT P-ch N-ch...
Page 251 CHAPTER 4 PORT FUNCTIONS Figure 4-47. Block Diagram of Type U-19 PFmn PFCE PFCEmn PFCmn PMCmn PMmn Output signal when alternate function is used PORT P-ch N-ch Address User’s Manual U19201EJ3V0UD...
Page 252 CHAPTER 4 PORT FUNCTIONS Figure 4-48. Block Diagram of Type U-20 PFmn INTR Note 1 INTRmn INTF Note 1 INTFmn PFCE PFCEmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used P-ch PORT N-ch...
Page 253 CHAPTER 4 PORT FUNCTIONS Figure 4-49. Block Diagram of Type U-21 PFmn PFCE PFCEmn PFCmn PMCmn PMmn Output signal when alternate function is used PORT P-ch N-ch Note Address Input signal 1 when alternate function is used Input signal 2 when alternate function is used Note Hysteresis characteristics are not available in port mode.
Page 254 CHAPTER 4 PORT FUNCTIONS Figure 4-50. Block Diagram of Type U-22 PFmn PFCE PFCEmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used Output signal 3 when alternate function is used P-ch PORT N-ch...
Page 255 CHAPTER 4 PORT FUNCTIONS Figure 4-51. Block Diagram of Type U-23 PFmn PFCE PFCEmn PFCmn PMCmn PMmn Output signal when alternate function is used PORT P-ch N-ch Note Address Input signal 1 when alternate function is used Input signal 2 when Noise alternate function is used elimination...
Page 256 CHAPTER 4 PORT FUNCTIONS Figure 4-52. Block Diagram of Type U-24 PFmn PFCE PFCEmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used P-ch PORT N-ch Address Note Input signal Noise when alternate elimination...
Page 257 CHAPTER 4 PORT FUNCTIONS Figure 4-53. Block Diagram of Type U-25 PFmn Output enable signal when alternate function is used PFCE PFCEmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used Output signal 3 when alternate function is used P-ch...
Page 258 CHAPTER 4 PORT FUNCTIONS Figure 4-54. Block Diagram of Type U-26 PFmn INTR Note 1 INTRmn INTF Note 1 INTFmn PFCE PFCEmn PFCmn PMCmn PMmn Output signal when alternate function is used PORT P-ch N-ch Note 2 Address Input signal 1 when alternate function is used Input signal 2 when Edge...
Page 259 CHAPTER 4 PORT FUNCTIONS Figure 4-55. Block Diagram of Type U-27 <R> PFmn PFCE PFCEmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used P-ch PORT N-ch Note Address Input signal 1 when alternate function is used Input signal 2 when alternate function is used...
Page 260 CHAPTER 4 PORT FUNCTIONS Figure 4-56. Block Diagram of Type U-28 PFmn Output enable signal when alternate function is used PFCE PFCEmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used Output signal 3 when alternate function is used P-ch...
Page 261 CHAPTER 4 PORT FUNCTIONS Figure 4-57. Block Diagram of Type U-29 PFmn PFCE PFCEmn PFCmn PMCmn PMmn Output signal when alternate function is used P-ch PORT N-ch Note Address Input signal 1 when alternate function is used Input signal 2 when alternate function is used Note Hysteresis characteristics are not available in port mode.
Page 262 CHAPTER 4 PORT FUNCTIONS Figure 4-58. Block Diagram of Type U-30 PFmn PFCE PFCEmn PFCmn PMCmn PMmn PORT P-ch N-ch Note Address Input signal 1 when alternate function is used Input signal 2 when alternate function is used Note Hysteresis characteristics are not available in port mode. User’s Manual U19201EJ3V0UD...
Page 263 CHAPTER 4 PORT FUNCTIONS Figure 4-59. Block Diagram of Type U-31 PFmn PFCE PFCEmn PFCmn PMCmn PMmn Output signal when alternate function is used PORT P-ch N-ch Note Address Input signal when alternate function is used Note Hysteresis characteristics are not available in port mode. User’s Manual U19201EJ3V0UD...
Page 264 CHAPTER 4 PORT FUNCTIONS Figure 4-60. Block Diagram of Type U-32 PFmn PFCE PFCEmn PFCmn PMCmn PMmn Output signal when alternate function is used PORT P-ch N-ch Note Address Input signal 1 when alternate function is used Input signal 2 when alternate function is used Note Hysteresis characteristics are not available in port mode.
Page 265 CHAPTER 4 PORT FUNCTIONS Figure 4-61. Block Diagram of Type U-33 PFmn INTR Note 1 INTRmn INTF Note 1 INTFmn PFCE PFCEmn PFCmn PMCmn PMmn Output signal when alternate function is used PORT P-ch N-ch Note 2 Address Input signal 1-1 when alternate function is used Input signal 1-2 when Noise...
Page 266 CHAPTER 4 PORT FUNCTIONS Figure 4-62. Block Diagram of Type U-34 PFmn PFCE PFCEmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used Output signal 2-1 when alternate function is used Output signal 2-2 when alternate function is used P-ch PORT N-ch...
Page 267 CHAPTER 4 PORT FUNCTIONS Figure 4-63. Block Diagram of Type U-35 <R> PFmn INTR Note 1 INTRmn INTF Note 1 INTFmn PFCE PFCEmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used P-ch PORT N-ch...
Page 268 CHAPTER 4 PORT FUNCTIONS Figure 4-64. Block Diagram of Type U-36 <R> PFmn PFCE PFCEmn PFCmn PMCmn PMmn Output signal when alternate function is used PORT P-ch N-ch Note Address Input signal when Noise alternate function is used elimination Note Hysteresis characteristics are not available in port mode. User’s Manual U19201EJ3V0UD...
Page 269 CHAPTER 4 PORT FUNCTIONS Figure 4-65. Block Diagram of Type U-37 <R> PFmn PFCE PFCEmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used P-ch PORT N-ch Note Address Input signal 1-1 when alternate function is used Input signal 1-2 when Noise...
Page 270 CHAPTER 4 PORT FUNCTIONS Figure 4-66. Block Diagram of Type U-38 <R> PFmn Output enable signal when alternate PFCE function is used PFCEmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used PORT P-ch N-ch...
Page 271 CHAPTER 4 PORT FUNCTIONS Figure 4-67. Block Diagram of Type AA-1 PFmn External reset signal OCDM0 OCDM0 INTR Note 1 INTRmn INTF Note 1 INTFmn PMCmn PMmn PORT P-ch N-ch Note 2 Address Input signal when Edge Noise alternate function is used detection elimination N-ch...
Page 272: Port Register Settings When Alternate Function Is Used
CHAPTER 4 PORT FUNCTIONS Port Register Settings When Alternate Function Is Used Table 4-25 shows the port register settings when each port is used for an alternate function. When using a port pin as an alternate-function pin, refer to the description of each pin. User’s Manual U19201EJ3V0UD...
Page 273 <R> Table 4-25. Using Port Pin as Alternate-Function Pin (1/13) Pin Name Alternate Function Pnx Bit of PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bits Pn Register PMn Register PMCn Register PFCEn Register PFCn Register (Registers) Name Note 3...
Page 274 Table 4-25. Using Port Pin as Alternate-Function Pin (2/13) Pin Name Alternate Function Pnx Bit of PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bits Pn Register PMn Register PMCn Register PFCEn Register PFCn Register (Registers) Name −...
Page 275 Table 4-25. Using Port Pin as Alternate-Function Pin (3/13) Pin Name Alternate Function Pnx Bit of PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bits Pn Register PMn Register PMCn Register PFCEn Register PFCn Register (Registers) Name RXDA2...
Page 276 Table 4-25. Using Port Pin as Alternate-Function Pin (4/13) Pin Name Alternate Function Pnx Bit of PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bits Pn Register PMn Register PMCn Register PFCEn Register PFCn Register (Registers) Name Input...
Page 277 <R> Table 4-25. Using Port Pin as Alternate-Function Pin (5/13) Pin Name Alternate Function Pnx Bit of PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bits Pn Register PMn Register PMCn Register PFCEn Register PFCn Register (Registers) Name Note 2...
Page 278 <R> Table 4-25. Using Port Pin as Alternate-Function Pin (6/13) Pin Name Alternate Function Pnx Bit of PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bits Pn Register PMn Register PMCn Register PFCEn Register PFCn Register (Registers) Name SIB5...
Page 279 Table 4-25. Using Port Pin as Alternate-Function Pin (7/13) Pin Name Alternate Function Pnx Bit of PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bits Pn Register PMn Register PMCn Register PFCEn Register PFCn Register (Registers) Name P613...
Page 280 Table 4-25. Using Port Pin as Alternate-Function Pin (8/13) Pin Name Alternate Function Pnx Bit of PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bits Pn Register PMn Register PMCn Register PFCEn Register PFCn Register (Registers) Name RXDA3...
Page 281 Table 4-25. Using Port Pin as Alternate-Function Pin (9/13) Pin Name Alternate Function Pnx Bit of PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bits Pn Register PMn Register PMCn Register PFCEn Register PFCn Register (Registers) Name Output...
Page 282 Table 4-25. Using Port Pin as Alternate-Function Pin (10/13) Pin Name Alternate Function Pnx Bit of PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bits Pn Register PMn Register PMCn Register PFCEn Register PFCn Register (Registers) Name Output...
Page 283 Table 4-25. Using Port Pin as Alternate-Function Pin (11/13) Pin Name Alternate Function Pnx Bit of PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bits Pn Register PMn Register PMCn Register PFCEn Register PFCn Register (Registers) Name P915...
Page 284 Table 4-25. Using Port Pin as Alternate-Function Pin (12/13) Pin Name Alternate Function Pnx Bit of PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bits Pn Register PMn Register PMCn Register PFCEn Register PFCn Register (Registers) Name −...
Page 285 Table 4-25. Using Port Pin as Alternate-Function Pin (13/13) Pin Name Alternate Function Pnx Bit of PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bits Pn Register PMn Register PMCn Register PFCEn Register PFCn Register (Registers) Name −...
Page 286: Cautions
CHAPTER 4 PORT FUNCTIONS Cautions 4.6.1 Cautions on setting port pins (1) In the V850E/SJ3-H and V850E/SK3-H, the general-purpose port function and several peripheral function I/O pin share a pin. To switch between the general-purpose port (port mode) and the peripheral function I/O pin (alternate-function mode), set by the PMCn register.
Page 287 CHAPTER 4 PORT FUNCTIONS The order of setting in which malfunction may occur on switching from the P41 pin to the SCL01 pin are shown below. Setting Order Setting Contents Pin States Pin Level <1> Initial value Port mode (input) Hi-Z (PMC41 bit = 0, PFC41 bit = 0,...
Page 288 CHAPTER 4 PORT FUNCTIONS Figure 4-68. Example of Switching from P02 to NMI (Incorrect) 0 → 1 PMC0 PMC0m bit = 0: Port mode PMC0m bit = 1: Alternate-function mode NMI interrupt occurrence Rising edge detector P02/NMI PMC02 bit = 0: Low level ↓...
Page 289: Cautions On Bit Manipulation Instruction For Port N Register (Pn)
CHAPTER 4 PORT FUNCTIONS 4.6.2 Cautions on bit manipulation instruction for port n register (Pn) When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the value of the output latch of an input port that is not subject to manipulation may be written in addition to the targeted bit. Therefore, it is recommended to rewrite the output latch when switching a port from input mode to output mode.
Page 290: Cautions On On-Chip Debug Pins
CHAPTER 4 PORT FUNCTIONS 4.6.3 Cautions on on-chip debug pins The DRST, DCK, DMS, DDI, and DDO pins are on-chip debug pins. After reset by the RESET pin, the P05/INTP2/DRST pin is initialized to function as an on-chip debug pin (DRST). If a high level is input to the DRST pin at this time, the on-chip debug mode is set, and the DCK, DMS, DDI, and DDO pins can be used.
Page 291: Cautions On Separate Bus Mode
CHAPTER 4 PORT FUNCTIONS 4.6.7 Cautions on separate bus mode Port 9 pins cannot be used as port pins or other alternate-function pins if even one of the A0 to A15 pins is used in the separate bus mode. After setting the PFC9 and PFCE9 registers to 0000H, therefore, set all 16 bits of the PMC9 register to FFFFH at once.
Page 292: Chapter 5 Bus Control Function
CHAPTER 5 BUS CONTROL FUNCTION The V850E/SJ3-H and V850E/SK3-H are provided with an external bus interface function by which external memories such as ROM and RAM, and I/O can be connected. Features Output is selectable from a multiplexed bus with a minimum of 3 bus cycles and a separate bus with a minimum of 2 bus cycles.
Page 293: Bus Control Pins
CHAPTER 5 BUS CONTROL FUNCTION Bus Control Pins The pins used to connect an external device are listed in the table below. Table 5-1. Bus Control Pins (a) When multiplexed bus is selected Bus Control Pin Alternate-Function Pin Function AD0 to AD15 PDL0 to PDL15 Address/data bus A16 to A23...
Page 294: Pin Status When Internal Rom, Internal Ram, On-Chip Peripheral I/O, Or Expanded Internal Ram Is Accessed
CHAPTER 5 BUS CONTROL FUNCTION 5.2.1 Pin status when internal ROM, internal RAM, on-chip peripheral I/O, or expanded internal RAM is accessed When the internal ROM, internal RAM, on-chip peripheral I/O, or expanded internal RAM is accessed, the status of each pin is as follows.
Page 295: Memory Block Function
CHAPTER 5 BUS CONTROL FUNCTION Memory Block Function The 28 MB external memory space is divided into memory blocks of 4 MB, 4MB, 4MB, and 16 MB, from the lower address, and they can be used as three CS spaces (CS1, CS2, CS3). The correspondence between the CS1 and <R>...
Page 296 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-1. Data Memory Map: Physical Address (1/2) (a) When using expanded internal RAM 0 3 F F F F F F H 0 3 F F F F F F H On-chip peripheral I/O area (2 MB) 0 3 E 0 0 0 0 0 H (4 KB)
Page 297 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-1. Data Memory Map: Physical Address (2/2) <R> (b) When not using expanded internal RAM 0 3 F F F F F F H 0 3 F F F F F F H On-chip peripheral I/O area (2 MB) 0 3 E 0 0 0 0 0 H (4 KB)
Page 298: Chip Select Control Function
CHAPTER 5 BUS CONTROL FUNCTION 5.3.1 Chip select control function In the V850E/SJ3-H and V850E/SK3-H, eight types of memory maps can be selected by the CSC0 and CSC1 registers. <R> (1) Chip area select control registers 0, 1 (CSC0 and CSC1) Set the CSC0 and CSC1 registers to the following set values.
Page 299 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-2. Four Types of Memory Maps That Can Be Set by CSC0 and CSC1 Registers: When Using Expanded Internal RAM (1/2) <1> Memory map 1 <2> Memory map 2 03FFFFFFH 03FFFFFFH Note 1 Note 1 03FE4000H 03FE4000H 03FE3FFFH...
Page 300 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-2. Four Types of Memory Maps That Can Be Set by CSC0 and CSC1 Registers: When Using Expanded Internal RAM (2/2) <3> Memory map 3 <4> Memory map 4 03FFFFFFH 03FFFFFFH Note Note 03FE4000H 03FE4000H 03FE3FFFH 03FE3FFFH...
Page 301 CHAPTER 5 BUS CONTROL FUNCTION (b) When not using expanded internal RAM The relationship between the setting value of the CSC0 and CSC1 registers and the memory map is as follows. CSC0 Register Set Value CSC1 Register Set Value Memory Map 2C11H (initial value) 0100H Memory map 1 (see <1>...
Page 302 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-3. Four Types of Memory Maps That Can Be Set by CSC0 and CSC1 Registers: When Not Using Expanded Internal RAM (2/2) <3> Memory map 3 <4> Memory map 4 03FFFFFFH 03FFFFFFH Note Note 03FEC000H 03FEC000H 03FEBFFFH...
Page 303: External Bus Interface Mode Control Function
CHAPTER 5 BUS CONTROL FUNCTION External Bus Interface Mode Control Function The V850E/SJ3-H and V850E/SK3-H include the following two external bus interface modes. • Multiplexed bus mode • Separate bus mode These two modes can be selected by using the EXIMC register. (1) External bus interface mode control register (EXIMC) The EXIMC register can be read or written in 8-bit or 1-bit units.
Page 304: Bus Access
CHAPTER 5 BUS CONTROL FUNCTION Bus Access 5.5.1 Number of clocks for access The following table shows the number of basic clocks required for accessing each resource. Area (Bus) Internal ROM Internal RAM (32 External Memory External Memory Expanded Internal (32 Bits) Bits) (Multiplexed Bus)
Page 305: Bus Size Setting Function
CHAPTER 5 BUS CONTROL FUNCTION 5.5.2 Bus size setting function Each external memory area selected by CSn can be set by using the BSC register. However, the bus size can be set to 8 bits and 16 bits only. The external memory area of the V850E/SJ3-H and V850E/SK3-H is selected by CS1 to CS3. (1) Bus size configuration register (BSC) The BSC register can be read or written in 16-bit units.
Page 306: Access By Bus Size
CHAPTER 5 BUS CONTROL FUNCTION 5.5.3 Access by bus size The V850E/SJ3-H and V850E/SK3-H access the on-chip peripheral I/O and external memory in 8-bit, 16-bit, or 32- bit units. The bus size is as follows. • The bus size of the on-chip peripheral I/O is fixed to 16 bits. •...
Page 307 CHAPTER 5 BUS CONTROL FUNCTION (2) Byte access (8 bits) (a) 16-bit data bus width <1> Access to even address (2n) <2> Access to odd address (2n + 1) Address Address 2n + 1 Byte data External data Byte data External data (b) 8-bit data bus width <1>...
Page 308 CHAPTER 5 BUS CONTROL FUNCTION (3) Halfword access (16 bits) (a) With 16-bit data bus width <1> Access to even address (2n) <2> Access to odd address (2n + 1) Address First access Second access Address Address 2n + 1 2n + 1 2n + 2 Halfword data External data...
Page 309 CHAPTER 5 BUS CONTROL FUNCTION (4) Word access (32 bits) (a) 16-bit data bus width (1/2) <1> Access to address (4n) First access Second access Address Address 4n + 1 4n + 3 4n + 2 Word data External data Word data External data <2>...
Page 310 CHAPTER 5 BUS CONTROL FUNCTION (a) 16-bit data bus width (2/2) <3> Access to address (4n + 2) First access Second access Address Address 4n + 3 4n + 5 4n + 2 4n + 4 Word data External data Word data External data <4>...
Page 311 CHAPTER 5 BUS CONTROL FUNCTION (b) 8-bit data bus width (1/2) <1> Access to address (4n) First access Second access Third access Fourth access Address Address Address Address 4n + 1 4n + 2 4n + 3 Word data External data Word data External data Word data External data Word data External data...
Page 312 CHAPTER 5 BUS CONTROL FUNCTION (b) 8-bit data bus width (2/2) <3> Access to address (4n + 2) First access Second access Third access Fourth access Address Address Address Address 4n + 2 4n + 3 4n + 4 4n + 5 Word data External data Word data External data Word data External data...
Page 313: Wait Function
CHAPTER 5 BUS CONTROL FUNCTION Wait Function 5.6.1 Programmable wait function (1) Data wait control register 0 (DWC0) To realize interfacing with a low-speed memory or I/O, up to seven data wait states can be inserted in the bus cycle that is executed for each CS space. The number of wait states can be programmed by using the DWC0 register.
Page 314 CHAPTER 5 BUS CONTROL FUNCTION After reset: 7777H Address: FFFFF484H DWC0 DW32 DW31 DW30 DW22 DW21 DW20 DW12 DW11 DW10 Number of wait states inserted in DWn2 DWn1 DWn0 CSn space (n = 1 to 3) Separate bus Multiplexed bus ≤...
Page 315 CHAPTER 5 BUS CONTROL FUNCTION <R> (b) When not using the expanded internal RAM To realize interfacing with a low-speed memory or I/O, up to seven data wait states can be inserted in the bus cycle that is executed for each external memory area (3E00000H to 3FEBFFFH). The number of wait states can be programmed by using the DWC1 register.
Page 316: External Wait Function
CHAPTER 5 BUS CONTROL FUNCTION 5.6.2 External wait function To synchronize an extremely slow external memory, I/O, or asynchronous system, any number of wait states can be inserted in the bus cycle by using the external wait pin (WAIT). When the PCM0 pin is set to alternate function, the external wait function is enabled. Access to each area of the internal ROM, internal RAM, and on-chip peripheral I/O is not subject to control by the external wait function, in the same manner as the programmable wait function.
Page 317: Relationship Between Programmable Wait And External Wait
CHAPTER 5 BUS CONTROL FUNCTION 5.6.3 Relationship between programmable wait and external wait Wait cycles are inserted as the result of an OR operation between the wait cycles specified by the set value of the programmable wait and the wait cycles controlled by the WAIT pin. Programmable wait Wait control Wait via WAIT pin...
Page 318: Programmable Address Wait Function
CHAPTER 5 BUS CONTROL FUNCTION 5.6.4 Programmable address wait function Address-setup (ASW) or address-hold waits (AHW) to be inserted in each bus cycle can be set by using the AWC register. Address wait insertion is set for each chip select area (CS1 to CS3). If an address setup wait is inserted, it seems that the high-clock period of the T1 state is extended by 1 clock.
Page 319 CHAPTER 5 BUS CONTROL FUNCTION After reset: FFFFH Address: FFFFF488H AHW3 ASW3 AHW2 ASW2 AHW1 ASW1 <R> Expanded internal RAM/external memory area setting Bits 15 to 8 Note 00111111 Expanded internal RAM is used. External memory area (3E00000H to 3FEBFFFH) is not used. 11110011 Expanded internal RAM is not used.
Page 320: Idle State Insertion Function
CHAPTER 5 BUS CONTROL FUNCTION Idle State Insertion Function To facilitate interfacing with low-speed memories, one idle state (TI) can be inserted after the T3 state in the bus cycle that is executed for each space selected by the chip select function in the multiplex address/data bus mode. In the separate bus mode, one idle state (TI) can be inserted after the T2 state.
Page 321: Bus Hold Function
CHAPTER 5 BUS CONTROL FUNCTION Bus Hold Function 5.8.1 Functional outline The HLDRQ and HLDAK functions are valid if the PCM2 and PCM3 pins are set to alternate function. When the HLDRQ pin is asserted (low level), indicating that another bus master has requested bus mastership, the external address/data bus goes into a high-impedance state and is released (bus hold status).
Page 322: Bus Hold Procedure
CHAPTER 5 BUS CONTROL FUNCTION 5.8.2 Bus hold procedure The bus hold status transition procedure is shown below. <1> HLDRQ = 0 acknowledged <2> All bus cycle start requests inhibited Normal status <3> End of current bus cycle <4> Shift to bus idle status <5>...
Page 323: Bus Priority
CHAPTER 5 BUS CONTROL FUNCTION Bus Priority Bus hold, DMA transfer, operand data accesses, instruction fetch (branch), and instruction fetch (successive) are executed in the external bus cycle. Bus hold has the highest priority, followed by DMA transfer, operand data access, instruction fetch (branch), and instruction fetch (successive).
Page 324: Bus Timing
CHAPTER 5 BUS CONTROL FUNCTION 5.10 Bus Timing Figure 5-6. Multiplexed Bus Read Timing (Bus Size: 16 Bits, 16-Bit Access) CLKOUT A23 to A16 ASTB CS3 to CS1 WAIT AD15 to AD0 Idle state Programmable External wait wait 8-bit access Odd address Even address AD15 to AD8...
Page 325 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-8. Multiplexed Bus Write Timing (Bus Size: 16 Bits, 16-Bit Access) CLKOUT A23 to A16 ASTB CS3 to CS1 WAIT AD15 to AD0 WR1, WR0 Programmable External wait wait 8-bit access Odd address Even address AD15 to AD8 Active Undefined...
Page 326 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-10. Multiplexed Bus Hold Timing (Bus Size: 16 Bits, 16-Bit Access) Note Note CLKOUT HLDRQ HLDAK Undefined A23 to A16 Undefined AD15 to AD0 Undefined Undefined ASTB CS3 to CS1 Note This idle state (TI) does not depend on the BCC register settings. Remarks 1.
Page 327 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-11. Separate Bus Read Timing (Bus Size: 16 Bits, 16-Bit Access) CLKOUT CS3 to CS1 WAIT A23 to A0 AD15 to AD0 External Programmable Idle state wait wait 8-bit access Odd address Even address AD15 to AD8 Active Hi-Z...
Page 328 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-13. Separate Bus Write Timing (Bus Size: 16 Bits, 16-Bit Access) CLKOUT CS3 to CS1 WAIT A23 to A0 WR1, WR0 AD15 to AD0 Programmable External wait wait 8-bit access Odd address Even address AD15 to AD8 Active Undefined...
Page 329 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-15. Separate Bus Hold Timing (Bus Size: 8 Bits, Write) Note Note CLKOUT HLDRQ HLDAK A23 to A0 Undefined Undefined AD7 to AD0 WR1, WR0 CS3 to CS1 Note This idle state (TI) does not depend on the BCC register settings. Remark The broken lines indicate high impedance.
Page 330: Chapter 6 Clock Generation Function
CHAPTER 6 CLOCK GENERATION FUNCTION Overview An outline of the clock generation function is shown below. Main clock oscillator • Oscillation (f Note ) via externally connected 3 to 10 MHz resonator Subclock oscillator • Oscillation (f ) via externally connected 32.768 kHz resonator On-chip oscillator •...
Page 331: Clock Mode
CHAPTER 6 CLOCK GENERATION FUNCTION Clock Mode The V850E/SJ3-H and V850E/SK3-H have four clock modes. The features of these clock modes are described below. Caution The clock mode is set using the option byte, and therefore cannot be switched during operation. Consequently, it is important to determine which clock mode is to be used, before starting operation.
Page 332 CHAPTER 6 CLOCK GENERATION FUNCTION Table 6-1. Frequency Range of Operating Clocks in Each Clock Mode and Corresponding Source Cocks (1/2) <R> Clock Mode Option Byte Range of Main Settable Operating Mode and Source Clock of Peripheral Note 0000007BH Oscillation Clock Main Clock Frequency (f Clock (f ), IEBus Clock (f...
Page 333 CHAPTER 6 CLOCK GENERATION FUNCTION Table 6-1. Frequency Range of Operating Clocks in Each Clock Mode and Corresponding Source Cocks (2/2) <R> Clock Mode Option Byte Range of Main Settable Operating Mode and Source Clock of Peripheral Note 0000007BH Oscillation Clock Main Clock Frequency (f Clock (f ), IEBus Clock (f...
Page 334 CHAPTER 6 CLOCK GENERATION FUNCTION 6.2.1 Clock mode 1 <R> Figure 6-1. Clock Generation Circuit for Clock Mode 1 PCC.FRC bit TMM0, watch timer, Subclock watchdog timer 2, oscillator real-time counter TMM1, TMM2, Prescaler 3 watch timer, real-time counter IDLE control PLLCTL.SELPLL PCC.CLS, CK3...
Page 335 CHAPTER 6 CLOCK GENERATION FUNCTION (1) Main clock oscillator The main resonator oscillates the following frequencies (f (a) PLLI0 bit of the option byte 0000007BH = 0 (no division) (See CHAPTER 33 OPTION BYTE FUNCTION.) • In clock-through mode = 3 to 10 MHz •...
Page 336 CHAPTER 6 CLOCK GENERATION FUNCTION (7) Prescaler 1 Prescaler 1 generates the clock to be supplied to the on-chip peripheral functions (f to f /1024), using the peripheral clock (f ) (= main clock (f )) as the source clock. The following blocks are supplied by this clock.
Page 337 CHAPTER 6 CLOCK GENERATION FUNCTION 6.2.2 Clock mode 2 <R> Figure 6-2. Clock Generation Circuit for Clock Mode 2 (1/2) PCC.FRC bit TMM0, watch timer, Subclock watchdog timer 2, oscillator real-time counter TMM1, TMM2, Prescaler 3 watch timer, real-time counter IDLE control PLLCTL.SELPLL...
Page 338 CHAPTER 6 CLOCK GENERATION FUNCTION Figure 6-2. Clock Generation Circuit for Clock Mode 2 (2/2) <R> Notes 3. In clock mode 2, be sure to set the CKC.CKDIV0 bit to 1 (no division). 4. The internal oscillation clock (f ) is selected when watchdog timer 2 overflows during the oscillation stabilization time.
Page 339 CHAPTER 6 CLOCK GENERATION FUNCTION (4) Internal oscillator Oscillates a frequency (f ) of 220 kHz (TYP.). Oscillation can be stopped by setting the RCM.RSTOP bit. However, oscillation cannot be stopped if stopping the on-chip oscillator has been disabled by setting the RMOPIN bit of the option byte 0000007AH (see CHAPTER 33 OPTION BYTE FUNCTION for details) to 1.
Page 340 CHAPTER 6 CLOCK GENERATION FUNCTION 6.2.3 Clock mode 3 <R> Figure 6-3. Clock Generation Circuit for Clock Mode 3 (1/2) PCC.FRC bit TMM0, watch timer, Subclock watchdog timer 2, oscillator real-time counter TMM1, TMM2, Prescaler 3 watch timer, real-time counter IDLE control PLLCTL.SELPLL...
Page 341 CHAPTER 6 CLOCK GENERATION FUNCTION <R> Figure 6-3. Clock Generation Circuit for Clock Mode 3 (2/2) Notes 3. In clock mode 3, be sure to set the CKC.CKDIV0 bit to 1 (no division). 4. The internal oscillation clock (f ) is selected when watchdog timer 2 overflows during the oscillation stabilization time.
Page 342 CHAPTER 6 CLOCK GENERATION FUNCTION (3) Main clock oscillator stop control This circuit generates a control signal that stops oscillation of the main clock oscillator. Oscillation of the main clock oscillator is stopped in the STOP mode or when the PCC.MCK bit = 1 (valid only when the PCC.CLS bit = 1).
Page 343: Clock Mode 4
CHAPTER 6 CLOCK GENERATION FUNCTION 6.2.4 Clock mode 4 <R> Figure 6-4. Clock Generation Circuit for Clock Mode 4 (1/2) PCC.FRC bit TMM0, watch timer, Subclock watchdog timer 2, oscillator real-time counter TMM1, TMM2, Prescaler 3 watch timer, real-time counter IDLE control PLLCTL.SELPLL...
Page 344 CHAPTER 6 CLOCK GENERATION FUNCTION <R> Figure 6-4. Clock Generation Circuit for Clock Mode 4 (2/2) Notes 3. In clock mode 4, be sure to set the CKC.CKDIV0 bit to 1 (no division). 4. The internal oscillation clock (f ) is selected when watchdog timer 2 overflows during the oscillation stabilization time.
Page 345 CHAPTER 6 CLOCK GENERATION FUNCTION (4) Internal oscillator Oscillates a frequency (f ) of 220 kHz (TYP.). Oscillation can be stopped by setting the RCM.RSTOP bit. However, oscillation cannot be stopped if stopping the on-chip oscillator has been disabled by setting the RMOPIN bit of the option byte 0000007AH (see CHAPTER 33 OPTION BYTE FUNCTION for details) to 1.
Page 346: Clock Mode Setting
CHAPTER 6 CLOCK GENERATION FUNCTION 6.2.5 Clock mode setting The clock mode can be set by using the SELCM2 to SELCM0 bits of the option byte 0000007BH. For details, see CHAPTER 33 OPTION BYTE FUNCTION. Caution The clock mode cannot be changed during operation. Table 6-2.
Page 347: Registers
CHAPTER 6 CLOCK GENERATION FUNCTION Registers (1) Processor clock control register (PCC) The PCC register is a special register. Data can be written to this register only in combination of specific sequences (see 3.4.8 Special registers). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 03H.
Page 348 CHAPTER 6 CLOCK GENERATION FUNCTION (2/2) Clock selection (f × Setting prohibited × × × Cautions 1. Do not change the CPU clock (by using the CK3 to CK0 bits) while CLKOUT is being output. 2. When manipulating the CK3 bit, do not change the set values of the CK2 to CK0 bits.
Page 349 CHAPTER 6 CLOCK GENERATION FUNCTION (2) Internal oscillation mode register (RCM) The RCM register is an 8-bit register that sets the operation mode of the internal oscillator. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H Address: FFFFF80CH <...
Page 350 CHAPTER 6 CLOCK GENERATION FUNCTION (4) PLL control register (PLLCTL) The PLLCTL register is an 8-bit register that controls the PLL function. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 01H. After reset: 01H Address: FFFFF82CH <...
Page 351 CHAPTER 6 CLOCK GENERATION FUNCTION (5) Clock control register (CKC) The CKC register is a special register. Data can be written to this register only in a combination of specific sequence (see 3.4.8 Special registers). The CKC register sets the multiplication clock (f This register can be read or written in 8-bit or 1-bit units.
Page 352 CHAPTER 6 CLOCK GENERATION FUNCTION (6) Lock register (LOCKR) Phase lock occurs at a given frequency following power application or immediately after the STOP mode is released, and the time required for stabilization is the lockup time (frequency stabilization time). This state until stabilization is called the lockup status, and the stabilized state is called the locked status.
Page 353 CHAPTER 6 CLOCK GENERATION FUNCTION (7) PLL lockup time specification register (PLLS) The PLLS register is an 8-bit register used to select the PLL lockup time when the PLLCTL.PLLON bit is changed from 0 to 1. This register can be read or written in 8-bit units. Reset sets this register to 03H.
Page 354 CHAPTER 6 CLOCK GENERATION FUNCTION (8) SSCG control register (SSCGCTL) The SSCGCTL register is an 8-bit register used to control the SSCG. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H Address: FFFFF3F0H <...
Page 355 CHAPTER 6 CLOCK GENERATION FUNCTION (9) SSCG frequency control register 0 (SFC0) The SFC0 register is a special register. Data can be written to this register only in a combination of specific sequences (see 3.4.8 Special registers). The SFC0 register is an 8-bit register used to control the main oscillation clock frequency (f ) of the SSCG.
Page 356 CHAPTER 6 CLOCK GENERATION FUNCTION (10) SSCG frequency control register 1 (SFC1) The SFC1 register is a special register. Data can be written to this register only in a combination of specific sequences (see 3.4.8 Special registers). The SFC1 register is an 8-bit register used to control the frequency modulation specification, frequency modulation ratio, and modulation cycle of the SSCG.
Page 357: Operation
CHAPTER 6 CLOCK GENERATION FUNCTION Operation 6.4.1 Operation of each clock The operating status of each clock is shown in the table below. Table 6-3. Clock Operating Statuses Register Setting CLS bit = 0, CLS bit = 0, CLS bit = 1, CLS bit = 1, and Operating MCK bit = 0,...
Page 358: Clock Output Function
CHAPTER 6 CLOCK GENERATION FUNCTION 6.4.2 Clock output function The clock output function is used to output the internal system clock (f ) from the CLKOUT pin. The internal system clock (f ) is selected by using the PCC.CK3 to PCC.CK0 bits. The CLKOUT pin shares pin with the PCM1 pin and functions as a clock output pin if so specified by the control register of port CM.
Page 359: Procedure For Setting Clock Generation Function For Using Clock Mode 1
CHAPTER 6 CLOCK GENERATION FUNCTION 6.4.3 Procedure for setting clock generation function for using clock mode 1 Figure 6-5. Procedure for Setting Clock Generation Function for Using Clock Mode 1 Reset Wait for main Watchdog timer 2 overflow occurred On-chip oscillator clock oscillator during oscillation stabilization time operation...
Page 360 CHAPTER 6 CLOCK GENERATION FUNCTION (1) Switching from clock-through mode to PLL mode <1> PLLS register setting: Lockup time selection μ Set so that the lockup time is 800 s or longer. <2> PLLCTL.PLLON bit ← 1: PLL operation enabled <3>...
Page 361 CHAPTER 6 CLOCK GENERATION FUNCTION (4) Switching from subclock operation to main clock operation <1> PCC.MCK bit ← 0: Start of main clock oscillation <2> Insert a wait by a program and wait for the main clock oscillation stabilization time to elapse. <3>...
Page 362: Procedure For Setting Clock Generation Function For Using Clock Modes 2, 3, And 4
CHAPTER 6 CLOCK GENERATION FUNCTION 6.4.4 Procedure for setting clock generation function for using clock modes 2, 3, and 4 Figure 6-6. Procedure for Setting Clock Generation Function for Using Clock Modes 2, 3, and 4 Reset Wait for main Watchdog timer 2 overflow occurred On-chip oscillator clock oscillator...
Page 363 CHAPTER 6 CLOCK GENERATION FUNCTION (1) Initial settings for using clock modes 2, 3, and 4 When using clock modes 2, 3, or 4, set appropriate values to the CKC and SFC0 registers while the clock modes are in their initial status following reset release; that is, in clock-through mode and with SSCG operation stopped.
Page 364 CHAPTER 6 CLOCK GENERATION FUNCTION (2) Switching from clock-through mode to SSCG mode <1> SSCGCTL.SSCGON bit ← 1: SSCG operation enabled <2> Software-based wait of 1 ms or longer: Wait for SSCG lockup time to elapse <3> SSCGCTL.SELSSCG bit ← 1: Multiplication clock (f ) selected as SSCG output clock SSCGO...
Page 365 CHAPTER 6 CLOCK GENERATION FUNCTION Remark Internal system clock (f ): Clock generated from the main clock (f ) by setting the PCC.CK2 to PCC.CK0 bits. (5) Switching from subclock operation to main clock operation <1> PCC.MCK bit ← 0: Start of main clock oscillation <2>...
Page 366: Chapter 7 16-Bit Timer/Event Counter P (Tmp)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Timer P (TMP) is a 16-bit timer/event counter. The V850E/SJ3-H and V850E/SK3-H have nine timer/event counter channels, TMP0 to TMP8. Overview 7.1.1 TMP0 to TMP6 An outline of TMP0 to TMP6 are shown below. •...
Page 367: Functions
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Functions 7.2.1 TMP0 to TMP6 TMP0 to TMP6 have the following functions. • Interval timer • External event counter • External trigger pulse output • One-shot pulse output • PWM output • Free-running timer •...
Page 368: Configuration
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Configuration 7.3.1 TMP0 to TMP6 TMP0 to TMP6 include the following hardware. Table 7-1. Configuration of TMP0 to TMP6 Item Configuration Timer register 16-bit counter Registers TMPk capture/compare registers 0, 1 (TPkCCR0, TPkCCR1) TMPk counter read buffer register (TPkCNT) CCR0, CCR1 buffer registers Note 1...
Page 369 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-1. Block Diagram of TMPk Internal bus TPkCNT INTTPkOV 16-bit counter Clear Note 1 Note 2 /256 TOPk0 Note 1 Note 2 /128 /512 TOPk1 CCR0 buffer INTTPkCC0 register CCR1 buffer INTTPkCC1 register TIPk0 TPkCCR0...
Page 370 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) 16-bit counter This 16-bit counter can count internal clocks or external events. The count value of this counter can be read by using the TPkCNT register. When the TPkCTL0.TPkCE bit = 0, the value of the 16-bit counter is FFFFH. If the TPkCNT register is read at this time, 0000H is read.
Page 371: Tmp7 And Tmp8
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.3.2 TMP7 and TMP8 TMP7 and TMP8 include the following hardware. Table 7-2. Configuration of TMP7 and TMP8 Item Configuration Timer register 16-bit counter Registers TMPm capture/compare registers 0, 1 (TPmCCR0, TPmCCR1) TMPm counter read buffer register (TPmCNT) TMPm counter write register (TPmTCW) CCR0, CCR1 buffer registers Note 1...
Page 372 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-2. Block Diagram of TMP7 and TMP8 Internal bus Note 3 TPmCNT TPmTCW Counter INTTPmOV 16-bit counter control Clear Note 1 Note 2 /256 TOPm0 Note 1 Note 2 /128 /512 TOPm1 Edge detection/ TENCm0/TIPm0 CCR0...
Page 373 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) 16-bit counter This 16-bit counter can count internal clocks or external events. The count value of this counter can be read by using the TPmCNT register. When the TPmCTL0.TPmCE bit = 0, the value of the 16-bit counter is FFFFH. If the TPmCNT register is read at this time, 0000H is read.
Page 374: Registers
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Registers The registers that control TMPn are as follows. • TMPn control register 0 (TPnCTL0) • TMPn control register 1 (TPnCTL1) • TMPm control register 2 (TPmCTL2) • TMPn I/O control register 0 (TPnIOC0) •...
Page 375 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) TMPn control register 0 (TPnCTL0) The TPnCTL0 register is an 8-bit register that controls the operation of TMPn. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. The same value can always be written to the TPnCTL0 register by software.
Page 376 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) TMPn control register 1 (TPnCTL1) The TPnCTL1 register is an 8-bit register that controls the operation of TMPn. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. (1/2) After reset: 00H Address: TP0CTL1 FFFFF591H, TP1CTL1 FFFFF5A1H,...
Page 377 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2/2) Cautions 1. The TPnEST bit is valid only in the external trigger pulse output mode or one-shot pulse output mode. In any other mode, writing 1 to this bit is ignored. 2. The TPnEEE bit is valid only in the interval timer mode, external trigger pulse output mode, one-shot pulse output mode, PWM output mode, free-running timer mode, or pulse width measurement mode.
Page 378 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (3) TMPm control register 2 (TPmCTL2) The TTmCTL2 register is an 8-bit register that controls the encoder count function operation. The TTmCTL2 register is valid only in the encoder compare mode. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 379 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2/2) TPmUDS1 TPmUDS0 Up/down count selection When valid edge of TENCm0 input is detected Counts down when TENCm1 = high level. Counts up when TENCm1 = low level. Counts up when valid edge of TENCm0 input is detected. Counts down when valid edge of TENCm1 input is detected.
Page 380 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (4) TMPn I/O control register 0 (TPnIOC0) The TPnIOC0 register is an 8-bit register that controls the timer output (TOPn0, TOPn1 pins). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 381 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) After reset: 00H Address: TP0IOC0 FFFFF592H, TP1IOC0 FFFFF5A2H, TP2IOC0 FFFFF5B2H, TP3IOC0 FFFFF5C2H, TP4IOC0 FFFFF5D2H, TP5IOC0 FFFFF5E2H, TP6IOC0 FFFFF5F2H, TP7IOC0 FFFFF643H, TP8IOC0 FFFFF663H <2> <0> TPnIOC0 TPnOL1 TPnOE1 TPnOL0 TPnOE0 (n = 0 to 8) Note TPnOL1 TOPn1 pin output level setting...
Page 382 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (5) TMPn I/O control register 1 (TPnIOC1) The TPnIOC1 register is an 8-bit register that controls the valid edge of the capture trigger input signals (TIPn0, TIPn1 pins). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 383 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (6) TMPn I/O control register 2 (TPnIOC2) The TPnIOC2 register is an 8-bit register that controls the valid edge of the external event count input signal (TIPn0 pin) and external trigger input signal (TIPn0 pin). This register can be read or written in 8-bit or 1-bit units.
Page 384 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (7) TMPm I/O control register 3 (TPmIOC3) The TPmIOC3 register is an 8-bit register that controls the encoder clear function operation. The TPmIOC3 register is valid only in the encoder compare mode. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 385 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2/2) TPmECS1 TPmECS0 Valid edge setting of encoder clear signal (TECRm pin) Detects no edge (clearing encoder is invalid). Detects rising edge. Detects falling edge. Detects both edges. TPmEIS1 TPmEIS0 Valid edge setting of encoder input signals (TENCm0, TENCm1 pins) Detects no edge (inputting encoder is invalid).
Page 386 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (8) TMPn option register 0 (TPnOPT0) The TPnOPT0 register is an 8-bit register used to set the capture/compare operation and detect an overflow. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 387 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (9) TMPm option register 1 (TPmOPT1) The TPmOPT1 register is an 8-bit register that detects the overflow, underflow, and count-up/down operation of the encoder count function. The TPmOPT1 register is valid only in the encoder compare mode. This register can be read or written in 8-bit or 1-bit units.
Page 388 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2/2) TPmEOF Overflow detection flag for TMPm encoder function Set (1) Overflow occurs. Reset (0) Cleared by writing 0 to the TPmEOF bit or when the TPmCTL0.TPmCE bit = 0 • The TPmEOF bit is set to 1 when 16-bit counter overflows from FFFFH to 0000H in encoder compare mode.
Page 389 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (10) TMPn capture/compare register 0 (TPnCCR0) The TPnCCR0 register is a 16-bit register that can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TPnOPT0.TPnCCS0 bit.
Page 390 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (a) Function as compare register The TPnCCR0 register can be rewritten even when the TPnCTL0.TPnCE bit = 1. The set value of the TPnCCR0 register is transferred to the CCR0 buffer register. When the value of the 16-bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal (INTTPnCC0) is generated.
Page 391 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (11) TMPn capture/compare register 1 (TPnCCR1) The TPnCCR1 register is a 16-bit register that can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TPnOPT0.TPnCCS1 bit.
Page 392 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (a) Function as compare register The TPnCCR1 register can be rewritten even when the TPnCTL0.TPnCE bit = 1. The set value of the TPnCCR1 register is transferred to the CCR1 buffer register. When the value of the 16-bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTPnCC1) is generated.
Page 393 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (12) TMPm counter write register (TPmTCW) The TPmTCW register is used to set the initial value of the 16-bit counter. The TPmTCW register is valid only in the encoder compare mode. This register can be read or written in 16-bit units. Rewrite the TPmTCW register when the TPmCTL0.TPmCE bit = 0.
Page 394 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (14) TMPm noise elimination control register (ENaNFC) Digital noise elimination can be selected for the TECRm, TENCm0, and TENCm1 pins. The noise elimination settings are performed using the ENaNFC register. When digital noise elimination is selected, the sampling clock for digital sampling can be selected from among /4, f /8, f /16, f...
Page 395 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-3 shows a timing example of noise elimination by digital filtering by the encoder count function input pins (TECRm, TENCm0, and TENCm1). Figure 7-3. Digital Noise Elimination Timing Example (Sampling: 3 Times (ENaNFSTS Bit = 0)) Noise elimination clock Input signal Sampling...
Page 396: Timer Output Operations
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Timer Output Operations The following table shows the operations and output levels of the TOPn0 and TOPn1 pins. Table 7-5. Timer Output Control in Each Mode Operation Mode TOPn1 Pin TOPn0 Pin Interval timer mode Square wave output External event count mode None...
Page 397: Operation
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Operation TMP0 to TMP6 can perform the following operations. TPkCTL1.TPkEST Bit TIPk0 Pin Capture/Compare Compare Register Operation (Software Trigger Bit) (External Trigger Input) Register Setting Write Interval timer mode Invalid Invalid Compare only Anytime write Note 1 External event count mode...
Page 398 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Counter basic operation for TMP0 to TMP6 This section explains the basic operation of the 16-bit counter. For details, refer to the description of the operation in each mode. Remark k = 0 to 6 (a) Count start operation •...
Page 399 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Counter basic operation for TMP7 and TMP8 This section explains the basic operation of the 16-bit counter. For details, refer to the description of the operation in each mode. Remark m = 7, 8 (a) Counter start operation •...
Page 400 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (d) Count value holding operation The value of the 16-bit counter is held by the TPmCTL2.TPmECC bit in the encoder compare mode. The value of the 16-bit counter is reset to FFFFH when the TPmECC bit = 0 and TPmCTL0.TPmCE bit = 0. When the TPmCE bit is set to 1 next time, the set value of the TPmTCW register is transferred to the 16-bit counter and the counter continues its count operation.
Page 401 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (3) Anytime write and batch write The TPnCCR0 and TPnCCR1 registers in TMPn can be rewritten during timer operation (TPnCTL0.TPnCE bit = 1), but the write method (anytime write, batch write) of the CCR0 and CCR1 buffer registers differs depending on the mode.
Page 402 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-5. Timing of Anytime Write TPnCE bit = 1 FFFFH 16-bit counter 0000H TPnCCR0 register CCR0 buffer register 0000H TPnCCR1 register CCR1 buffer register 0000H INTTPnCC0 signal INTTPnCC1 signal Remarks 1. D : Setting values of TPnCCR0 register : Setting values of TPnCCR1 register 2.
Page 403 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) Batch write In this mode, data is transferred all at once from the TPnCCR0 and TPnCCR1 registers to the CCR0 and CCR1 buffer registers during timer operation. This data is transferred upon a match between the value of the CCR0 buffer register and the value of the 16-bit counter.
Page 404 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-6. Flowchart of Basic Operation for Batch Write START Initial settings • Set values to TPnCCRa register • Timer operation enable (TPnCE bit = 1) → Transfer values of TPnCCRa register to CCRa buffer register TPnCCR0 register rewrite Batch write enable...
Page 405 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-7. Timing of Batch Write TPnCE bit = 1 FFFFH 16-bit counter 0000H TPnCCR0 register CCR0 buffer register 0000H Note 1 Note 1 Same value write TPnCCR1 register Note 2 Note 3 CCR1 buffer register 0000H Note 1...
Page 406: Interval Timer Mode (Tpnmd2 To Tpnmd0 Bits = 000)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.6.1 Interval timer mode (TPnMD2 to TPnMD0 bits = 000) In the interval timer mode, an interrupt request signal (INTTPnCC0) is generated at the interval set by the TPnCCR0 register if the TPnCTL0.TPnCE bit is set to 1. A square wave with a duty factor of 50% whose half cycle is equal to the interval can be output from the TOPn0 pin.
Page 407 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) When the TPnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization with the count clock, and the counter starts counting. At this time, the output of the TOPn0 pin is inverted. Additionally, the set value of the TPnCCR0 register is transferred to the CCR0 buffer register.
Page 408 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-10. Register Setting for Interval Timer Mode Operation (2/3) (c) TMPn I/O control register 0 (TPnIOC0) TPnOL1 TPnOE1 TPnOL0 TPnOE0 TPnIOC0 0: Disable TOPn0 pin output 1: Enable TOPn0 pin output Setting TOPn0 pin output level before count operation 0: Low level 1: High level...
Page 409 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-10. Register Setting for Interval Timer Mode Operation (3/3) (g) TMPn capture/compare register 1 (TPnCCR1) The TPnCCR1 register is not used in the interval timer mode. However, the set value of the TPnCCR1 register is transferred to the CCR1 buffer register.
Page 410 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Interval timer mode operation flow Figure 7-11. Software Processing Flow in Interval Timer Mode FFFFH 16-bit counter 0000H TPnCE bit TPnCCR0 register TOPn0 pin output INTTPnCC0 signal <1> <2> <1> Count operation start flow START Register initial setting Initial setting of these registers is performed...
Page 411 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Interval timer mode operation timing (a) Operation if TPnCCR0 register is set to 0000H If the TPnCCR0 register is set to 0000H, the INTTPnCC0 signal is generated at each count clock, and the output of the TOPn0 pin is inverted.
Page 412 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) Operation if TPnCCR0 register is set to FFFFH If the TPnCCR0 register is set to FFFFH, the 16-bit counter counts up to FFFFH. The counter is cleared to 0000H in synchronization with the next count-up timing. The INTTPnCC0 signal is generated and the output of the TOPn0 pin is inverted.
Page 413 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Notes on rewriting TPnCCR0 register When the value of the TPnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. If there is a possibility of overflow, stop counting and then change the set value. FFFFH 16-bit counter 0000H...
Page 414 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (d) Operation of TPnCCR1 register Figure 7-12. Configuration of TPnCCR1 Register TPnCCR1 register Output TOPn1 pin CCR1 buffer register controller Match signal INTTPnCC1 signal Clear Count clock Output 16-bit counter TOPn0 pin selection controller Match signal INTTPnCC0 signal...
Page 415 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) When the TPnCCR1 register is set to the same value as the TPnCCR0 register, the INTTPnCC1 signal is generated at the same timing as the INTTPnCC0 signal and the TOPn1 pin output is inverted. In other words, a square wave with a duty factor of 50% can be output from the TOPn1 pin.
Page 416 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) If the set value of the TPnCCR1 register is greater than the set value of the TPnCCR0 register, the count value of the 16-bit counter does not match the value of the TPnCCR1 register. Consequently, the INTTPnCC1 signal is not generated, nor is the output of the TOPn1 pin changed.
Page 417 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (3) Operation by external event count input (TIPn0) (a) Operation To count the 16-bit counter at the valid edge of external event count input (TIPn0) in the interval timer mode, the valid edge of the external event count input is necessary once because the 16-bit counter is cleared from FFFFH to 0000H immediately after the TPnCE bit is set from 0 to 1.
Page 418: External Event Count Mode (Tpnmd2 To Tpnmd0 Bits = 001)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.6.2 External event count mode (TPnMD2 to TPnMD0 bits = 001) In the external event count mode, the valid edge of the external event count input (TIPn0) is counted when the TPnCTL0.TPnCE bit is set to 1, and an interrupt request signal (INTTPnCC0) is generated each time the number of edges set by the TPnCCR0 register have been counted.
Page 419 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-16. Basic Timing in External Event Count Mode FFFFH 16-bit counter − 1 16-bit counter 0000 0001 0000H External event count input TPnCE bit (TIPn0 pin input) TPnCCR0 register TPnCCR0 register INTTPnCC0 signal INTTPnCC0 signal Number of Number of...
Page 420 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) When the TPnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H. The counter counts each time the valid edge of external event count input is detected. Additionally, the set value of the TPnCCR0 register is transferred to the CCR0 buffer register.
Page 421 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-17. Register Setting for Operation in External Event Count Mode (2/2) (d) TMPn counter read buffer register (TPnCNT) The count value of the 16-bit counter can be read by reading the TPnCNT register. (e) TMPn capture/compare register 0 (TPnCCR0) If the TPnCCR0 register is set to D , the count is cleared when the number of external events has...
Page 422 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) External event count mode operation flow Figure 7-18. Flow of Software Processing in External Event Count Mode FFFFH 16-bit counter 0000H TPnCE bit TPnCCR0 register INTTPnCC0 signal <1> <2> <1> Count operation start flow START Register initial setting Initial setting of these registers...
Page 423 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Operation timing in external event count mode Cautions 1. In the external event count mode, setting the TPnCCR0 and TPnCCR1 registers to 0000H is disabled. 2. In the external event count mode, use of the timer output (TOPn0, TOPn1) is disabled. If performing external event count input (TIPn0) using timer output (TOPn1), set the interval timer mode to enable the count clock operation (TPnCTL1.TPnEEE bit = 1) for the external event count input (refer to 7.6.1 (3) Operation by external event count input (TIPn0)).
Page 424 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) Notes on rewriting the TPnCCR0 register If the value of the TPnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. If there is a possibility of overflow, stop counting and then change the set value. FFFFH 16-bit counter 0000H...
Page 425 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Operation of TPnCCR1 register Figure 7-19. Configuration of TPnCCR1 Register TPnCCR1 register CCR1 buffer register Match signal INTTPnCC1 signal Clear Edge TIPn0 pin 16-bit counter detector (external event count input) Match signal INTTPnCC0 signal TPnCE bit CCR0 buffer register...
Page 426 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) If the set value of the TPnCCR1 register is greater than the set value of the TPnCCR0 register, the INTTPnCC1 signal is not generated because the count value of the 16-bit counter and the value of the TPnCCR1 register do not match.
Page 427: External Trigger Pulse Output Mode (Tpnmd2 To Tpnmd0 Bits = 010)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.6.3 External trigger pulse output mode (TPnMD2 to TPnMD0 bits = 010) In the external trigger pulse output mode, 16-bit timer/event counter P waits for a trigger when the TPnCTL0.TPnCE bit is set to 1. When the valid edge of an external trigger input signal is detected, 16-bit timer/event counter P starts counting, and outputs a PWM waveform from the TOPn1 pin.
Page 428 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-23. Basic Timing in External Trigger Pulse Output Mode FFFFH 16-bit counter 0000H TPnCE bit External trigger input (TIPn0 pin input) TPnCCR0 register INTTPnCC0 signal TOPn0 pin output (only when software trigger is used) TPnCCR1 register INTTPnCC1 signal TOPn1 pin output...
Page 429 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-24. Setting of Registers in External Trigger Pulse Output Mode (1/2) (a) TMPn control register 0 (TPnCTL0) TPnCE TPnCKS2 TPnCKS1 TPnCKS0 TPnCTL0 Select count clock 0: Stop counting 1: Enable counting (b) TMPn control register 1 (TPnCTL1) TPnEST TPnEEE TPnMD2 TPnMD1 TPnMD0...
Page 430 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-24. Setting of Registers in External Trigger Pulse Output Mode (2/2) (d) TMPn I/O control register 2 (TPnIOC2) TPnEES1 TPnEES0 TPnETS1 TPnETS0 TPnIOC2 Select valid edge of external trigger input (TIPn0 pin) (e) TMPn counter read buffer register (TPnCNT) The value of the 16-bit counter can be read by reading the TPnCNT register.
Page 431 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Operation flow in external trigger pulse output mode Figure 7-25. Software Processing Flow in External Trigger Pulse Output Mode (1/2) FFFFH 16-bit counter 0000H TPnCE bit External trigger input (TIPn0 pin input) TPnCCR0 register CCR0 buffer register INTTPnCC0 signal...
Page 432 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-25. Software Processing Flow in External Trigger Pulse Output Mode (2/2) <1> Count operation start flow <3> TPnCCR0, TPnCCR1 register setting change flow Only writing of the TPnCCR1 START register must be performed when the set duty factor is changed.
Page 433 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) External trigger pulse output mode operation timing (a) Note on changing pulse width during operation To change the PWM waveform while the counter is operating, write the TPnCCR1 register last. Rewrite the TPnCCRm register after writing the TPnCCR1 register after the INTTPnCC0 signal is detected. FFFFH 16-bit counter 0000H...
Page 434 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) In order to transfer data from the TPnCCRa register to the CCRa buffer register, the TPnCCR1 register must be written. To change both the cycle and active level width of the PWM waveform at this time, first set the cycle to the TPnCCR0 register and then set the active level width to the TPnCCR1 register.
Page 435 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TPnCCR1 register to 0000H. The 16-bit counter is cleared to 0000H and the INTTPnCC0 and INTTPnCC1 signals are generated at the next timing after a match between the count value of the 16-bit counter and the value of the CCR0 buffer register.
Page 436 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Conflict between trigger detection and match with CCR1 buffer register If the trigger is detected immediately after the INTTPnCC1 signal is generated, the 16-bit counter is immediately cleared to 0000H, the output signal of the TOPn1 pin is asserted, and the counter continues counting.
Page 437 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (d) Conflict between trigger detection and match with CCR0 buffer register If the trigger is detected immediately after the INTTPnCC0 signal is generated, the 16-bit counter is cleared to 0000H and continues counting up. Therefore, the active period of the TOPn1 pin is extended by time from generation of the INTTPnCC0 signal to trigger detection.
Page 438 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (e) Generation timing of compare match interrupt request signal (INTTPnCC1) The timing of generation of the INTTPnCC1 signal in the external trigger pulse output mode differs from the timing of other mode INTTPnCC1 signals; the INTTPnCC1 signal is generated when the count value of the 16-bit counter matches the value of the TPnCCR1 register.
Page 439: One-Shot Pulse Output Mode (Tpnmd2 To Tpnmd0 Bits = 011)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.6.4 One-shot pulse output mode (TPnMD2 to TPnMD0 bits = 011) In the one-shot pulse output mode, 16-bit timer/event counter P waits for a trigger when the TPnCTL0.TPnCE bit is set to 1. When the valid edge of an external trigger input (TIPn0) is detected, 16-bit timer/event counter P starts counting, and outputs a one-shot pulse from the TOPn1 pin.
Page 440 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-27. Basic Timing in One-Shot Pulse Output Mode FFFFH 16-bit counter 0000H TPnCE bit External trigger input (TIPn0 pin input) TPnCCR0 register INTTPnCC0 signal TOPn0 pin output (only when software trigger is used) TPnCCR1 register INTTPnCC1 signal TOPn1 pin output...
Page 441 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-28. Setting of Registers in One-Shot Pulse Output Mode (1/2) (a) TMPn control register 0 (TPnCTL0) TPnCE TPnCKS2 TPnCKS1 TPnCKS0 TPnCTL0 Select count clock 0: Stop counting 1: Enable counting (b) TMPn control register 1 (TPnCTL1) TPnEST TPnEEE TPnMD2 TPnMD1 TPnMD0...
Page 442 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-28. Setting of Registers in One-Shot Pulse Output Mode (2/2) (d) TMPn I/O control register 2 (TPnIOC2) TPnEES1 TPnEES0 TPnETS1 TPnETS0 TPnIOC2 Select valid edge of external trigger input (TIPn0 pin) (e) TMPn counter read buffer register (TPnCNT) The value of the 16-bit counter can be read by reading the TPnCNT register.
Page 443 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Operation flow in one-shot pulse output mode Figure 7-29. Software Processing Flow in One-Shot Pulse Output Mode FFFFH 16-bit counter 0000H TPnCE bit External trigger input (TIPn0 pin input) TPnCCR0 register INTTPnCC0 signal TPnCCR1 register INTTPnCC1 signal TOPn1 pin output...
Page 444 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Operation timing in one-shot pulse output mode (a) Note on rewriting TPnCCRa register If the value of the TPnCCRa register is rewritten to a smaller value during counting, the 16-bit counter may overflow.
Page 445 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) Generation timing of compare match interrupt request signal (INTTPnCC1) The generation timing of the INTTPnCC1 signal in the one-shot pulse output mode is different from other mode INTTPnCC1 signals; the INTTPnCC1 signal is generated when the count value of the 16-bit counter matches the value of the TPnCCR1 register.
Page 446: Pwm Output Mode (Tpnmd2 To Tpnmd0 Bits = 100)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.6.5 PWM output mode (TPnMD2 to TPnMD0 bits = 100) In the PWM output mode, a PWM waveform is output from the TOPn1 pin when the TPnCTL0.TPnCE bit is set to 1. In addition, a square wave with a duty factor of 50% with the set value of the TPnCCR0 register + 1 as half its cycle is output from the TOPn0 pin.
Page 447 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-31. Basic Timing in PWM Output Mode FFFFH 16-bit counter 0000H TPnCE bit TPnCCR0 register CCR0 buffer register INTTPnCC0 signal TOPn0 pin output TPnCCR1 register CCR1 buffer register INTTPnCC1 signal TOPn1 pin output Active period Cycle Inactive period...
Page 448 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-32. Setting of Registers in PWM Output Mode (1/2) (a) TMPn control register 0 (TPnCTL0) TPnCE TPnCKS2 TPnCKS1 TPnCKS0 TPnCTL0 Note Select count clock 0: Stop counting 1: Enable counting Note The setting is invalid when the TPnCTL1.TPnEEE bit = 1. (b) TMPn control register 1 (TPnCTL1) TPnEST TPnEEE...
Page 449 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-32. Register Setting in PWM Output Mode (2/2) (d) TMPn I/O control register 2 (TPnIOC2) TPnEES1 TPnEES0 TPnETS1 TPnETS0 TPnIOC2 Select valid edge of external event count input (TIPn0 pin). (e) TMPn counter read buffer register (TPnCNT) The value of the 16-bit counter can be read by reading the TPnCNT register.
Page 450 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Operation flow in PWM output mode Figure 7-33. Software Processing Flow in PWM Output Mode (1/2) FFFFH 16-bit counter 0000H TPnCE bit TPnCCR0 register CCR0 buffer register INTTPnCC0 signal TOPn0 pin output TPnCCR1 register CCR1 buffer register INTTPnCC1 signal...
Page 451 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-33. Software Processing Flow in PWM Output Mode (2/2) <1> Count operation start flow <3> TPnCCR0, TPnCCR1 register setting change flow (duty only) Only writing of the TPnCCR1 START register must be performed when the set duty factor is changed.
Page 452 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) PWM output mode operation timing (a) Changing pulse width during operation To change the PWM waveform while the counter is operating, write the TPnCCR1 register last. Rewrite the TPnCCRa register after writing the TPnCCR1 register after the INTTPnCC0 signal is detected. FFFFH 16-bit counter 0000H...
Page 453 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TPnCCR1 register to 0000H. The 16-bit counter is cleared to 0000H and the INTTPnCC0 and INTTPnCC1 signals are generated at the next timing after a match between the count value of the 16-bit counter and the value of the CCR0 buffer register.
Page 454 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Generation timing of compare match interrupt request signal (INTTPnCC1) The timing of generation of the INTTPnCC1 signal in the PWM output mode differs from the timing of other mode INTTPnCC1 signals; the INTTPnCC1 signal is generated when the count value of the 16-bit counter matches the value of the TPnCCR1 register.
Page 455: Free-Running Timer Mode (Tpnmd2 To Tpnmd0 Bits = 101)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.6.6 Free-running timer mode (TPnMD2 to TPnMD0 bits = 101) In the free-running timer mode, 16-bit timer/event counter P starts counting when the TPnCTL0.TPnCE bit is set to 1. At this time, the TPnCCRa register can be used as a compare register or a capture register, depending on the setting of the TPnOPT0.TPnCCS0 and TPnOPT0.TPnCCS1 bits.
Page 456 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) • Compare operation When the TPnCE bit is set to 1, 16-bit timer/event counter P starts counting, and the output signals of the TOPn0 and TOPn1 pins are inverted. When the count value of the 16-bit counter later matches the set value of the TPnCCRa register, a compare match interrupt request signal (INTTPnCCa) is generated, and the output signal of the TOPna pin is inverted.
Page 457 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) • Capture operation When the TPnCE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIPna pin is detected, the count value of the 16-bit counter is stored in the TPnCCRa register, and a capture interrupt request signal (INTTPnCCa) is generated.
Page 458 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-37. Register Setting in Free-Running Timer Mode (1/3) (a) TMPn control register 0 (TPnCTL0) TPnCE TPnCKS2 TPnCKS1 TPnCKS0 TPnCTL0 Note Select count clock 0: Stop counting 1: Enable counting Note The setting is invalid when the TPnCTL1.TPnEEE bit = 1 (b) TMPn control register 1 (TPnCTL1) TPnEST TPnEEE...
Page 459 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-37. Register Setting in Free-Running Timer Mode (2/3) (d) TMPn I/O control register 1 (TPnIOC1) TPnIS3 TPnIS2 TPnIS1 TPnIS0 TPnIOC1 Select valid edge Note of TIPn0 pin input Select valid edge of TIPn1 pin input Note Set the valid edge selection of the unused alternate external input signals to “No edge detection”.
Page 460 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-37. Register Setting in Free-Running Timer Mode (3/3) (h) TMPn capture/compare registers 0 and 1 (TPnCCR0 and TPnCCR1) These registers function as capture registers or compare registers depending on the setting of the TPnOPT0.TPnCCSa bit.
Page 461 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Operation flow in free-running timer mode (a) When using capture/compare register as compare register Figure 7-38. Software Processing Flow in Free-Running Timer Mode (Compare Function) (1/2) FFFFH 16-bit counter 0000H TPnCE bit TPnCCR0 register INTTPnCC0 signal TOPn0 pin output...
Page 462 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-38. Software Processing Flow in Free-Running Timer Mode (Compare Function) (2/2) <1> Count operation start flow START Register initial setting Initial setting of these registers TPnCTL0 register is performed before setting the (TPnCKS0 to TPnCKS2 bits) TPnCE bit to 1.
Page 463 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) When using capture/compare register as capture register Figure 7-39. Software Processing Flow in Free-Running Timer Mode (Capture Function) (1/2) FFFFH 16-bit counter 0000H TPnCE bit TIPn0 pin input TPnCCR0 register 0000 0000 INTTPnCC0 signal TIPn1 pin input 0000...
Page 464 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-39. Software Processing Flow in Free-Running Timer Mode (Capture Function) (2/2) <1> Count operation start flow START Register initial setting Initial setting of these registers TPnCTL0 register is performed before setting the (TPnCKS0 to TPnCKS2 bits) TPnCE bit to 1.
Page 465 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Operation timing in free-running timer mode (a) Interval operation with compare register When 16-bit timer/event counter P is used as an interval timer with the TPnCCRa register used as a compare register, software processing is necessary for setting a comparison value to generate the next interrupt request signal each time the INTTPnCCa signal has been detected.
Page 466 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) Pulse width measurement with capture register When pulse width measurement is performed with the TPnCCRa register used as a capture register, software processing is necessary for reading the capture register each time the INTTPnCCa signal has been detected and for calculating an interval.
Page 467 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Processing of overflow when two capture registers are used Care must be exercised in processing the overflow flag when two capture registers are used. First, an example of incorrect processing is shown below. Example of incorrect processing when two capture registers are used FFFFH 16-bit counter...
Page 468 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1/2) Example when two capture registers are used (using overflow interrupt) FFFFH 16-bit counter 0000H TPnCE bit INTTPnOV signal TPnOVF bit Note TPnOVF0 flag TIPn0 pin input TPnCCR0 register Note TPnOVF1 flag TIPn1 pin input TPnCCR1 register <1>...
Page 469 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2/2) Example when two capture registers are used (without using overflow interrupt) FFFFH 16-bit counter 0000H TPnCE bit INTTPnOV signal TPnOVF bit Note TPnOVF0 flag TIPn0 pin input TPnCCR0 register Note TPnOVF1 flag TIPn1 pin input TPnCCR1 register <1>...
Page 470 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (d) Processing of overflow if capture trigger interval is long If the pulse width is greater than one cycle of the 16-bit counter, care must be exercised because an overflow may occur more than once from the first capture trigger to the next. First, an example of incorrect processing is shown below.
Page 471 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Example when capture trigger interval is long FFFFH 16-bit counter 0000H TPnCE bit TIPna pin input TPnCCRa register INTTPnOV signal TPnOVF bit Overflow 2H 0H Note counter 1 cycle of 16-bit counter Pulse width <1>...
Page 472 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (e) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TPnOVF bit to 0 with the CLR instruction after reading the TPnOVF bit when it is 1 and by writing 8-bit data (bit 0 is 0) to the TPnOPT0 register after reading the TPnOVF bit when it is 1.
Page 473: Pulse Width Measurement Mode (Tpnmd2 To Tpnmd0 Bits = 110)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.6.7 Pulse width measurement mode (TPnMD2 to TPnMD0 bits = 110) In the pulse width measurement mode, 16-bit timer/event counter P starts counting when the TPnCTL0.TPnCE bit is set to 1. Each time the valid edge input to the TIPna pin has been detected, the count value of the 16-bit counter is stored in the TPnCCRa register, and the 16-bit counter is cleared to 0000H.
Page 474 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-41. Basic Timing in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TPnCE bit TIPna pin input 0000H TPnCCRa register INTTPnCCa signal INTTPnOV signal Cleared to 0 by TPnOVF bit CLR instruction Remark n = 0 to 8 a = 0, 1...
Page 475 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-42. Register Setting in Pulse Width Measurement Mode (1/2) (a) TMPn control register 0 (TPnCTL0) TPnCE TPnCKS2 TPnCKS1 TPnCKS0 TPnCTL0 Select count clock 0: Stop counting 1: Enable counting (b) TMPn control register 1 (TPnCTL1) TPnEST TPnEEE TPnMD2 TPnMD1 TPnMD0...
Page 476 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-42. Register Setting in Pulse Width Measurement Mode (2/2) (d) TMPn option register 0 (TPnOPT0) TPnCCS1 TPnCCS0 TPnOVF TPnOPT0 Overflow flag (e) TMPn counter read buffer register (TPnCNT) The value of the 16-bit counter can be read by reading the TPnCNT register. (f) TMPn capture/compare registers 0 and 1 (TPnCCR0 and TPnCCR1) These registers store the count value of the 16-bit counter when the valid edge input to the TIPna pin is detected.
Page 477 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Operation flow in pulse width measurement mode Figure 7-43. Software Processing Flow in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TPnCE bit TIPn0 pin input TPnCCR0 register 0000H 0000H INTTPnCC0 signal <1>...
Page 478 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Operation timing in pulse width measurement mode (a) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TPnOVF bit to 0 with the CLR instruction after reading the TPnOVF bit when it is 1 and by writing 8-bit data (bit 0 is 0) to the TPnOPT0 register after reading the TPnOVF bit when it is 1.
Page 479: Encoder Count Function (Only For Tmp7 And Tmp8)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.6.8 Encoder count function (only for TMP7 and TMP8) The encoder count function includes an encoder compare mode (see 7.6.9 Encoder compare mode (TPmMD3 to TPmMD0 bits = 1000)). Mode TPmCCR0 Register TPmCCR1 Register Encoder compare mode Compare only Compare only...
Page 480 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (5) Controlling bits of TPmCTL2 register The setting of the TPmCTL2 register in the encoder compare mode is shown below. Table 7-7. Setting of TPmCTL2 Register Mode TPmUDS1, TPmECM1 Bit TPmECM0 Bit TPmLDE Bit Counter Clear Transfer to TPmUDS0 Bits...
Page 481 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) Detailed explanation of each bit <1> TPmUDS1 and TPmUDS0 bits: Count-up/-down selection Whether the 16-bit counter is counting up or down is identified by the phase input from the TENCm0 or TENCm1 pin and depending on the setting of the TPmUDS1 and TPmUDS0 bits. These bits are valid only in the encoder compare mode.
Page 482 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) • When TPmUDS1 and TPmUDS0 bits = 01 TENCm0 Pin TENCm1 Pin Count Operation Low level Rising edge Count down Falling edge Both edges High level Rising edge Falling edge Both edges Rising edge High level Count up Falling edge...
Page 483 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) • When TPmUDS1 and TPmUDS0 bits = 10 TENCm0 Pin TENCm1 Pin Count Operation Low level Falling edge Counter does not perform count operation but holds value immediately before. Rising edge Low level Count down High level Rising edge...
Page 484 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) • When TPmUDS1 and TPmUDS0 bits = 11 TENCm0 Pin TENCm1 Pin Count Operation Low level Falling edge Count down Rising edge Low level High level Rising edge High level Falling edge Rising edge Count up High level Falling edge...
Page 485 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) <2> TPmECM1 and TPmECM0 bits: Timer/counter clear function upon match of the compare register The 16-bit counter performs its count operation in accordance with the set value of the TPmECM1 and TPmECM0 bits when the count value of the counter matches the value of the CCRa buffer register.
Page 486 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) <3> TPmLDE bit: Transfer function of the set value of the TPmCCR0 register to the 16-bit counter when the counter underflows When the TPmLDE bit = 1, the set value of the TPmCCR0 register can be transferred to the 16-bit counter when the counter underflows.
Page 487 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-51. Operation Timing (Count Operation in Range from 0000H to Set Value of TPmCCR0 Register) Peripheral clock Count timing signal H = down counting TPmESF bit − 0002H 0001H 0000H TPmCNT register TPmCCR0 register INTTPmCC0 signal TPmEOF bit...
Page 488 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (6) Clearing counter to 0000H by encoder clear signal (TECRm pin) The 16-bit counter can be cleared to 0000H by the input signal of the TECRm pin in two ways which are selected by the TPmIOC3.TPmSCE bit. The TPmSCE bit also controls, depending its setting, the TPmIOC3.TPmZCL, TPmIOC3.TPmBCL,...
Page 489 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) Clearing method <2>: By detecting clear level condition of the TENCm0, TENCm1, and TECRm pins (TPmSCE bit = 1) When the TPmSCE bit = 1, the 16-bit counter is cleared to 0000H if the clear level condition of the TECRm, TENCm0, or TENCm1 pin specified by the TPmZCL, TPmBCL, and TPmACL bits is detected.
Page 490 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-53. Operation Example (When TPmSCE Bit = 1, TPmZCL Bit = 1, TPmBCL Bit = 0, TPmACL Bit = 1, TPmUDS1 and TPmUDS0 Bits = 11, TECRm = High Level, TENCm1 = Low Level, and TENCm0 = High Level) (1/3) (i) If inputting the high level to the TECRm pin lags behind inputting the low level to the TENCm1 pin while the counter is counting up, the counter is cleared after it counts up.
Page 491 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-53. Operation Example (When TPmSCE Bit = 1, TPmZCL Bit = 1, TPmBCL Bit = 0, TPmACL Bit = 1, TPmUDS1 and TPmUDS0 Bits = 11, TECRm = High Level, TENCm1 = Low Level, and TENCm0 = High Level) (2/3) (ii) If the high level is input to the TECRm pin at the same time as the low level is input to the TECNm1 pin while the counter is counting up, the counter is cleared without counting up.
Page 492 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-53. Operation Example (When TPmSCE Bit = 1, TPmZCL Bit = 1, TPmBCL Bit = 0, TPmACL Bit = 1, TPmUDS1 and TPmUDS0 Bits = 11, TECRm = High Level, TENCm1 = Low Level, and TENCm0 = High Level) (3/3) (iv) If the high level is input to the TECRm pin later than the low level is input to the TENCm1 pin while the counter is counting up, the counter is cleared after it counts up.
Page 493: Encoder Compare Mode (Tpmmd3 To Tpmmd0 Bits = 1000)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.6.9 Encoder compare mode (TPmMD3 to TPmMD0 bits = 1000) In the encoder compare mode, the encoder is controlled by using both the TPmCCR0 and TPmCCR1 registers as compare registers and the input pins for encoder count function (TENCm0, TENCm1, and TECRm). In this mode, the 16-bit counter can be cleared to 0000H in three ways: when the count value of the counter matches the value of the CCRa buffer register (compare match interrupt request signal (INTTPmCCa) is generated), when the edge of the encoder clear input (TECRm pin) is detected and cleared, and when the clear level condition of...
Page 494 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-55. Encoder Compare Mode Operation Processing Valid edge of TENCm0, TENCm1 detected? Count down Which count operation? Count up TPmECM0 = 1? TPmECM1 = 1? (TPmCTL2) (TPmCTL2) Count value matches Count value matches CCR0 register value? CCR1 register value? 16-bit counter cleared...
Page 495 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Encoder compare mode operation timing (a) Basic timing 1 [Register setting conditions] • TPmCTL2.TPmECM1 and TPmCTL2.TPmECM0 bits = 01 The 16-bit counter is cleared to 0000H when its count value matches the value of the CCR0 buffer register.
Page 496 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) When the 16-bit counter starts operating (TPmCE bit = 0 → 1), the set value of the TPmTCW register is transferred to the counter and the 16-bit counter starts operating. When the count value of the counter matches the value of the CCR0 buffer register, the compare match interrupt request signal (INTTPmCC0) is generated.
Page 497 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) Basic timing 2 [Register setting condition] • TPmCTL2.TPmECM1 and TPmCTL2.TPmECM0 bits = 00 The 16-bit counter is not cleared even when its count value matches the value of the CCRa buffer register (a = 0, 1). •...
Page 498 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) When the 16-bit counter starts operating (TPmCE bit = 0 → 1), the set value of the TPmTCW register is transferred to the 16-bit counter and the counter starts operating. When the count value of the 16-bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal (INTTPmCC0) is generated.
Page 499 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Basic timing 3 [Register setting condition] • TPmCTL2.TPmECM1 and TPmCTL2.TPmECM0 bits = 11 The count value of the 16-bit counter is cleared to 0000H when its value matches the value of the CCR0 buffer register.
Page 500 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) When the 16-bit counter starts operating (TPmCE bit = 0 → 1), the set value of the TPmTCW register is transferred to the 16-bit counter and the counter starts operating. When the count value of the 16-bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal (INTTPmCC0) is generated.
Page 501: Selector Function
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Selector Function Note In the V850E/SJ3-H and V850E/SK3-H, the TIP input or RXDA input and the TIQ input or TSOUT signal can be selected as the capture trigger input of TMP and TMQ, respectively. By using this function, the following is possible.
Page 502 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Selector operation control register 0 (SELCNT0) The SELCNT0 register is an 8-bit register that selects the capture trigger for TMP1, TMP3, and TMQ0. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 503: Cautions
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Cautions (1) DMA transfer start factors In the V850E/SJ3-H and V850E/SK3-H, the DMA transfer start factors INTTP0OV signal and INTUB0TIT signal, INTTP1OV signal and INTUB1TIR signal, and INTTP2OV signal and INTUB1TIT signal are used alternately and cannot be used simultaneously.
Page 504: Chapter 8 16-Bit Timer/Event Counter Q (Tmq)
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Timer Q (TMQ) is a 16-bit timer/event counter. The V850E/SJ3-H and V850E/SK3-H incorporate TMQ0. Overview An outline of TMQ0 is shown below. • Clock selection: 8 ways • Capture/trigger input pins: 4 • External event count input pin: 1 •...
Page 505: Configuration
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Configuration TMQ0 includes the following hardware. Table 8-1. Configuration of TMQ0 Item Configuration Timer register 16-bit counter Registers TMQ0 capture/compare registers 0 to 3 (TQ0CCR0 to TQ0CCR3) TMQ0 counter read buffer register (TQ0CNT) CCR0 to CCR3 buffer registers Note 1 Timer inputs...
Page 506 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-1. Block Diagram of TMQ0 Internal bus TQ0CNT INTTQ0OV 16-bit counter Clear TOQ00 TOQ01 /128 TOQ02 CCR0 buffer TOQ03 register CCR1 buffer INTTQ0CC0 register CCR2 INTTQ0CC1 buffer TIQ00 TQ0CCR0 register INTTQ0CC2 CCR3 buffer INTTQ0CC3 TIQ01...
Page 507 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (3) CCR1 buffer register This is a 16-bit compare register that compares the count value of the 16-bit counter. When the TQ0CCR1 register is used as a compare register, the value written to the TQ0CCR1 register is transferred to the CCR1 buffer register.
Page 508: Registers
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Registers The registers that control TMQ0 are as follows. • TMQ0 control register 0 (TQ0CTL0) • TMQ0 control register 1 (TQ0CTL1) • TMQ0 I/O control register 0 (TQ0IOC0) • TMQ0 I/O control register 1 (TQ0IOC1) •...
Page 509 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) TMQ0 control register 0 (TQ0CTL0) The TQ0CTL0 register is an 8-bit register that controls the operation of TMQ0. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. The same value can always be written to the TQ0CTL0 register by software.
Page 510 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) TMQ0 control register 1 (TQ0CTL1) The TQ0CTL1 register is an 8-bit register that controls the operation of TMQ0. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H Address: FFFFF541H...
Page 511 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (3) TMQ0 I/O control register 0 (TQ0IOC0) The TQ0IOC0 register is an 8-bit register that controls the timer output (TOQ00 to TOQ03 pins). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 512 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (4) TMQ0 I/O control register 1 (TQ0IOC1) The TQ0IOC1 register is an 8-bit register that controls the valid edge of the capture trigger input signals (TIQ00 to TIQ03 pins). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 513 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (5) TMQ0 I/O control register 2 (TQ0IOC2) The TQ0IOC2 register is an 8-bit register that controls the valid edge of the external event count input signal (TIQ00 pin) and external trigger input signal (TIQ00 pin). This register can be read or written in 8-bit or 1-bit units.
Page 514 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (6) TMQ0 option register 0 (TQ0OPT0) The TQ0OPT0 register is an 8-bit register used to set the capture/compare operation and detect an overflow. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 515 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (7) TMQ0 capture/compare register 0 (TQ0CCR0) The TQ0CCR0 register is a 16-bit register that can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TQ0OPT0.TQ0CCS0 bit.
Page 516 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (a) Function as compare register The TQ0CCR0 register can be rewritten even when the TQ0CTL0.TQ0CE bit = 1. The set value of the TQ0CCR0 register is transferred to the CCR0 buffer register. When the value of the 16-bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal (INTTQ0CC0) is generated.
Page 517 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (8) TMQ0 capture/compare register 1 (TQ0CCR1) The TQ0CCR1 register is a 16-bit register that can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TQ0OPT0.TQ0CCS1 bit.
Page 518 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (a) Function as compare register The TQ0CCR1 register can be rewritten even when the TQ0CTL0.TQ0CE bit = 1. The set value of the TQ0CCR1 register is transferred to the CCR1 buffer register. When the value of the 16-bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTQ0CC1) is generated.
Page 519 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (9) TMQ0 capture/compare register 2 (TQ0CCR2) The TQ0CCR2 register is a 16-bit register that can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TQ0OPT0.TQ0CCS2 bit.
Page 520 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (a) Function as compare register The TQ0CCR2 register can be rewritten even when the TQ0CTL0.TQ0CE bit = 1. The set value of the TQ0CCR2 register is transferred to the CCR2 buffer register. When the value of the 16-bit counter matches the value of the CCR2 buffer register, a compare match interrupt request signal (INTTQ0CC2) is generated.
Page 521 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (10) TMQ0 capture/compare register 3 (TQ0CCR3) The TQ0CCR3 register is a 16-bit register that can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TQ0OPT0.TQ0CCS3 bit.
Page 522 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (a) Function as compare register The TQ0CCR3 register can be rewritten even when the TQ0CTL0.TQ0CE bit = 1. The set value of the TQ0CCR3 register is transferred to the CCR3 buffer register. When the value of the 16-bit counter matches the value of the CCR3 buffer register, a compare match interrupt request signal (INTTQ0CC3) is generated.
Page 523: Timer Output Operations
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (11) TMQ0 counter read buffer register (TQ0CNT) The TQ0CNT register is a read buffer register that can read the count value of the 16-bit counter. If this register is read when the TQ0CTL0.TQ0CE bit = 1, the count value of the 16-bit timer can be read. This register is read-only, in 16-bit units.
Page 524: Operation
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Table 8-7. Truth Table of TOQ00 to TOQ03 Pins Under Control of Timer Output Control Bits TQ0IOC0.TQ0OLm Bit TQ0IOC0.TQ0OEm Bit TQ0CTL0.TQ0CE Bit Level of TOQ0m Pin × Low-level output Low-level output Low level immediately before counting, high level after counting is started ×...
Page 525 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) Counter basic operation This section explains the basic operation of the 16-bit counter. For details, refer to the description of the operation in each mode. (a) Counter start operation • External event count mode When the TQ0CE bit value is changed from 0 to 1, the value of 0000H is set to the 16-bit counter.
Page 526 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (e) Interrupt operation TMQ0 generates the following five interrupt request signals. • INTTQ0CC0 interrupt: This signal functions as a match interrupt request signal of the CCR0 buffer register and as a capture interrupt request signal to the TQ0CCR0 register. •...
Page 527 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) Anytime write and batch write The TQ0CCR0 to TQ0CCR3 registers can be rewritten in the TMQ0 during timer operation (TQ0CTL0.TQ0CE bit = 1), but the write method (anytime write, batch write) of the CCR0 to CCR3 buffer registers differs depending on the mode.
Page 528 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-3. Timing of Anytime Write TQ0CE bit = 1 FFFFH 16-bit counter 0000H TQ0CCR0 register CCR0 buffer 0000H register INTTQ0CC0 signal TQ0CCR1 register CCR1 buffer 0000H register INTTQ0CC1 signal TQ0CCR2 register CCR2 buffer 0000H register INTTQ0CC2...
Page 529 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (b) Batch write In this mode, data is transferred all at once from the TQ0CCR0 to TQ0CCR3 registers to the CCR0 to CCR3 buffer registers during timer operation. This data is transferred upon a match between the value of the CCR0 buffer register and the value of the 16-bit counter.
Page 530 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-4. Flowchart of Basic Operation for Batch Write START Initial settings • Set values to TQ0CCRm register • Timer operation enable (TQ0CE bit = 1) → Transfer of values of TQ0CCRm register to CCRm buffer register TQ0CCR0, TQ0CCR2, TQ0CCR3 register rewrite...
Page 531 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-5. Timing of Batch Write TQ0CE bit = 1 FFFFH 16-bit counter 0000H TQ0CCR0 register CCR0 buffer 0000H register Note 1 Note 1 Same value write TQ0CCR1 Note 2 Note 3 register CCR1 buffer 0000H register...
Page 532: Interval Timer Mode (Tq0Md2 To Tq0Md0 Bits = 000)
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) 8.6.1 Interval timer mode (TQ0MD2 to TQ0MD0 bits = 000) In the interval timer mode, an interrupt request signal (INTTQ0CC0) is generated at the interval set by the TQ0CCR0 register if the TQ0CTL0.TQ0CE bit is set to 1. A square wave with a duty factor of 50% whose half cycle is equal to the interval can be output from the TOQ00 pin.
Page 533 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) When the TQ0CE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization with the count clock, and the counter starts counting. At this time, the output of the TOQ00 pin is inverted. Additionally, the set value of the TQ0CCR0 register is transferred to the CCR0 buffer register.
Page 534 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-8. Register Setting for Interval Timer Mode Operation (2/3) (c) TMQ0 I/O control register 0 (TQ0IOC0) TQ0OL3 TQ0OE3 TQ0OL2 TQ0OE2 TQ0OL1 TQ0OE1 TQ0OL0 TQ0OE0 TQ0IOC0 0: Disable TOQ00 pin output 1: Enable TOQ00 pin output Setting of TOQ00 pin output level before count operation 0: Low level...
Page 535 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-8. Register Setting for Interval Timer Mode Operation (3/3) (g) TMQ0 capture/compare registers 1 to 3 (TQ0CCR1 to TQ0CCR3) The TQ0CCR1 to TQ0CCR3 registers are not used in the interval timer mode. However, the set value of the TQ0CCR1 to TQ0CCR3 registers are transferred to the CCR1 to CCR3 buffer registers.
Page 536 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) Interval timer mode operation flow Figure 8-9. Software Processing Flow in Interval Timer Mode FFFFH 16-bit counter 0000H TQ0CE bit TQ0CCR0 register TOQ00 pin output INTTQ0CC0 signal <1> <2> <1> Count operation start flow START Register initial setting Initial setting of these registers is performed...
Page 537 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) Interval timer mode operation timing (a) Operation if TQ0CCR0 register is set to 0000H If the TQ0CCR0 register is set to 0000H, the INTTQ0CC0 signal is generated at each count clock, and the output of the TOQ00 pin is inverted.
Page 538 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (c) Notes on rewriting TQ0CCR0 register If the value of the TQ0CCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. If there is a possibility of overflow, stop counting and then change the set value. FFFFH 16-bit counter 0000H...
Page 539 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (d) Operation of TQ0CCR1 to TQ0CCR3 registers Figure 8-10. Configuration of TQ0CCR1 to TQ0CCR3 Registers TQ0CCR1 register CCR1 buffer Output TOQ01 pin register controller Match signal INTTQ0CC1 signal TQ0CCR2 register Output CCR2 buffer TOQ02 pin controller register...
Page 540 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) If the same value as the set value of the TQ0CCR0 register is set to the TQ0CCRk register, the INTTQ0CCk signal is generated together with the INTTQ0CC0 signal, and the output of the TOQ0k pin is inverted.
Page 541 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) If the set value of the TQ0CCRk register is greater than the set value of the TQ0CCR0 register, the count value of the 16-bit counter does not match the value of the TQ0CCRk register. Consequently, the INTTQ0CCk signal is not generated, nor is the output of the TOQ0k pin changed.
Page 542 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (3) Operation by external event count input (TIQ00) (a) Operation To count the 16-bit counter at the valid edge of external event count input (TIQ00) in the interval timer mode, the valid edge of the external event count input is necessary once because the 16-bit counter is cleared from FFFFH to 0000H immediately after the TQ0CE bit is set from 0 to 1.
Page 543: External Event Count Mode (Tq0Md2 To Tq0Md0 Bits = 001)
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) 8.6.2 External event count mode (TQ0MD2 to TQ0MD0 bits = 001) In the external event count mode, the valid edge of the external event count input (TIQ00) is counted when the TQ0CTL0.TQ0CE bit is set to 1, and an interrupt request signal (INTTQ0CC0) is generated each time the specified number of edges set by the TQ0CCR0 register have been counted.
Page 544 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-14. Basic Timing in External Event Count Mode FFFFH 16-bit counter − 1 16-bit counter 0000 0001 0000H External event count input TQ0CE bit (TIQ00 pin input) TQ0CCR0 register TQ0CCR0 register NTTQ0CC0 signal INTTQ0CC0 signal Number Number...
Page 545 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) When the TQ0CE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H. The counter counts each time the valid edge of external event count input is detected. Additionally, the set value of the TQ0CCR0 register is transferred to the CCR0 buffer register.
Page 546 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-15. Register Setting for Operation in External Event Count Mode (2/2) (e) TMQ0 capture/compare register 0 (TQ0CCR0) If the TQ0CCR0 register is set to D , the count is cleared when the number of external events has reached (D ) and the first compare match interrupt request signal (INTTQ0CC0) is generated.
Page 547 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) External event count mode operation flow Figure 8-16. Flow of Software Processing in External Event Count Mode FFFFH 16-bit counter 0000H TQ0CE bit TQ0CCR0 register INTTQ0CC0 signal <1> <2> <1> Count operation start flow START Register initial setting Initial setting of these registers...
Page 548 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) Operation timing in external event count mode Cautions 1. In the external event count mode, setting the TQ0CCR0 to TQ0CCR3 registers to 0000H is disabled. 2. In the external event count mode, use of the timer output (TOQ00 to TOQ03) is disabled. If performing external event count input (TIQ00) using the timer outputs (TOQ01 to TOQ03), set the interval timer mode to enable the count clock operation (TQ0CTL1.TQ0EEE bit = 1) for the external event count input (refer to 8.6.1 (3) Operation by external event count...
Page 549 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (b) Notes on rewriting the TQ0CCR0 register If the value of the TQ0CCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. If there is a possibility of overflow, stop counting and then change the set value. FFFFH 16-bit counter 0000H...
Page 550 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (c) Operation of TQ0CCR1 to TQ0CCR3 registers Figure 8-17. Configuration of TQ0CCR1 to TQ0CCR3 Registers TQ0CCR1 register CCR1 buffer register Match signal INTTQ0CC1 signal TQ0CCR2 register CCR2 buffer register Match signal INTTQ0CC2 signal TQ0CCR3 register CCR3 buffer...
Page 551 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) If the set value of the TQ0CCRk register is smaller than the set value of the TQ0CCR0 register, the INTTQ0CCk signal is generated once per cycle. Remark k = 1 to 3 ≥ D Figure 8-18.
Page 552 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) If the set value of the TQ0CCRk register is greater than the set value of the TQ0CCR0 register, the INTTQ0CCk signal is not generated because the count value of the 16-bit counter and the value of the TQ0CCRk register do not match.
Page 553: External Trigger Pulse Output Mode (Tq0Md2 To Tq0Md0 Bits = 010)
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) 8.6.3 External trigger pulse output mode (TQ0MD2 to TQ0MD0 bits = 010) In the external trigger pulse output mode, 16-bit timer/event counter Q waits for a trigger when the TQ0CTL0.TQ0CE bit is set to 1. When the valid edge of an external trigger input signal (TIQ00) is detected, 16-bit timer/event counter Q starts counting, and outputs a PWM waveform from the TOQ01 to TOQ03 pins.
Page 554 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-21. Basic Timing in External Trigger Pulse Output Mode FFFFH 16-bit counter 0000H TQ0CE bit External trigger input (TIQ00 pin input) TQ0CCR0 register INTTQ0CC0 signal TOQ00 pin output (only when software trigger is used) TQ0CCR1 register INTTQ0CC1 signal TOQ01 pin output...
Page 555 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) 16-bit timer/event counter Q waits for a trigger when the TQ0CE bit is set to 1. When the trigger is generated, the 16-bit counter is cleared from FFFFH to 0000H, starts counting at the same time, and outputs a PWM waveform from the TOQ0k pin.
Page 556 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-22. Setting of Registers in External Trigger Pulse Output Mode (2/3) (b) TMQ0 control register 1 (TQ0CTL1) TQ0EST TQ0EEE TQ0MD2 TQ0MD1 TQ0MD0 TQ0CTL1 0, 1, 0: External trigger pulse output mode 0: Operate on count clock selected by TQ0CKS0 to TQ0CKS2 bits Generate software trigger...
Page 557 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-22. Setting of Registers in External Trigger Pulse Output Mode (3/3) (d) TMQ0 I/O control register 2 (TQ0IOC2) TQ0EES1 TQ0EES0 TQ0ETS1 TQ0ETS0 TQ0IOC2 Select valid edge of external trigger input (TIQ00 pin) (e) TMQ0 counter read buffer register (TQ0CNT) The value of the 16-bit counter can be read by reading the TQ0CNT register.
Page 558 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) Operation flow in external trigger pulse output mode Figure 8-23. Software Processing Flow in External Trigger Pulse Output Mode (1/2) FFFFH 16-bit counter 0000H TQ0CE bit External trigger input (TIQ00 pin input) TQ0CCR0 register CCR0 buffer register INTTQ0CC0 signal...
Page 559 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-23. Software Processing Flow in External Trigger Pulse Output Mode (2/2) <1> Count operation start flow <4> TQ0CCR1 to TQ0CCR3 register setting change flow Writing of the TQ0CCR1 START Setting of TQ0CCR2, register must be performed TQ0CCR3 registers when the set duty factor is only...
Page 560 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) External trigger pulse output mode operation timing (a) Note on changing pulse width during operation To change the PWM waveform while the counter is operating, write the TQ0CCR1 register last. Rewrite the TQ0CCRk register after writing the TQ0CCR1 register after the INTTQ0CC0 signal is detected. FFFFH 16-bit counter 0000H...
Page 561 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) In order to transfer data from the TQ0CCRm register to the CCRm buffer register, the TQ0CCR1 register must be written. To change both the cycle and active level width of the PWM waveform at this time, first set the cycle to the TQ0CCR0 register, set the active level width to the TQ0CCR2 and TQ0CCR3 registers, and then set an active level to the TQ0CCR1 register.
Page 562 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TQ0CCRk register to 0000H. The 16-bit counter is cleared to 0000H and the INTTQ0CC0 and INTTQ0CCk signals are generated at the next timing after a match between the count value of the 16-bit counter and the value of the CCR0 buffer register.
Page 563 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (c) Conflict between trigger detection and match with CCRk buffer register If the trigger is detected immediately after the INTTQ0CCk signal is generated, the 16-bit counter is immediately cleared to 0000H, the output signal of the TOQ0k pin is asserted, and the counter continues counting.
Page 564 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (d) Conflict between trigger detection and match with CCR0 buffer register If the trigger is detected immediately after the INTTQ0CC0 signal is generated, the 16-bit counter is cleared to 0000H and continues counting up. Therefore, the active period of the TOQ0k pin is extended by time from generation of the INTTQ0CC0 signal to trigger detection.
Page 565 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (e) Generation timing of compare match interrupt request signal (INTTQ0CCk) The timing of generation of the INTTQ0CCk signal in the external trigger pulse output mode differs from the timing of other mode INTTQ0CCk signals; the INTTQ0CCk signal is generated when the count value of the 16-bit counter matches the value of the CCRk buffer register.
Page 566: One-Shot Pulse Output Mode (Tq0Md2 To Tq0Md0 Bits = 011)
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) 8.6.4 One-shot pulse output mode (TQ0MD2 to TQ0MD0 bits = 011) In the one-shot pulse output mode, 16-bit timer/event counter Q waits for a trigger when the TQ0CTL0.TQ0CE bit is set to 1. When the valid edge of an external trigger input (TIQ00) is detected, 16-bit timer/event counter Q starts counting, and outputs a one-shot pulse from the TOQ01 to TOQ03 pins.
Page 567 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-25. Basic Timing in One-Shot Pulse Output Mode FFFFH 16-bit counter 0000H TQ0CE bit External trigger input (TIQ00 pin input) TQ0CCR0 register INTTQ0CC0 signal TOQ00 pin output (only when software trigger is used) TQ0CCR1 register INTTQ0CC1 signal TOQ01 pin output...
Page 568 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) When the TQ0CE bit is set to 1, 16-bit timer/event counter Q waits for a trigger. When the trigger is generated, the 16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a one-shot pulse from the TOQ0k pin. After the one-shot pulse is output, the 16-bit counter is set to 0000H, stops counting, and waits for a trigger.
Page 569 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-26. Register Setting in One-Shot Pulse Output Mode (2/3) (c) TMQ0 I/O control register 0 (TQ0IOC0) TQ0OL3 TQ0OE3 TQ0OL2 TQ0OE2 TQ0OL1 TQ0OE1 TQ0OL0 TQ0OE0 Note TQ0IOC0 0: Disable TOQ00 pin output 1: Enable TOQ00 pin output Setting of TOQ00 pin output level in status of waiting for external trigger 0: Low level...
Page 570 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-26. Register Setting in One-Shot Pulse Output Mode (3/3) (e) TMQ0 counter read buffer register (TQ0CNT) The value of the 16-bit counter can be read by reading the TQ0CNT register. (f) TMQ0 capture/compare registers 0 to 3 (TQ0CCR0 to TQ0CCR3) If D is set to the TQ0CCR0 register and D to the TQ0CCRk register, the active level width and output...
Page 571 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) Operation flow in one-shot pulse output mode Figure 8-27. Software Processing Flow in One-Shot Pulse Output Mode (1/2) FFFFH 16-bit counter 0000H TQ0CE bit External trigger input (TIQ00 pin input) TQ0CCR0 register INTTQ0CC0 signal TOQ00 pin output (only when software...
Page 572 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-27. Software Processing Flow in One-Shot Pulse Output Mode (2/2) <1> Count operation start flow <2> TQ0CCR0 to TQ0CCR3 register setting change flow As rewriting the TQ0CCRm register START immediately forwards to the CCRm buffer Setting of TQ0CCR0 to TQ0CCR3 register, rewriting registers...
Page 573 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) Operation timing in one-shot pulse output mode (a) Note on rewriting TQ0CCRm register If the value of the TQ0CCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow.
Page 574 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (b) Generation timing of compare match interrupt request signal (INTTQ0CCk) The generation timing of the INTTQ0CCk signal in the one-shot pulse output mode is different from other mode INTTQ0CCk signals; the INTTQ0CCk signal is generated when the count value of the 16-bit counter matches the value of the TQ0CCRk register.
Page 575: Pwm Output Mode (Tq0Md2 To Tq0Md0 Bits = 100)
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) 8.6.5 PWM output mode (TQ0MD2 to TQ0MD0 bits = 100) In the PWM output mode, a PWM waveform is output from the TOQ01 to TOQ03 pins when the TQ0CTL0.TQ0CE bit is set to 1. In addition, a square wave with a duty factor of 50% with the set value of the TQ0CCR0 register + 1 as half its cycle is output from the TOQ00 pin.
Page 576 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-29. Basic Timing in PWM Output Mode FFFFH 16-bit counter 0000H TQ0CE bit TQ0CCR0 register INTTQ0CC0 signal TOQ00 pin output TQ0CCR1 register INTTQ0CC1 signal TOQ01 pin output Active Active Active Active level width level width level width level width...
Page 577 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) When the TQ0CE bit is set to 1, the 16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs PWM waveform from the TOQ0k pin. The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows. Active level width = (Set value of TQ0CCRk register ) ×...
Page 578 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-30. Setting of Registers in PWM Output Mode (2/3) (c) TMQ0 I/O control register 0 (TQ0IOC0) TQ0OL3 TQ0OE3 TQ0OL2 TQ0OE2 TQ0OL1 TQ0OE1 TQ0OL0 TQ0OE0 Note TQ0IOC0 0: Disable TOQ00 pin output 1: Enable TOQ00 pin output Setting of TOQ00 pin output level before count operation 0: Low level...
Page 579 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-30. Register Setting in PWM Output Mode (3/3) (f) TMQ0 capture/compare registers 0 to 3 (TQ0CCR0 to TQ0CCR3) If D is set to the TQ0CCR0 register and D to the TQ0CCR1 register, the cycle and active level of the PWM waveform are as follows.
Page 580 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) Operation flow in PWM output mode Figure 8-31. Software Processing Flow in PWM Output Mode (1/2) FFFFH 16-bit counter 0000H TQ0CE bit TQ0CCR0 register CCR0 buffer register INTTQ0CC0 signal TOQ00 pin output TQ0CCR1 register CCR1 buffer register INTTQ0CC1 signal...
Page 581 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-31. Software Processing Flow in PWM Output Mode (2/2) <1> Count operation start flow <4> TQ0CCR1 to TQ0CCR3 register setting change flow Only writing of the TQ0CCR1 START Setting of TQ0CCR2, register must be performed TQ0CCR3 registers when the set duty factor is only changed after writing the...
Page 582 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) PWM output mode operation timing (a) Changing pulse width during operation To change the PWM waveform while the counter is operating, write the TQ0CCR1 register last. Rewrite the TQ0CCRm register after writing the TQ0CCR1 register after the INTTQ0CC0 signal is detected.
Page 583 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) To transfer data from the TQ0CCRm register to the CCRm buffer register, the TQ0CCR1 register must be written. To change both the cycle and active level of the PWM waveform at this time, first set the cycle to the TQ0CCR0 register, set the active level width to the TQ0CCR2 and TQ0CCR3 registers, and then set an active level width to the TQ0CCR1 register.
Page 584 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TQ0CCRk register to 0000H. The 16-bit counter is cleared to 0000H and the INTTQ0CC0 and INTQ0CCk signals are generated at the timing following the clock in which the count value of the 16-bit counter matches the value of the CCR0 buffer register.
Page 585 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (c) Generation timing of compare match interrupt request signal (INTTQ0CCk) The timing of generation of the INTTQ0CCk signal in the PWM output mode differs from the timing of other mode INTTQ0CCk signals; the INTTQ0CCk signal is generated when the count value of the 16-bit counter matches the value of the TQ0CCRk register.
Page 586: Free-Running Timer Mode (Tq0Md2 To Tq0Md0 Bits = 101)
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) 8.6.6 Free-running timer mode (TQ0MD2 to TQ0MD0 bits = 101) In the free-running timer mode, 16-bit timer/event counter Q starts counting when the TQ0CTL0.TQ0CE bit is set to 1. At this time, the TQ0CCRm register can be used as a compare register or a capture register, depending on the setting of the TQ0OPT0.TQ0CCSm bits.
Page 587 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-32. Configuration in Free-Running Timer Mode TQ0CCR3 Output Note 2 TOQ03 pin register controller (compare) TQ0CCR2 Output Note 2 TOQ02 pin register controller (compare) TQ0CCR1 Output Note 2 TOQ01 pin register controller (compare) TQ0CCR0 Output...
Page 588 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) • Compare operation When the TQ0CE bit is set to 1, 16-bit timer/event counter Q starts counting, and the output signals of the TOQ00 to TOQ03 pins are inverted. When the count value of the 16-bit counter later matches the set value of the TQ0CCRm register, a compare match interrupt request signal (INTTQ0CCm) is generated, and the output signal of the TOQ0m pin is inverted.
Page 589 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) • Capture operation When the TQ0CE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIQ0m pin is detected, the count value of the 16-bit counter is stored in the TQ0CCRm register, and a capture interrupt request signal (INTTQ0CCm) is generated.
Page 590 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-35. Register Setting in Free-Running Timer Mode (1/3) (a) TMQ0 control register 0 (TQ0CTL0) TQ0CE TQ0CKS2 TQ0CKS1 TQ0CKS0 TQ0CTL0 Note Select count clock 0: Stop counting 1: Enable counting Note The setting is invalid when the TQ0CTL1.TQ0EEE bit = 1 (b) TMQ0 control register 1 (TQ0CTL1) TQ0EST TQ0EEE...
Page 591 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-35. Register Setting in Free-Running Timer Mode (2/3) (d) TMQ0 I/O control register 1 (TQ0IOC1) TQ0IS7 TQ0IS6 TQ0IS5 TQ0IS4 TQ0IS3 TQ0IS2 TQ0IS1 TQ0IS0 TQ0IOC1 Select valid edge Note of TIQ00 pin input Select valid edge of TIQ01 pin input Select valid edge...
Page 592 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-35. Register Setting in Free-Running Timer Mode (3/3) (g) TMQ0 counter read buffer register (TQ0CNT) The value of the 16-bit counter can be read by reading the TQ0CNT register. (h) TMQ0 capture/compare registers 0 to 3 (TQ0CCR0 to TQ0CCR3) These registers function as capture registers or compare registers depending on the setting of the TQ0OPT0.TQ0CCSm bit.
Page 593 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) Operation flow in free-running timer mode (a) When using capture/compare register as compare register Figure 8-36. Software Processing Flow in Free-Running Timer Mode (Compare Function) (1/2) FFFFH 16-bit counter 0000H TQ0CE bit TQ0CCR0 register INTTQ0CC0 signal TOQ00 pin output...
Page 594 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-36. Software Processing Flow in Free-Running Timer Mode (Compare Function) (2/2) <1> Count operation start flow START Initial setting of these registers Register initial setting is performed before setting the TQ0CTL0 register TQ0CE bit to 1.
Page 595 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (b) When using capture/compare register as capture register Figure 8-37. Software Processing Flow in Free-Running Timer Mode (Capture Function) (1/2) FFFFH 16-bit counter 0000H TQ0CE bit TIQ00 pin input TQ0CCR0 register 0000 0000 INTTQ0CC0 signal TIQ01 pin input TQ0CCR1 register...
Page 596 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-37. Software Processing Flow in Free-Running Timer Mode (Capture Function) (2/2) <1> Count operation start flow START Register initial setting Initial setting of these registers TQ0CTL0 register is performed before setting the (TQ0CKS0 to TQ0CKS2 bits) TQ0CE bit to 1.
Page 597 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) Operation timing in free-running timer mode (a) Interval operation with compare register When 16-bit timer/event counter Q is used as an interval timer with the TQ0CCRm register used as a compare register, software processing is necessary for setting a comparison value to generate the next interrupt request signal each time the INTTQ0CCm signal has been detected.
Page 598 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) When performing an interval operation in the free-running timer mode, two intervals can be set with one channel. To perform the interval operation, the value of the corresponding TQ0CCRm register must be re-set in the interrupt servicing that is executed when the INTTQ0CCm signal is detected.
Page 599 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (b) Pulse width measurement with capture register When pulse width measurement is performed with the TQ0CCRm register used as a capture register, software processing is necessary for reading the capture register each time the INTTQ0CCm signal has been detected and for calculating an interval.
Page 600 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) When executing pulse width measurement in the free-running timer mode, four pulse widths can be measured with one channel. To measure a pulse width, the pulse width can be calculated by reading the value of the TQ0CCRm register in synchronization with the INTTQ0CCm signal, and calculating the difference between the read value and the previously read value.
Page 601 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (c) Processing of overflow when two or more capture registers are used Care must be exercised in processing the overflow flag when two capture registers are used. First, an example of incorrect processing is shown below. Example of incorrect processing when two or more capture registers are used FFFFH 16-bit counter...
Page 602 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1/2) Example when two capture registers are used (using overflow interrupt) FFFFH 16-bit counter 0000H TQ0CE bit INTTQ0OV signal TQ0OVF bit Note TQ0OVF0 flag TIQ00 pin input TQ0CCR0 register Note TQ0OVF1 flag TIQ01 pin input TQ0CCR1 register <1>...
Page 603 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2/2) Example when two capture registers are used (without using overflow interrupt) FFFFH 16-bit counter 0000H TQ0CE bit INTTQ0OV signal TQ0OVF bit Note TQ0OVF0 flag TIQ00 pin input TQ0CCR0 register Note TQ0OVF1 flag TIQ01 pin input TQ0CCR1 register <1>...
Page 604 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (d) Processing of overflow if capture trigger interval is long If the pulse width is greater than one cycle of the 16-bit counter, care must be exercised because an overflow may occur more than once from the first capture trigger to the next. First, an example of incorrect processing is shown below.
Page 605 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Example when capture trigger interval is long FFFFH 16-bit counter 0000H TQ0CE bit TIQ0m pin input TQ0CCRm register INTTQ0OV signal TQ0OVF bit Overflow 2H 0H Note counter 1 cycle of 16-bit counter Pulse width <1>...
Page 606 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (3) Note on capture operation If the capture operation is used and if a slow clock is selected as the count clock, FFFFH, not 0000H, may be captured to the TQ0CCRm register, or the capture operation may not be performed (capture interrupt does not occur) if the capture trigger is input immediately after the TQ0CTL0.TQ0CE bit is set to 1 (m = 0 to 3).
Page 607: Pulse Width Measurement Mode (Tq0Md2 To Tq0Md0 Bits = 110)
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) 8.6.7 Pulse width measurement mode (TQ0MD2 to TQ0MD0 bits = 110) In the pulse width measurement mode, 16-bit timer/event counter Q starts counting when the TQ0CTL0.TQ0CE bit is set to 1. Each time the valid edge input to the TIQ0m pin has been detected, the count value of the 16-bit counter is stored in the TQ0CCRm register, and the 16-bit counter is cleared to 0000H.
Page 608 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-39. Basic Timing in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TQ0CE bit TIQ0m pin input 0000H TQ0CCRm register INTTQ0CCm signal INTTQ0OV signal Cleared to 0 by TQ0OVF bit CLR instruction Remark m = 0 to 3 When the TQ0CE bit is set to 1, the 16-bit counter starts counting.
Page 609 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-40. Register Setting in Pulse Width Measurement Mode (1/2) (a) TMQ0 control register 0 (TQ0CTL0) TQ0CE TQ0CKS2 TQ0CKS1 TQ0CKS0 TQ0CTL0 Select count clock 0: Stop counting 1: Enable counting (b) TMQ0 control register 1 (TQ0CTL1) TQ0EST TQ0EEE TQ0MD2 TQ0MD1 TQ0MD0...
Page 610 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-40. Register Setting in Pulse Width Measurement Mode (2/2) (d) TMQ0 option register 0 (TQ0OPT0) TQ0CCS1 TQ0CCS0 TQ0OVF TQ0CCS3 TQ0CCS2 TQ0OPT0 Overflow flag (e) TMQ0 counter read buffer register (TQ0CNT) The value of the 16-bit counter can be read by reading the TQ0CNT register. (f) TMQ0 capture/compare registers 0 to 3 (TQ0CCR0 to TQ0CCR3) These registers store the count value of the 16-bit counter when the valid edge input to the TIQ0m pin is detected.
Page 611 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) Operation flow in pulse width measurement mode Figure 8-41. Software Processing Flow in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TQ0CE bit TIQ00 pin input TQ0CCR0 register 0000H 0000H INTTQ0CC0 signal <1>...
Page 612: Selector Function
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) Operation timing in pulse width measurement mode (a) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TQ0OVF bit to 0 with the CLR instruction after reading the TQ0OVF bit when it is 1 and by writing 8-bit data (bit 0 is 0) to the TQ0OPT0 register after reading the TQ0OVF bit when it is 1.
Page 613: Cautions
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Cautions (1) Switching of DMA transfer start factor In the V850E/SJ3-H and V850E/SK3-H, the INTTQ0OV and INTUB0TIR signals, which are the DMA transfer start factors, share the same pin, and they cannot be used at the same time. To use the INTTQ0OV signal as the DMA transfer start factor, set the DTFROB0 bit of the option byte 0000007AH to 0 (refer to CHAPTER 33 OPTION BYTE FUNCTION).
Page 614: Chapter 9 16-Bit Interval Timer M (Tmm)
CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) Timer M (TMM) is a 16-bit interval timer. The V850E/SJ3-H and V850E/SK3-H incorporate TMM0 to TMM2. Overview The TMMn has the following functions (n = 0 to 2). • Interval function • 8 clocks selectable •...
Page 615: Configuration
CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) Configuration TMMn includes the following hardware (n = 0 to 2). Table 9-1. Configuration of TMMn Item Configuration Timer register 16-bit counter Register TMMn compare register 0 (TMnCMP0) Control register TMMn control register 0 (TMnCTL0) Remark n = 0 to 2 Figure 9-1.
Page 616 CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) Figure 9-2. Block Diagram of TMM1 and TMM2 Internal bus TMmCTL0 TMmCE TMmCKS2TMmCKS1TMmCKS0 TMmCMP0 Match INTTMmEQ0 16-bit counter Controller /512 Clear INTTMaEQ0 Remarks 1. f Peripheral clock frequency (prescaler 1 input clock frequency). In clock mode 1, f In clock mode 2, f /2 (14.64 to 16 MHz)
Page 617: Register
CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) Register (1) TMMn control register 0 (TMnCTL0) The TMnCTL0 register is an 8-bit register that controls the TMMn operation. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. The same value can always be written to the TMnCTL0 register by software.
Page 618: Operation
CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) Operation Caution Do not set the TMnCMP0 register to FFFFH. 9.4.1 Interval timer mode In the interval timer mode, an interrupt request signal (INTTMnEQ0) is generated at the specified interval by the TMnCMP0 register if the TMnCTL0.TMnCE bit is set to 1. Figure 9-3.
Page 619 CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) Figure 9-5. Register Setting for Interval Timer Mode Operation (a) TMMn control register 0 (TMnCTL0) TMnCE TMnCKS2 TMnCKS1 TMnCKS0 TMnCTL0 Select count clock 0: Stop counting 1: Enable counting (b) TMMn compare register 0 (TMnCMP0) If the TMnCMP0 register is set to D , the interval is as follows.
Page 620 CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) (1) Interval timer mode operation flow Figure 9-6. Software Processing Flow in Interval Timer Mode FFFFH 16-bit counter 0000H TMnCE bit TMnCMP0 register INTTMnEQ0 signal <1> <2> <1> Count operation start flow START Initial setting of these registers is performed before setting the TMnCE bit to 1.
Page 621 CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) (2) Interval timer mode operation timing Caution Do not set the TMnCMP0 register to FFFFH. (a) Operation if TMnCMP0 register is set to 0000H If the TMnCMP0 register is set to 0000H, the INTTMnEQ0 signal is generated at each count clock. The value of the 16-bit counter is always 0000H.
Page 622: Cautions
CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) 9.4.2 Cautions (1) Maximum time before counting start It takes the 16-bit counter up to the following time to start counting after the TMnCTL0.TMnCE bit is set to 1, depending on the count clock selected. Selected Count Clock Maximum Time Before Counting Start 128/f...
Page 623: Chapter 10 Watch Functions
CHAPTER 10 WATCH FUNCTIONS This chapter explains prescaler 3, watch timer, and real-time counter (RTC). For timer M, refer to CHAPTER 9 16- BIT INTERVAL TIMER M (TMM). 10.1 Overview The V850E/SJ3-H and V850E/SK3-H realizes a watch function in the following four ways. (1) Watch timer This timer generates an interrupt request signal (INTWT) at an interval of 0.5 or 0.25 seconds by using the main oscillation clock (f...
Page 624: Configuration
CHAPTER 10 WATCH FUNCTIONS 10.2 Configuration The block diagram of the watch function is shown below. Figure 10-1. Block Diagram of Watch Function Prescaler 3 INTWT Watch timer INTRTC0 year, month, week, day, hour, minute, and second counters INTRTC1 and subcounter TMM1 INTTM1EQ0 TMM2...
Page 625: Prescaler 3
CHAPTER 10 WATCH FUNCTIONS 10.3 Prescaler 3 10.3.1 Function This prescaler generates a count clock (32.768 kHz) of the watch timer or real-time counter by dividing the main oscillation clock (f It is also used in combination with TMM1 or TMM2, or with the watch timer and TMM0 to generate an interrupt request signal (INTTMmEQ0) of a time interval of 0.5 to 0.25 seconds which is necessary for the watch function, from the main oscillation clock (f ) of any frequency (m = 0 to 2).
Page 626: Registers
CHAPTER 10 WATCH FUNCTIONS 10.3.3 Registers The following registers are provided for the prescaler 3. • Prescaler mode register 0 (PRSM0) • Prescaler compare register 0 (PRSCM0) (1) Prescaler mode register 0 (PRSM0) The PRSM0 register controls the generation of the watch timer count clock. This register can be read or written in 8-bit or 1-bit units.
Page 627 CHAPTER 10 WATCH FUNCTIONS (2) Prescaler compare register 0 (PRSCM0) The PRSCM0 register is an 8-bit compare register. This register can be read or written in 8-bit units. Reset sets this register to 00H. After reset: 00H Address: FFFFF8B1H PRSCM0 PRSCM07 PRSCM06 PRSCM05 PRSCM04 PRSCM03 PRSCM02 PRSCM01 PRSCM00 Cautions 1.
Page 628: Watch Timer Functions
CHAPTER 10 WATCH FUNCTIONS 10.4 Watch Timer Functions 10.4.1 Functions The watch timer has the following functions. • Watch timer: An interrupt request signal (INTWT) is generated at intervals of 0.5 or 0.25 seconds by using the main oscillation clock (f ) or subclock (f •...
Page 629 CHAPTER 10 WATCH FUNCTIONS (1) 11-bit prescaler This prescaler divides f to generate a clock of f to f (2) 5-bit counter This counter counts f or f , and generates a watch timer interrupt request signal at intervals of 2 , or 2 (3) Selector The watch timer has the following four selectors.
Page 630: Control Registers
CHAPTER 10 WATCH FUNCTIONS 10.4.3 Control Registers The following registers are provided for the watch timer. • Watch timer operation mode register (WTM) • Prescaler mode register 0 (PRSM0) • Prescaler compare register 0 (PRSCM0) (1) Watch timer operation mode register (WTM) The WTM register enables or disables the count clock and operation of the watch timer, sets the interval time of the prescaler, controls the operation of the 5-bit counter, and sets the set time of the watch flag.
Page 631 CHAPTER 10 WATCH FUNCTIONS (2/2) WTM7 WTM3 WTM2 Selection of set time of watch flag (0.5 s: f (0.25 s: f μ (977 s: f μ (488 s: f (0.5 s: f (0.25 s: f μ (977 s: f μ (488 s: f WTM1 Control of 5-bit counter operation...
Page 632: Operation
CHAPTER 10 WATCH FUNCTIONS 10.4.4 Operation (1) Operation as watch timer The watch timer generates an interrupt request signal (INTWT) at fixed time intervals. The watch timer operates using time intervals of 0.25 or 0.5 seconds with the subclock (f ) (32.768 kHz) or main oscillation clock (f The count operation starts when the WTM.WTM1 and WTM.WTM0 bits are set to 11.
Page 633 CHAPTER 10 WATCH FUNCTIONS Figure 10-4. Operation Timing of Watch Timer/Interval Timer 5-bit counter Overflow Overflow Start Count clock or f Watch timer interrupt INTWT Interrupt time of watch timer (0.5 s) Interrupt time of watch timer (0.5 s) Interval timer interrupt INTWTI Interval time (T) Interval time (T)
Page 634: Real-Time Counter (Rtc)
CHAPTER 10 WATCH FUNCTIONS 10.5 Real-time Counter (RTC) 10.5.1 Function The real-time counter (RTC) has the following functions. • Has year, month, week, day, hour, minute, and second counters and a subcounter, and can count up to 99 years. • The value of the year, month, week, day, hour, minute, and second counters is indicated in BCD code Note 1 •...
Page 635: Configuration
CHAPTER 10 WATCH FUNCTIONS 10.5.2 Configuration The real-time counter consists of the following hardware units. Table 10-2. Configuration of Real-Time Counter Item Configuration Control registers Real-time counter control register 0 (RC1CC0) Real-time counter control register 1 (RC1CC1) Real-time counter control register 2 (RC1CC2) Real-time counter control register 3 (RC1CC3) Subcount register (RC1SUBC) Second count register (RC1SEC)
Page 636 CHAPTER 10 WATCH FUNCTIONS Figure 10-6. Block Diagram of Real-Time Counter CLOE1 bit RC1CK1HZ Minute Hour Week alarm alarm alarm INTRTC1 INTRTC0 Count clock = 32.768 kHz 1 minute 1 hour 1 month 1 day Prescaler 3 Second Minute Year Hour Week Month...
Page 637 CHAPTER 10 WATCH FUNCTIONS (1) Pin configuration The RTC output pins constituting the real-time counter are alternate-function pins, as shown in Table 10-3. To use each of these pins, its port function must be set (refer to Table 4-25 Using Port Pin as Alternate- Function Pin).
Page 638: Registers
CHAPTER 10 WATCH FUNCTIONS 10.5.3 Registers The real-time counter is controlled by the following 16 types of registers. (1) Real-time counter control register 0 (RC1CC0) This register is used to select the input clock of the real-time counter. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 639 CHAPTER 10 WATCH FUNCTIONS After reset: 00H Address: FFFFFADEH <7> <5> <4> <3> RC1CC1 RTCE CLOE1 CLOE0 AMPM RCTE Control of operation of each counter Stops counter operation. Enables counter operation. CLOE1 Output control of RC1CK1HZ pin Disables output by RC1CK1HZ pin (1 Hz). Enables output by RC1CK1HZ pin (1 Hz).
Page 640 CHAPTER 10 WATCH FUNCTIONS (3) Real-time counter control register 2 (RC1CC2) This is an 8-bit register that is used to control the alarm interrupt function and the wait state of the counter. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 641 CHAPTER 10 WATCH FUNCTIONS (4) Real-time counter control register 3 (RC1CC3) This is an 8-bit register that is used to control the interval interrupt function and the RC1CKDIV pin. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 642 CHAPTER 10 WATCH FUNCTIONS (5) Subcount register (RC1SUBC) This is a 16-bit register that counts the reference time of 1 second of the real-time counter. The value of this register ranges from 0000H to 7FFFH and the register counts 1 second with a clock of 32.768 kHz.
Page 643 CHAPTER 10 WATCH FUNCTIONS (7) Minute count register (RC1MIN) This is an 8-bit register that indicates the count value of minutes in a range of 0 to 59 (decimal number). It counts up when an overflow occurs from the second counter. If a value is written to this register, it is written to a buffer and then to the counter after up to 2 clocks (32.768 kHz).
Page 644 CHAPTER 10 WATCH FUNCTIONS The relationship in time between the set value of the RC1CC1.AMPM bit and the value of the RC1HOUR register is shown in Table 10-4. Table 10-4. Time Digit Indication 12-Hour System (AMPM Bit = 0) 24-Hour System (AMPM Bit = 1) Time Value of RC1HOUR Register Time...
Page 645 CHAPTER 10 WATCH FUNCTIONS (9) Day count register (RC1DAY) This is an 8-bit register that indicates the count value of days in a range of 1 to 31 (decimal number). It counts up when an overflow occurs from the hour counter. The counter counts up as follows.
Page 646 CHAPTER 10 WATCH FUNCTIONS (10) Week count register (RC1WEEK) This is an 8-bit register that indicates the count value of weeks in a range of 0 to 6 (decimal number). It counts up in synchronization with the day counter. If a value is written to this register, it is written to a buffer and then to the counter after up to 2 clocks (32.768 kHz).
Page 647 CHAPTER 10 WATCH FUNCTIONS (11) Month count register (RC1MONTH) This is an 8-bit register that indicates the count value of months in a range of 0 to 12 (decimal number). It counts up when an overflow occurs from the day counter. If a value is written to this register, it is written to a buffer and then to the counter after up to 2 clocks (32.768 kHz).
Page 648 CHAPTER 10 WATCH FUNCTIONS (13) Watch error correction register (RC1SUBU) This register can correct the advance or delay of the watch with a high precision by changing the value (reference value: 7FFFH) that overflows from the subcount register (RSUBC) to the second count register. This register can be read or written in 8-bit or 1-bit units.
Page 649 CHAPTER 10 WATCH FUNCTIONS (14) Alarm minute setting register (RC1ALM) This register sets the minutes of alarm. This register can be read or written in 8-bit units. Reset sets this register to 00H. Cautions 1. Set a BCD code of 00 to 59 (decimal number) to this register. If a value other than this range is set, the alarm is not detected.
Page 650 CHAPTER 10 WATCH FUNCTIONS (16) Alarm week setting register (RC1ALW) This register sets the weeks of alarm. This register can be read or written in 8-bit units. Reset sets this register to 00H. Caution To rewrite the RC1ALW register while the real-time counter is operating (RC1CC0.RC1PWR bit = 1), refer to 10.5.4 (5) Changing setting of INTRTC1 interrupt during clock operation.
Page 651: Operation
CHAPTER 10 WATCH FUNCTIONS 10.5.4 Operation (1) Initialization Initialization should be executed when the watch function or periodic interrupt operation is to be performed. Figure 10-7. Initialization Procedure Start RTCE bit = 0 Setting to stop counter operation (RC1CC1) Setting RC1CKS bit Selecting the operating clock of the real-time counter (RTC) (RC1CC0) Setting RC1PWR bit...
Page 652 CHAPTER 10 WATCH FUNCTIONS (2) Rewriting each counter during clock operation Make the following setting to rewrite each counter (RC1SEC, RC1MIN, RC1HOUR, RC1WEEK, RC1DAY, RC1MONTH, or RC1YEAR register) during clock operation (RC1CC0.RC1PWR bit = 1). Figure 10-8. Rewriting Each Counter During Clock Operation Start RWST bit = 0? Checking if the previous writing to the RC1SEC...
Page 653 CHAPTER 10 WATCH FUNCTIONS (3) Reading each counter during clock operation Read each counter (RC1SEC, RC1MIN, RC1HOUR, RC1WEEK, RC1DAY, RC1MONTH, or RC1YEAR register) during clock operation (RC1CC0.RC1PWR bit = 1) as follows. Figure 10-9. Reading Each Counter During Clock Operation Start RWST bit = 0? Checking if the previous writing to the RC1SEC to...
Page 654 CHAPTER 10 WATCH FUNCTIONS (4) Changing setting of INTRTC0 interrupt during clock operation If the setting of the INTRTC0 interrupt (periodic interrupt) is changed during the clock operation of the real-time counter (RC1CC0.RC1PWR bit = 1), a whisker may be generated on the waveform of the INTRCT0 interrupt and an unintended signal may be output.
Page 655 CHAPTER 10 WATCH FUNCTIONS (5) Changing setting of INTRTC1 interrupt during clock operation If the setting of the INTRTC1 interrupt (alarm interrupt) is changed during the clock operation of the real-time counter (RC1CC0.RC1PWR bit = 1), a whisker may be generated on the waveform of the INTRCT1 interrupt and an unintended signal may be output.
Page 656 CHAPTER 10 WATCH FUNCTIONS (6) Initial setting of INTRTC2 interrupt Set the INTRTC1 interrupt (interval interrupt) as follows. Figure 10-12. Setting of INTRTC2 Interrupt Start RC1PWR bit = 1 Enabling counter operation (RC1CC0) Setting ICT2 to ICT0 bits <1> Selecting interval time of INTRTC2 (interval) interrupt (RC1CC3) <2>...
Page 657 CHAPTER 10 WATCH FUNCTIONS (7) Changing setting of INTRTC2 interrupt during clock operation If the setting of the INTRTC2 interrupt (interval interrupt) is changed during clock operation of the real-time counter (RC1CC0.RC1PWR bit = 1), a whisker may be generated on the waveform of the INTRCT2 interrupt and an unintended signal may be output.
Page 658 CHAPTER 10 WATCH FUNCTIONS (8) Initializing real-time counter The following figure shows the procedure for initializing the real-time counter Figure 10-14. Initializing Real-Time Counter Start Setting RTCnMK bit Masking interrupt request signal (INTRTCn) (RTCnIC) CLOE2 bit = 0 (RC1CC3) Disabling RC1CKDIV interrupt CLOE1 bit = 0 (RC1CC1) Disabling RC1CK1HZ interrupt CLOE0 bit = 0 (RC1CC1)
Page 659 CHAPTER 10 WATCH FUNCTIONS (9) Example of correcting watch error of real-time counter The watch error correction function is to correct the deviation of the oscillation frequency of the resonator connected to the V850E/SJ3-H or V850E/SK3-H. The “deviation” means the “constant deviation” of the frequency of the resonator when the resonator was designed.
Page 660 CHAPTER 10 WATCH FUNCTIONS If a “positive error” that is faster than 32.768 kHz occurs on the resonator, as shown in Figure 10-15, the watch can be accurately counted by increasing the count value of the RC1SUBC register. Similarly, if a “negative error”...
Page 661 CHAPTER 10 WATCH FUNCTIONS (c) RC1SUBU.DEV bit The RC1SUBU.DEV bit determines the timing in which the setting of the F6 to F0 bits is valid. The value set by the F6 to F0 bits is not always reflected on the count value of the RC1SUBC register but it is reflected in the following timing.
Page 662 CHAPTER 10 WATCH FUNCTIONS Table 10-8. Frequency Range Correctable When DEV Bit = 0 F6 Bit F5 to F0 RC1SUBC Register Correction Value Connected Clock Frequency Bits (with constant deviation included) − 000000 No correction − 000001 No correction 000010 Increments RC1SUBC register count value by +2 once every 20 seconds 32.76810000 kHz 000011...
Page 663: Chapter 11 Functions Of Watchdog Timer 2
CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2 11.1 Functions Watchdog timer 2 has the following functions. • Default-start watchdog timer Notes 1, 2 → Reset mode: Reset operation upon overflow of watchdog timer 2 (generation of WDT2RES signal) → Non-maskable interrupt request mode: NMI operation upon overflow of watchdog timer 2 (generation of Note 3 INTWDT2 signal) •...
Page 664: Configuration
CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2 11.2 Configuration The following shows the block diagram of watchdog timer 2. Figure 11-1. Block Diagram of Watchdog Timer 2 to f to f INTWDT2 Clock to f Output 16-bit input Selector controller counter WDT2RES controller...
Page 665: Registers
CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2 11.3 Registers (1) Watchdog timer mode register 2 (WDTM2) The WDTM2 register sets the overflow time and operation clock of watchdog timer 2. This register can be read or written in 8-bit units. This register can be read any number of times, but it can be written only once following reset release.
Page 666 CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2 (2/2) Cautions 1. When watchdog timer 2 is not used or when changing the operation mode, be sure to always set the WDTMD1 bit of the option byte 0000007AH to 0. Changing modes with the WDTM2 register when the WDTMD1 bit is set to 1 is invalid.
Page 667 CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2 Table 11-2. Watchdog Timer 2 Clock Selection Selected WDCS24 WDCS23 WDCS22 WDCS21 WDCS20 100 kHz (MIN.) 220 kHz (TYP.) 400 kHz (MAX.) Clock 41.0 ms 18.6 ms 10.2 ms 81.9 ms 37.2 ms 20.5 ms 163.8 ms 74.5 ms...
Page 668 CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2 (2) Watchdog timer enable register (WDTE) The counter of watchdog timer 2 is cleared and counting restarted by writing “ACH” to the WDTE register. The WDTE register can be read or written in 8-bit units. Reset sets this register to 9AH.
Page 669: Operation
CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2 11.4 Operation Watchdog timer 2 automatically starts in the reset mode following reset release. The WDTM2 register can be written to only once following reset using byte access. To use watchdog timer 2, write the operation mode and the interval time to the WDTM2 register using an 8-bit memory manipulation instruction.
Page 670: Chapter 12 Real-Time Output Function (Rto)
CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO) 12.1 Function The real-time output function transfers preset data to the RTBLn and RTBHn registers, and then transfers this data by hardware to an external device via the output latches, upon occurrence of a timer interrupt. The pins through which the data is output to an external device constitute a port called the real-time output function (RTO).
Page 671: Configuration
CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO) 12.2 Configuration The block diagram of RTO is shown below. Figure 12-1. Block Diagram of RTO Real-time output Real-time output buffer register nH RTPn4, latch nH (RTBHn) RTPn5 Real-time output Real-time output buffer register nL RTPn0 to latch nL (RTBLn)
Page 672 CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO) (1) Real-time output buffer registers nL, nH (RTBLn, RTBHn) The RTBLn and RTBHn registers are 4-bit registers that hold preset output data. These registers are mapped to independent addresses in the peripheral I/O register area. These registers can be read or written in 8-bit or 1-bit units.
Page 673: Registers
CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO) 12.3 Registers RTO is controlled using the following two registers. • Real-time output port mode register n (RTPMn) • Real-time output port control register n (RTPCn) (1) Real-time output port mode register n (RTPMn) The RTPMn register selects the real-time output port mode or port mode in 1-bit units.
Page 674 CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO) (2) Real-time output port control register n (RTPCn) The RTPCn register is a register that sets the operation mode and output trigger of the real-time output port. The relationship between the operation mode and output trigger of the real-time output port is as shown in Tables 12-3 and 12-4.
Page 675: Operation
CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO) 12.4 Operation If the real-time output operation is enabled by setting the RTPCn.RTPOEn bit to 1, the data of the RTBHn and RTBLn registers is transferred to the real-time output latch in synchronization with the generation of the selected transfer trigger (set by the RTPCn.EXTRn and RTPCn.BYTEn bits).
Page 676: Usage
CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO) 12.5 Usage (1) Disable real-time output. Clear the RTPCn.RTPOEn bit to 0. (2) Perform initialization as follows. • When n = 0, set the alternate-function pins of port 5 Set the PFC5.PFC5m bit and PFCE5.PFCE5m bit to 1, and then set the PMC5.PMC5m bit to 1 (m = 0 to 5). When n = 1, set the alternate-function pins of port 6 Set the PFC6.PFC6m bit and PFCE6.PFCE6m bit to 0, and then set the PMC6.PMC6m bit to 1.
Page 677: Chapter 13 A/D Converter
CHAPTER 13 A/D CONVERTER 13.1 Overview The A/D converter converts analog input signals into digital values, has a resolution of 10 bits, and can handle 16 analog input signal channels (ANI0 to ANI15). The A/D converter has the following features. 10-bit resolution 16 channels Successive approximation method...
Page 678: Configuration
CHAPTER 13 A/D CONVERTER 13.3 Configuration The block diagram of the A/D converter is shown below. Figure 13-1. Block Diagram of A/D Converter REF0 ANI0 Sample & hold circuit ADA0CE bit ANI1 ANI2 Voltage comparator & Compare voltage ADA0CE bit ANI13 generation DAC ANI14...
Page 679 CHAPTER 13 A/D CONVERTER (1) Successive approximation register (SAR) The SAR register compares the voltage value of the analog input signal with the output voltage of the compare voltage generation DAC (compare voltage), and holds the comparison result starting from the most significant bit (MSB).
Page 680 CHAPTER 13 A/D CONVERTER (12) Compare voltage generation DAC This compare voltage generation DAC is connected between AV and AV and generates a voltage for REF0 comparison with the analog input signal. (13) ANI0 to ANI15 pins These are analog input pins for the 16 A/D converter channels and are used to input analog signals to be converted into digital signals.
Page 681: Registers
CHAPTER 13 A/D CONVERTER 13.4 Registers The A/D converter is controlled by the following registers. • A/D converter mode registers 0, 1, 2 (ADA0M0, ADA0M1, ADA0M2) • A/D converter channel specification register 0 (ADA0S) • Power-fail compare mode register (ADA0PFM) The following registers are also used.
Page 682 CHAPTER 13 A/D CONVERTER (2/2) Specification of external trigger (ADTRG pin) input valid edge ADA0ETS1 ADA0ETS0 No edge detection Falling edge detection Rising edge detection Detection of both rising and falling edges ADA0TMD Trigger mode specification Software trigger mode External trigger mode/timer trigger mode ADA0EF A/D converter status display A/D conversion stopped...
Page 683 CHAPTER 13 A/D CONVERTER (2) A/D converter mode register 1 (ADA0M1) The ADA0M1 register is an 8-bit register that specifies the conversion time. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H Address: FFFFF201H ADA0M1...
Page 684 CHAPTER 13 A/D CONVERTER Table 13-2. Conversion Time Selection in Normal Conversion Mode (ADA0HS1 Bit = 0) ADA0FR3 to A/D Conversion Time ADA0FR0 Stabilization Time + Conversion = 32 MHz = 24 MHz = 20 MHz = 16 MHz = 4 MHz Trigger Bits Time + Wait Time...
Page 685 CHAPTER 13 A/D CONVERTER Table 13-3. Conversion Time Selection in High-Speed Conversion Mode (ADA0HS1 Bit = 1) A/D Conversion Time ADA0FR3 to ADA0FR0 Conversion Time = 32 MHz = 24 MHz = 20 MHz = 16 MHz = 4 MHz Trigger Response Bits (+ Stabilization Time)
Page 686 CHAPTER 13 A/D CONVERTER (3) A/D converter mode register 2 (ADA0M2) The ADA0M2 register specifies the hardware trigger mode. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H Address: FFFFF203H ADA0M2 ADA0TMD1 ADA0TMD0...
Page 687 CHAPTER 13 A/D CONVERTER (4) A/D converter channel specification register (ADA0S) The ADA0S register specifies the pin that inputs the analog voltage to be converted into a digital signal. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 688 CHAPTER 13 A/D CONVERTER (5) A/D conversion result registers n, nH (ADA0CRn, ADA0CRnH) The ADA0CRn and ADA0CRnH registers store the A/D conversion results. These registers are read-only, in 16-bit or 8-bit units. However, specify the ADA0CRn register for 16-bit access and the ADA0CRnH register for 8-bit access.
Page 689 CHAPTER 13 A/D CONVERTER The relationship between the analog voltage input to the analog input pins (ANI0 to ANI15) and the A/D conversion result (ADA0CRn register) is as follows. × 1,024 + 0.5) SAR = INT ( REF0 = SAR × 64 Note ADA0CR REF0...
Page 690 CHAPTER 13 A/D CONVERTER (6) Power-fail compare mode register (ADA0PFM) The ADA0PFM register is an 8-bit register that sets the power-fail compare mode. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H Address: FFFFF204H <7>...
Page 691 CHAPTER 13 A/D CONVERTER (7) Power-fail compare threshold value register (ADA0PFT) The ADA0PFT register sets the compare value in the power-fail compare mode. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H Address: FFFFF205H ADA0PFT...
Page 692: Operation
CHAPTER 13 A/D CONVERTER 13.5 Operation 13.5.1 Basic operation <1> Set the operation mode, trigger mode, and conversion time for executing A/D conversion by using the ADA0M0, ADA0M1, ADA0M2, and ADA0S registers. When the ADA0M0.ADA0CE bit is set, conversion is started in the software trigger mode and the A/D converter waits for a trigger in the external or timer trigger mode.
Page 693: Conversion Operation Timing
CHAPTER 13 A/D CONVERTER 13.5.2 Conversion operation timing Figure 13-3. Conversion Operation Timing (Continuous Conversion) (1) Operation in normal conversion mode (ADA0HS1 bit = 0) ADA0M0.ADA0CE bit First conversion Second conversion Setup Sampling A/D conversion Wait Setup Sampling Processing state INTAD signal Stabilization Conversion time...
Page 694: Trigger Mode
CHAPTER 13 A/D CONVERTER 13.5.3 Trigger mode The timing of starting the conversion operation is specified by setting a trigger mode. The trigger mode includes a software trigger mode and hardware trigger modes. The hardware trigger modes include timer trigger modes 0 and 1, and external trigger mode.
Page 695 CHAPTER 13 A/D CONVERTER (3) Timer trigger mode In this mode, converting the signal of the analog input pin (ANI0 to ANI15) specified by the ADA0S register is started by the compare match interrupt request signal (INTTP2CC0 or INTTP2CC1) of the capture/compare register connected to the timer.
Page 696: Operation Mode
CHAPTER 13 A/D CONVERTER 13.5.4 Operation mode Four operation modes are available as the modes in which to set the ANI0 to ANI15 pins: continuous select mode, continuous scan mode, one-shot select mode, and one-shot scan mode. The operation mode is selected by the ADA0M0.ADA0MD1 and ADA0M0.ADA0MD0 bits. (1) Continuous select mode In this mode, the voltage of one analog input pin selected by the ADA0S register is continuously converted into a digital value.
Page 697 CHAPTER 13 A/D CONVERTER Figure 13-5. Timing Example of Continuous Scan Mode Operation (ADA0S Register = 03H) (a) Timing example ANI0 Data 1 Data 5 ANI1 Data 6 Data 2 Data 7 Data 3 ANI2 ANI3 Data 4 Data 1 Data 2 Data 3 Data 4...
Page 698 CHAPTER 13 A/D CONVERTER (3) One-shot select mode In this mode, the voltage on the analog input pin specified by the ADA0S register is converted into a digital value only once. The conversion result is stored in the ADA0CRn register corresponding to the analog input pin. In this mode, an analog input pin and an ADA0CRn register correspond on a one-to-one basis.
Page 699 CHAPTER 13 A/D CONVERTER Figure 13-7. Timing Example of One-Shot Scan Mode Operation (ADA0S Register = 03H) (a) Timing example ANI0 Data Data 1 ANI1 Data Data Data Data ANI2 ANI3 Data Data 1 Data 2 Data 3 Data 4 conversion (ANI0) (ANI1)
Page 700: Power-Fail Compare Mode
CHAPTER 13 A/D CONVERTER 13.5.5 Power-fail compare mode The A/D conversion end interrupt request signal (INTAD) can be controlled as follows by the ADA0PFM and ADA0PFT registers. • When the ADA0PFM.ADA0PFE bit = 0, the INTAD signal is generated each time conversion is completed (normal use of the A/D converter).
Page 701 CHAPTER 13 A/D CONVERTER (1) Continuous select mode In this mode, the result of converting the voltage of the analog input pin specified by the ADA0S register is compared with the set value of the ADA0PFT register. If the result of power-fail compare matches the condition set by the ADA0PFC bit, the conversion result is stored in the ADA0CRn register, and the INTAD signal is generated.
Page 702 CHAPTER 13 A/D CONVERTER Figure 13-9. Timing Example of Continuous Scan Mode Operation (When Power-Fail Comparison Is Made: ADA0S Register = 03H) (a) Timing example ANI0 Data 1 Data 5 ANI1 Data 6 Data 2 Data 7 Data 3 ANI2 ANI3 Data 4 Data 1...
Page 703 CHAPTER 13 A/D CONVERTER (3) One-shot select mode In this mode, the result of converting the voltage of the analog input pin specified by the ADA0S register is compared with the set value of the ADA0PFT register. If the result of power-fail compare matches the condition set by the ADA0PFC bit, the conversion result is stored in the ADA0CRn register, and the INTAD signal is generated.
Page 704 CHAPTER 13 A/D CONVERTER Figure 13-11. Timing Example of One-Shot Scan Mode Operation (When Power-Fail Comparison Is Made: ADA0S Register = 03H) (a) Timing example ANI0 Data 1 Data 5 ANI1 Data 6 Data 2 Data 7 Data 3 ANI2 ANI3 Data 4 Data 1...
Page 705: Cautions
CHAPTER 13 A/D CONVERTER 13.6 Cautions (1) When A/D converter is not used When the A/D converter is not used, the power consumption can be reduced by clearing the ADA0M0.ADA0CE bit to 0. (2) Input range of ANI0 to ANI15 pins Input the voltage within the specified range to the ANI0 to ANI15 pins.
Page 706 CHAPTER 13 A/D CONVERTER (4) Alternate I/O The analog input (ANI0 to ANI15) pins are multiplexed with port pins. The AV power pin is multiplexed with REF0 the reference power supply to the A/D converter and the I/O buffer power supply of port 7. If any of the following processings is performed during A/D conversion, therefore, the expected A/D conversion value may not be obtained.
Page 707 CHAPTER 13 A/D CONVERTER (5) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the contents of the ADA0S register are changed. If the analog input pin is changed during A/D conversion, therefore, the result of converting the previously selected analog input signal may be stored and the conversion end interrupt request flag may be set immediately before the ADA0S register is rewritten.
Page 708 CHAPTER 13 A/D CONVERTER (7) AV REF0 (a) The AV pin is used as the power supply pin of the A/D converter and also supplies power to the REF0 alternate-function ports. In an application where a backup power supply is used, be sure to supply the same voltage as V to the AV pin as shown in Figure 13-15.
Page 709 CHAPTER 13 A/D CONVERTER (10) Restriction for each mode (a) To select the external trigger mode/timer trigger mode, set the high-speed conversion mode. Do not input a trigger during stabilization time that is inserted once after the A/D conversion operation is enabled (ADA0M0.ADA0CE bit = 1).
Page 710: How To Read A/D Converter Characteristics Table
CHAPTER 13 A/D CONVERTER 13.7 How to Read A/D Converter Characteristics Table This section describes the terms related to the A/D converter. (1) Resolution The minimum analog input voltage that can be recognized, i.e., the ratio of an analog input voltage to 1 bit of digital output is called 1 LSB (least significant bit).
Page 711 CHAPTER 13 A/D CONVERTER (3) Quantization error This is an error of ±1/2 LSB that inevitably occurs when an analog value is converted into a digital value. Because the A/D converter converts analog input voltages in a range of ±1/2 LSB into the same digital codes, a quantization error is unavoidable.
Page 712 CHAPTER 13 A/D CONVERTER (5) Full-scale error This is the difference between the actually measured analog input voltage and its theoretical value when the digital output changes from 1…110 to 1…111 (full scale − 3/2 LSB). Figure 13-19. Full-Scale Error Full-scale error 2 AV REF0 −...
Page 713 CHAPTER 13 A/D CONVERTER (7) Integral linearity error This error indicates the extent to which the conversion characteristics differ from the ideal linear relationship. It indicates the maximum value of the difference between the actually measured value and its theoretical value where the zero-scale error and full-scale error are 0.
Page 714: Chapter 14 D/A Converter
CHAPTER 14 D/A CONVERTER 14.1 Functions The D/A converter has the following functions. 8-bit resolution × 2 channels (DA0CS0, DA0CS1) R-2R ladder method μ Settling time: 3 s max. (when AV is 3.0 to 3.6 V and external load is 20 pF) REF1 ×...
Page 715: Registers
CHAPTER 14 D/A CONVERTER The D/A converter consists of the following hardware. Table 14-1. Configuration of D/A Converter Item Configuration Control registers D/A converter mode register (DA0M) D/A converter conversion value setting registers 0, 1 (DA0CS0, DA0CS1) 14.3 Registers The registers that control the D/A converter are as follows. •...
Page 716 CHAPTER 14 D/A CONVERTER (2) D/A converter conversion value setting registers 0, 1 (DA0CS0, DA0CS1) The DA0CS0 and DA0CS1 registers set the analog voltage value output to the ANO0 and ANO1 pins. These registers can be read or written in 8-bit units. Reset sets these registers to 00H.
Page 717: Operation
CHAPTER 14 D/A CONVERTER 14.4 Operation 14.4.1 Operation in normal mode D/A conversion is performed using a write operation to the DA0CSn register as the trigger. The setting method is described below. <1> Set the DA0M.DA0MDn bit to 0 (normal mode). <2>...
Page 718: Cautions
CHAPTER 14 D/A CONVERTER 14.4.3 Cautions Observe the following cautions when using the D/A converter of the V850E/SJ3-H or V850E/SK3-H. (1) Do not change the set value of the DA0CSn register while the trigger signal is being issued in the real-time output mode.
Page 719: Chapter 15 Asynchronous Serial Interface A (Uarta)
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.1 Port Settings of UARTA0 to UARTA5 15.1.1 For V850E/SJ3-H Table 15-1. Pin Configuration Mode Alternate-Function Pin Name Port <1> Port <2> Pin No. Port Alternate Function Pin No. Port Alternate Function − −...
Page 720 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (3) UARTA2 The transmission/reception pins (TXDA2 and RXDA2) of UARTA2 are assigned to P38 and P39, respectively. When using UARTA2, specify P38 and P39 as the TXDA2 and RXDA2 pins in advance, using the PMC3, PFC3, and PFCE3 registers.
Page 721: For V850E/Sk3-H
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.1.2 For V850E/SK3-H Table 15-2. Pin Configuration Mode Alternate-Function Pin Name Port <1> Port <2> Pin No. Port Alternate Function Pin No. Port Alternate Function − − − UARTA0 TXDA0 SOB4 − − −...
Page 722 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (3) UARTA2 The transmission/reception pins (TXDA2 and RXDA2) of UARTA2 are assigned to two port pins P38, P39 and P311, P312, respectively, and can be used at either one of the two port pins only. When using UARTA2 at P38 and P39, specify P38 and P39 as the TXDA2 and RXDA2 pins in advance, using the PMC3, PFC3, and PFCE3 registers.
Page 723: Features
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.2 Features Transfer rate: 300 bps to 625 kbps (using dedicated baud rate generator) Full-duplex communication: Internal UARTAn receive data register (UAnRX) Internal UARTAn transmit data register (UAnTX) 2-pin configuration: TXDAn: Transmit data output pin RXDAn: Receive data input pin Reception error output function •...
Page 724: Configuration
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.3 Configuration The block diagram of the UARTAn is shown below. Figure 15-1. Block Diagram of Asynchronous Serial Interface An Internal bus INTUAnT INTUAnR Transmission Reception unit UAnRX UAnTX unit Receive Transmit Transmission Reception shift register shift register...
Page 725 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) UARTAn consists of the following hardware units. Table 15-3. Configuration of UARTAn Item Configuration Registers UARTAn control register 0 (UAnCTL0) UARTAn control register 1 (UAnCTL1) UARTAn control register 2 (UAnCTL2) UARTAn option control register 0 (UAnOPT0) UARTAn status register (UAnSTR) UARTAn receive shift register UARTAn receive data register (UAnRX)
Page 726 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (8) UARTAn transmit shift register The transmit shift register is a shift register used to convert the parallel data transferred from the UAnTX register into serial data. When 1 byte of data is transferred from the UAnTX register, the shift register data is output from the TXDAn pin. This register cannot be manipulated directly.
Page 727: Registers
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.4 Registers (1) UARTAn control register 0 (UAnCTL0) The UAnCTL0 register is an 8-bit register that controls the UARTAn serial transfer operation. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 10H.
Page 728 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (2/2) UAnRXE Reception operation enable Disable reception operation Enable reception operation • To start reception, set the UAnPWR bit to 1 and then set the UAnRXE bit to 1. • To initialize the reception unit, clear the UAnRXE bit to 0, wait for two cycles of the base clock, and then set the UAnRXE bit to 1 again.
Page 729 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (2) UARTAn control register 1 (UAnCTL1) For details, see 15.7 (2) UARTAn control register 1 (UAnCTL1). (3) UARTAn control register 2 (UAnCTL2) For details, see 15.7 (3) UARTAn control register 2 (UAnCTL2). (4) UARTAn option control register 0 (UAnOPT0) The UAnOPT0 register is an 8-bit register that controls the serial transfer operation of the UARTAn register.
Page 730 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (2/2) UAnSTT SBF transmission trigger − SBF transmission trigger • This is the SBF transmission trigger bit during LIN communication, and when read, “0” is always read. • Set the UAnSTT bit after setting the UAnPWR bit = UAnTXE bit = 1. •...
Page 731 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (5) UARTAn status register (UAnSTR) The UAnSTR register is an 8-bit register that displays the UARTAn transfer status and reception error contents. This register can be read or written in 8-bit or 1-bit units, but the UAnTSF bit is a read-only bit, while the UAnPE, UAnFE, and UAnOVE bits can both be read and written.
Page 732 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) After reset: 00H Address: UA0STR FFFFFA04H, UA1STR FFFFFA14H, UA2STR FFFFFA24H, UA3STR FFFFFA34H, UA4STR FFFFFA44H, UA5STR FFFFFA54H <2> <1> <7> <0> UAnSTR UAnTSF UAnPE UAnFE UAnOVE (n = 0 to 5) UAnTSF Transfer status flag •...
Page 733 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (6) UARTAn receive data register (UAnRX) The UAnRX register is an 8-bit buffer register that stores parallel data converted by the receive shift register. The data stored in the receive shift register is transferred to the UAnRX register upon completion of reception of 1 byte of data.
Page 734: Interrupt Request Signals
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.5 Interrupt Request Signals The following two interrupt request signals are generated from UARTAn. • Reception completion interrupt request signal (INTUAnR) • Transmission enable interrupt request signal (INTUAnT) The default priority for these two interrupt request signals is reception completion interrupt request signal then transmission enable interrupt request signal.
Page 735: Operation
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6 Operation 15.6.1 Data format Full-duplex serial data reception and transmission is performed. As shown in Figure 15-2, one data frame of transmit/receive data consists of a start bit, character bits, parity bit, and stop bit(s).
Page 736 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) Figure 15-2. UARTA Transmit/Receive Data Format (a) 8-bit data length, LSB first, even parity, 1 stop bit, transfer data: 55H 1 data frame Start Parity Stop (b) 8-bit data length, MSB first, even parity, 1 stop bit, transfer data: 55H 1 data frame Start Parity...
Page 737: Sbf Transmission/Reception Format
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.2 SBF transmission/reception format The V850E/SJ3-H and V850E/SK3-H have an SBF (Sync Break Field) transmission/reception control function to enable use of the LIN function. Remark LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication protocol intended to aid the cost reduction of an automotive network.
Page 738 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) Figure 15-4. LIN Reception Manipulation Outline Wake-up Sync Check signal break Sync Identifier DATA DATA frame field field field field field field Note 2 Data Data Note 5 SF reception 13 bits ID reception transmission transmission Data transmission...
Page 739: Sbf Transmission
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.3 SBF transmission When the UAnCTL0.UAnPWR bit = UAnCTL0.UAnTXE bit = 1, the transmission enabled status is entered, and SBF transmission is started by setting (to 1) the SBF transmission trigger (UAnOPT0.UAnSTT bit). Thereafter, a low level the width of bits 13 to 20 specified by the UAnOPT0.UAnSLS2 to UAnOPT0.UAnSLS0 bits is output.
Page 740: Sbf Reception
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.4 SBF reception The reception enabled status is achieved by setting the UAnCTL0.UAnPWR bit to 1 and then setting the UAnCTL0.UAnRXE bit to 1. The SBF reception wait status is set by setting the SBF reception trigger (UAnOPT0.UAnSTR bit) to 1. In the SBF reception wait status, similarly to the UART reception wait status, the RXDAn pin is monitored and start bit detection is performed.
Page 741: Uart Transmission
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.5 UART transmission A high level is output to the TXDAn pin by setting the UAnCTL0.UAnPWR bit to 1. Next, the transmission enabled status is set by setting the UAnCTL0.UAnTXE bit to 1, and transmission is started by writing transmit data to the UAnTX register.
Page 742: Continuous Transmission Procedure
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.6 Continuous transmission procedure UARTAn can write the next transmit data to the UAnTX register when the UARTAn transmit shift register starts the shift operation. The transmit timing of the UARTAn transmit shift register can be judged from the transmission enable interrupt request signal (INTUAnT).
Page 743 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) Figure 15-9. Continuous Transmission Operation Timing (a) Transmission start Start Data (1) Parity Stop Start Data (2) Parity Stop Start TXDAn UAnTX Data (1) Data (2) Data (3) Transmission Data (2) Data (1) shift register INTUAnT UAnTSF...
Page 744: Uart Reception
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.7 UART reception The reception wait status is set by setting the UAnCTL0.UAnPWR bit to 1 and then setting the UAnCTL0.UAnRXE bit to 1. In the reception wait status, the RXDAn pin is monitored and start bit detection is performed. Start bit detection is performed using a two-step detection routine.
Page 745: Reception Errors
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.8 Reception errors Errors during a receive operation are of three types: parity errors, framing errors, and overrun errors. Data reception result error flags are set in the UAnSTR register and a reception completion interrupt request signal (INTUAnR) is output when an error occurs.
Page 746 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) When reception errors occur, perform the following procedures depending upon the kind of error. • Parity error If false data is received due to problems such as noise in the reception line, discard the received data and retransmit.
Page 747: Parity Types And Operations
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.9 Parity types and operations Caution When using the LIN function, fix the UAnPS1 and UAnPS0 bits of the UAnCTL0 register to 00. The parity bit is used to detect bit errors in the communication data. Normally the same parity is used on the transmission side and the reception side.
Page 748: Receive Data Noise Filter
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.10 Receive data noise filter This filter samples signals received via the RXDAn pin using the base clock supplied by the dedicated baud rate generator. When the same sampling value is read twice, the match detector output changes and the RXDAn signal is sampled <R>...
Page 749: Dedicated Baud Rate Generator
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.7 Dedicated Baud Rate Generator The dedicated baud rate generator consists of a source clock selector block and an 8-bit programmable counter, and generates a serial clock during transmission and reception with UARTAn. Regarding the serial clock, a dedicated baud rate generator output can be selected for each channel.
Page 750 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (a) Base clock When the UAnCTL0.UAnPWR bit is 1, the clock selected by the UAnCTL1.UAnCKS3 to UAnCTL1.UAnCKS0 bits is supplied to the 8-bit counter. This clock is called the base clock (f ). The UCLK base clock f is fixed to the low level when the UAnPWR bit is 0.
Page 751 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (2) UARTAn control register 1 (UAnCTL1) The UAnCTL1 register is an 8-bit register that selects the UARTAn base clock. This register can be read or written in 8-bit units. Reset sets this register to 00H. Caution Clear the UAnCTL0.UAnPWR bit to 0 before rewriting the UAnCTL1 register.
Page 752 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (3) UARTAn control register 2 (UAnCTL2) The UAnCTL2 register is an 8-bit register that selects the baud rate (serial transfer speed) clock of UARTAn. This register can be read or written in 8-bit units. Reset sets this register to FFH.
Page 753 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (4) Baud rate The baud rate is obtained by the following equation. UCLK Baud rate = [bps] 2 × k When using the internal clock, the equation will be as follows (when using the ASCKA0 pin as clock at UARTA0, calculate using the above equation).
Page 754 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) The baud rate error is obtained by the following equation. Actual baud rate (baud rate with error) − 1 × 100 [%] Error (%) = Target baud rate (correct baud rate) UCLK − 1 × 100 [%] 2 ×...
Page 755 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) To set the baud rate, perform the following calculation and set the UAnCTL1 and UAnCTL2 registers (when using internal clock). /(2 × Target baud rate). Set m = 0. <1> Set k = f <2>...
Page 756 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (5) Allowable baud rate range during reception The baud rate error range at the destination that is allowable during reception is shown below. Caution The baud rate error during reception must be set within the allowable error range using the following equation.
Page 757 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) Therefore, the maximum baud rate that can be received by the destination is as follows. − BRmax = (FLmin/11) Brate 21k + 2 Similarly, obtaining the following maximum allowable transfer rate yields the following. 21k −...
Page 758 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (6) Baud rate during continuous transmission During continuous transmission, the transfer rate from the stop bit to the next start bit is usually 2 base clocks longer. However, timing initialization is performed via start bit detection by the receiving side, so this has no influence on the transfer result.
Page 759: Cautions
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.8 Cautions (1) When clock supply to UARTAn is stopped When the clock supply to UARTAn is stopped (for example, in IDLE1, IDLE2, or STOP mode), the operation stops with each register retaining the value it had immediately before the clock supply was stopped. The TXDAn pin output also holds and outputs the value it had immediately before the clock supply was stopped.
Page 760 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (8) Switching DMA transfer start factor (a) Switching DMA transfer start factor between INTUA1R and INTIIC2 signals Setting the DMA transfer start factor to other than the following combinations is prohibited. <1> When using UARTA1 and I C02 simultaneously, and the INTUA1R signal is specified as the DMA transfer start factor (V850E/SK3-H only) When the DTFRn.IFCn5 to IFCn0 bits = 28H, set the DTFROB1 bit of the option byte 0000007AH...
Page 761: Chapter 16 Asynchronous Serial Interface B (Uartb)
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) 16.1 Features • Transfer rate: Maximum 1.5 Mbps (using a dedicated baud rate generator) <R> • Full-duplex communications • Single mode and FIFO mode selectable • Single mode: 8-bit × 1-stage data register (UBnTX register or UBnRX register) is used for each of transmission and reception.
Page 762: Configuration
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) 16.2 Configuration The block diagram of the UARTBn is shown below. Figure 16-1. Block Diagram of UARTBn Internal bus Reception unit Transmission unit UARTBnFIFO status register 1 (UBnFIS1) Receive Transmit UARTBnFIFO status INTUBnTIF FIFOn FIFOn register 0 (UBnFIS0)
Page 763 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) UARTBn consists of the following hardware units. Table 16-1. Configuration of UARTBn Item Configuration Registers UARTBn control register 0 (UBnCTL0) UARTBn control register 2 (UBnCTL2) UARTBn status register (UBnSTR) UARTBn FIFO control register 0 (UBnFIC0) UARTBn FIFO control register 1 (UBnFIC1) UARTBn FIFO control register 2 (UBnFIC2) UARTBn FIFO status register 0 (UBnFIS0)
Page 764 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) (7) UARTBn FIFO status register 0 (UBnFIS0) This register is valid in the FIFO mode. The number of bytes of data stored in the receive FIFOn can be read from this register. (8) UARTBn FIFO status register 1 (UBnFIS1) This register is valid in the FIFO mode.
Page 765 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) (12) UARTBn transmit data register (UBnTX) The transmit data register n is a buffer for transmit data. The 8-bit × 1-stage UBnTX register is used as this buffer in the single mode. In the FIFO mode, the 8-bit × 16-stage transmit FIFOn is used. When 7-bit length data is transmitted with the LSB first, bits 6 to 0 of the transmit data register n are transmitted as the transmit data from the LSB (bit 0) with the MSB (bit 7) always being 0.
Page 766: Control Registers
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) 16.3 Control Registers (1) UARTBn control register 0 (UBnCTL0) The UBnCTL0 register controls the transfer operations of UARTBn. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 10H. Cautions 1.
Page 767 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) (1/2) After reset: 10H Address: UB0CTL0 FFFFFA80H, UB1CTL0 FFFFFAA0H <7> <6> <5> <4> UBnCTL0 UBnPWR UBnTXE UBnRXE UBnDIR UBnPS1 UBnPS0 UBnCL UBnSL (n = 0, 1) UBnPWR Operation clock control to UARTBn Stops supply of clocks to UARTBn Supplies clocks to UARTBn •...
Page 768 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) (2/2) UBnDIR Specification of transfer direction mode (MSB/LSB) MSB transfer first LSB transfer first • Clear the UBnPWR bit or UBnTXE and UBnRXE bits to 0 before changing the setting of the UBnDIR bit. UBnPS1 UBnPS0 Parity selection during transmission...
Page 769 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) (2) UARTBn status register (UBnSTR) The UBnSTR register indicates the transfer status and reception error contents while UARTBn is transmitting data. The status flag that indicates the transfer status during transmission indicates the data retention status of the transmit shift register n and transmit data register n (the UBnTX register in the single mode or transmit FIFOn in the FIFO mode).
Page 770 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) (1/2) After reset: 00H Address: UB0STR FFFFFA84H, UB1STR FFFFFAA4H <7> <3> <2> <1> <0> UBnSTR UBnTSF UBnOVF UBnPE UBnFE UBnOVE ( n = 0, 1) UBnTSF Transfer status flag • In single mode (UBnFIC0.UBnMOD bit = 0) Data to be transferred to the transmit shift register n and UBnTX register does not exist (cleared (0) when UBnCTL0.UBnPWR bit = 0 or UBnCTL0.UBnTXE bit = 0).
Page 771 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) (2/2) UBnPE Parity error flag Parity error did not occur. Parity error occurred (during reception). • The UBnPE bit is valid only in the single mode (when UBnFIC0.UBnMOD bit = 0), and invalid in the FIFO mode (when UBnFIC0.UBnMOD bit = 1). •...
Page 772 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) (3) UARTBn control register 2 (UBnCTL2) The UBnCTL2 register is used to specify the division ratio by which to control the baud rate (serial transfer speed) of UARTBn. This register can be read or written in 16-bit units. Reset sets this register to FFFFH.
Page 773 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) (4) UARTBn transmit data register (UBnTX) The UBnTX register is used to set transmit data. It functions as the 8-bit × 1-stage UBnTX register, in the single mode (UBnFIC0.UBnMOD bit = 0), and as the 8-bit × 16-stage transmit FIFOn in the FIFO mode (UBnFIC0.UBnMOD bit = 1).
Page 774 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) (5) UARTBn receive data register AP (UBnRXAP), UARTBn receive data register (UBnRX) These registers store parallel data converted by the receive shift register n. They function as the 8-bit × 1- stage UBnRX register, in the single mode (UBnFIC0.UBnMOD bit = 0), and as the 16-bit × 16-stage receive FIFOn (UBnRXAP register) in the FIFO mode (UBnFIC0.UBnMOD bit = 1).
Page 775 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) Cautions 4. Do not perform the following operations when debugging a system that uses the single mode. • Setting a break for an instruction immediately after the UBnRX register is read • Setting a break before DMA transfer with the UBnRX register specified as the transfer source is completed •...
Page 776 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) (6) UARTBn FIFO control register 0 (UBnFIC0) The UBnFIC0 register is used to select the operation mode of UARTBn and the functions that become valid in the FIFO mode (UBnMOD bit = 1). In the FIFO mode, it clears transmit FIFOn/receive FIFOn and specifies the timing mode in which the transmission enable interrupt request signal (INTUBnTIT)/reception completion interrupt request signal (INTUBnTIR) is generated.
Page 777 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) (1/3) After reset: 00H Address: UB0FIC0 FFFFFA8AH, UB1FIC0 FFFFFAAAH <3> <2> <7> UBnFIC0 UBnMOD UBnTFC UBnRFC UBnITM UBnIRM (n = 0, 1) UBnMOD Specification of UARTBn operation mode Single mode FIFO mode UBnTFC Transmit FIFOn clear trigger bit Normal status Clear (This bit automatically returns to 0 after transmit FIFO is cleared.)
Page 778 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) (2/3) UBnRFC Receive FIFOn (UBnRXAP) clear trigger bit Normal status Clear (This bit automatically returns to 0 after receive FIFOn is cleared.) • The UBnRFC bit is valid only in the FIFO mode (UBnMOD bit = 1), and is invalid in the single mode (UBnMOD bit = 0).
Page 779 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) (3/3) UBnIRM Specification of INTUBnTIR interrupt generation timing in FIFO mode Pending mode Pointer mode In the FIFO mode, the INTUBnTIR signal is generated as soon as receive data of the number set as the trigger by the UBnFIC2.UBnRT3 to UBnFIC2.UBnRT0 bits have been transferred from the receive shift register n to receive FIFOn.
Page 780 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) (7) UARTBn FIFO control register 1 (UBnFIC1) The UBnFIC1 register is valid in the FIFO mode (UBnFIC0.UBnMOD bit = 1). It generates a reception timeout interrupt request signal (INTUBnTITO) if data is stored in receive FIFOn when the next data does not come (start bit is not detected) after the lapse of the time set by the UBnTC4 to UBnTC0 bits (next data reception wait time), after the stop bit has been received.
Page 781 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) (8) UARTBn FIFO control register 2 (UBnFIC2) The UBnFIC2 register is valid in the FIFO mode (UBnFIC0.UBnMOD bit = 1). It sets the timing of generating an interrupt, using the number of transmit/receive data as a trigger. When data is transmitted, the number of data transferred from transmit FIFOn is specified as the condition of generating the interrupt.
Page 782 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) (2/2) Number of data of UBnRT3 UBnRT2 UBnRT1 UBnRT0 Pointer mode Pending mode transmit FIFOn set as trigger 1 byte Settable Settable 2 bytes Setting prohibited 3 bytes 4 bytes 5 bytes 6 bytes 7 bytes 8 bytes 9 bytes...
Page 783 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) (9) UARTBn FIFO status register 0 (UBnFIS0) The UBnFIS0 register is valid in the FIFO mode (UBnFIC0.UBnMOD bit = 1). It is used to read the number of bytes of the data stored in receive FIFOn. This register is read-only in 8-bit units.
Page 784 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) (10) UARTBn FIFO status register 1 (UBnFIS1) The UBnFIS1 register is valid in the FIFO mode (UBnFIC0.UBnMOD bit = 1). This register can be used to read the number of empty bytes of transmit FIFOn. This register is read-only in 8-bit units.
Page 785 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) After reset: 10H Address: UB0FIS1 FFFFFA8FH, UB1FIS1 FFFFFAAFH UBnFIS1 UBnTB4 UBnTB3 UBnTB2 UBnTB1 UBnTB0 (n = 0, 1) UBnTB4 UBnTB3 UBnTB2 UBnTB1 UBnTB0 Transmit FIFOn pointer 0 bytes 1 byte 2 bytes 3 bytes 4 bytes 5 bytes 6 bytes...
Page 786: Interrupt Request Signals
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) 16.4 Interrupt Request Signals The following five types of interrupt requests are generated from UARTBn. • Reception completion interrupt request signal (INTUBnTIR) • Transmission enable interrupt request signal (INTUBnTIT) • FIFO transmission completion interrupt request signal (INTUBnTIF) •...
Page 787 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) (2) Reception completion interrupt request signal (INTUBnTIR) (a) Single mode When reception is enabled, a reception completion interrupt request signal is generated if data is shifted into the receive shift register n and stored in the UBnRX register (if the receive data can be read). When reception is disabled, no reception completion interrupt request signal is generated.
Page 788 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) (5) Reception timeout interrupt request signal (INTUBnTITO) (a) Single mode Cannot be used. (b) FIFO mode The reception timeout interrupt request signal is generated if data is stored in receive FIFOn when the next data does not come (start bit is not detected) even after the next data reception wait time specified by the UBnFIC1.UBnTC4 to UBnFIC1.UBnTC0 bits has elapsed, when the timeout counter function is used (UBnFIC1.UBnTCE bit = 1).
Page 789: Control Modes
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) 16.5 Control Modes (1) Single mode/FIFO mode The single mode or FIFO mode can be selected by using the UBnFIC0.UBnMOD bit. Caution Be sure to select the single mode when writing a transmit data or reading a received data by using the DMA control.
Page 790 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) (2) Pending mode/pointer mode The pending mode or pointer mode can be selected by using the UBnFIC0.UBnITM and UBnFIC0.UBnIRM bits in the FIFO mode (UBnFIC0.UBnMOD bit = 1). If transmission is started by writing data of more than double the amount set as the trigger by the UBnFIC2.UBnTT3 to UBnFIC2.UBnTT0 bits to transmit FIFOn, the transmission enable interrupt request signal (INTUBnTIT) may occur more than once.
Page 791 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) (ii) During reception (reading from receive FIFOn) • If data for the first reception completion interrupt request signal (INTUBnTIR) is not read from receive FIFO, the second INTUBnTIR signal does not occur (is held pending) even if the generation condition of the second INTUBnTIR is satisfied (if receive data of the number set as the trigger by the UBnFIC2.UBnRT3 to UBnFIC2.UBnRT0 bits can be read from receive FIFOn).
Page 792 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) (ii) During reception (reading from receive FIFOn) • Each time the data of 1 byte is transferred to receive FIFOn from the receive shift register n, a reception completion interrupt request signal (INTUBnTIR) occurs. •...
Page 793: Operation
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) 16.6 Operation 16.6.1 Data format Full-duplex serial data transmission and reception can be performed. The transmit/receive data format consists of one data frame containing a start bit, character bits, a parity bit, and stop bits as shown in Figure 16-2.
Page 794: Transmit Operation
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) 16.6.2 Transmit operation In the single mode (UBnFIC0.UBnMOD bit = 0), transmission is enabled when the UBnCTL0.UBnTXE bit is set to 1, and transmission is started when transmit data is written to the UBnTX register. In the FIFO mode (UBnFIC0.UBnMOD bit = 1), transmission is started when transmit data of at least the number set as the trigger by the UBnFIC2.UBnTT3 to UBnFIC2.UBnTT0 bits and 16 bytes or less is written to transmit FIFOn and then the UBnTXE bit is set to 1.
Page 795 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) (3) Transmission interrupt request signal (a) Transmission enable interrupt request signal (INTUBnTIT) • In single mode (UBnFIC0.UBnMOD bit = 0) In the single mode, the transmission enable interrupt request signal (INTUBnTIT) occurs when transmit data can be written to the UBnTX register (when 1 byte of data is transferred from the UBnTX register to the transmit shift register n).
Page 796 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) Figure 16-3. Timing of Asynchronous Serial Interface Transmission Enable Interrupt Request Signal (INTUBnTIT) TXDBn (output) Start Parity Stop INTUBnTIT (output) Remark In the FIFO mode, the INTUBnTIT signal occurs at the above timing when as many transmit data as the number set as the trigger by the UBnFIC2.UBnTT3 to UBnFIC2.UBnTT0 bits are serially transferred.
Page 797: Continuous Transmission Operation
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) 16.6.3 Continuous transmission operation Cautions 1. Be sure to check whether the transmission has been completed before performing initialization during the transmission processing (UBnSTR.UBnTSF bit = 0, but it can be checked by the generation of the FIFO transmission completion interrupt request signal (INTUBnTIF) in the FIFO mode.) 2.
Page 798: Receive Operation
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) 16.6.4 Receive operation The awaiting reception state is set by setting the UBnCTL0.UBnPWR bit to 1 and then setting the UBnCTL0.UBnRXE bit to 1. RXDBn pin sampling begins and a start bit is detected. When the start bit is detected, the receive operation begins, and data is stored sequentially in the receive shift register n according to the baud rate that was set.
Page 799 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) (3) Reception interrupt request signal (a) Reception completion interrupt request signal (INTUBnTIR) • In single mode (UBnFIC0.UBnMOD bit = 0) When UBnCTL0.UBnRXE bit = 1 and the reception of one frame of data is completed (the stop bit is detected) in the single mode, a reception completion interrupt request signal (INTUBnTIR) is generated and the receive data in the receive shift register n is transferred to the UBnRX register at the same time.
Page 800 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) (b) Reception timeout interrupt request signal (INTUBnTITO) (only in FIFO mode) When the timeout counter function (UBnFIC1.UBnTCE bit = 1) is used in the FIFO mode, the reception timeout interrupt request signal (INTUBnTITO) occurs if the next data does not come even after the next data reception wait time specified by the UBnFIC1.UBnTC4 to UBnFIC1.UBnTC0 bits has elapsed and if data is stored in receive FIFOn.
Page 801: Reception Error
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) 16.6.5 Reception error In the single mode (UBnFIC0.UBnMOD bit = 0), the three types of errors that can occur during a receive operation are a parity error, framing error, and overrun error. In the FIFO mode (UBnFIC0.UBnMOD bit = 1), the three types of errors that can occur during a receive operation are a parity error, framing error, and overflow error.
Page 802: Parity Types And Corresponding Operation
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) 16.6.6 Parity types and corresponding operation A parity bit is used to detect a bit error in communication data. Normally, the same type of parity bit is used at the transmission and reception sides. (1) Even parity (a) During transmission The parity bit is controlled so that the number of bits with the value “1”...
Page 803: Receive Data Noise Filter
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) 16.6.7 Receive data noise filter The RXDBn signal is sampled at the rising edge of the peripheral clock (f ). If the same sampling value is obtained twice, the match detector output changes, and this output is sampled as input data. Therefore, data not exceeding one clock width is judged to be noise and is not delivered to the internal circuit (see Figure 16-7).
Page 804 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) Figure 16-7. Timing of RXDBn Signal Judged as Noise RXDBn (input) Internal signal A Match Match Mismatch Mismatch (judged as noise) (judged as noise) Internal signal B Remark Peripheral clock frequency (prescaler 1 input clock frequency) In clock mode 1, f In clock mode 2, f /2 (14.64 to 16 MHz)
Page 805: Dedicated Baud Rate Generator (Brg)
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) 16.7 Dedicated Baud Rate Generator (BRG) A dedicated baud rate generator, which consists of a 16-bit programmable counter, generates serial clocks during transmission/reception in UARTBn. The dedicated baud rate generator output can be selected as the serial clock for each channel.
Page 806 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) (2) Serial clock generation A serial clock can be generated according to the settings of the UBnCTL2 register. The 16-bit counter divisor value can be selected according to the UBnCTL2.UBnBRS15 to UBnCTL2.UBnBRS0 bits. (a) Baud rate The baud rate is the value obtained according to the following formula.
Page 807 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) (3) Baud rate setting example Table 16-5. Baud Rate Generator Setting Data (1/2) Baud Rate = 32 MHz = 24 MHz = 16 MHz (bps) UBnCTL2 ERR (%) UBnCTL2 ERR (%) UBnCTL2 ERR (%) D055H 0.00 9C40H...
Page 808 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) (4) Allowable baud rate range during reception The degree to which a discrepancy from the transmission destination’s baud rate is allowed during reception is shown below. Caution The equations described below should be used to set the baud rate error during reception so that it always is within the allowable error range.
Page 809 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) Therefore, the maximum baud rate that can be received at the transfer destination is as follows. − BRmax (FLmin/11) Brate Similarly, the maximum allowable value can be obtained as follows. − × × −...
Page 810 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) (5) Transfer rate during continuous transmission During continuous transmission, the transfer rate from a stop bit to the next start bit is extended two clocks longer than normal. However, on the reception side, the transfer result is not affected since the timing is initialized by the detection of the start bit.
Page 811: Control Flow
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) 16.8 Control Flow (1) Example of continuous transmission processing flow in single mode (CPU control) Figure 16-11. Example of Continuous Transmission Processing Flow in Single Mode (CPU Control) START Set UARTBn-related registers UBnTXE = 1 (UBnCTL0) : Enable transmission Write UBnTX register : Write transmit data...
Page 812 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) (2) Example of continuous reception processing flow in single mode (CPU control) Figure 16-12. Example of Continuous Reception Processing Flow in Single Mode (CPU Control) START Set UARTBn-related registers UBnRXE = 1 (UBnCTL0) : Enable reception INTUBnTIRE interrupt = 1? : Reception error occurred?
Page 813 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) (3) Example of continuous transmission processing flow in single mode (DMA control) Figure 16-13. Example of Continuous Transmission Processing Flow in Single Mode (DMA Control) START Set UARTBn/DMAC-related Note registers Set DTFRm register : Set INTUBnTIT as DMA transfer start factor (in the case of INTUBnTIT) and clear DFm bit Emm = 1 (DCHCm)
Page 814 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) (4) Example of continuous reception processing flow in single mode (DMA control) Figure 16-14. Example of Continuous Reception Processing Flow in Single Mode (DMA Control) START Set UARTBn/DMAC-related registers Set DTFRm register : Set INTUBnTIR as DMA transfer start factor (in the case of INTUBnTIR) and clear DFm bit Emm = 1 (DCHCm) : Enable DMA transfer...
Page 815 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) (5) Example of continuous transmission processing flow in FIFO mode (CPU control) Figure 16-15. Example of Continuous Transmission Processing Flow in FIFO Mode (CPU Control) START Set UARTBn-related registers Note 1 Write transmit FIFO : Write transmit data UBnTXE = 1 (UBnCTL0) : Enable transmission...
Page 816 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) (6) Example of continuous reception processing in FIFO mode (CPU control) Figure 16-16. Example of Continuous Reception Processing in FIFO Mode (CPU Control) START Set UARTBn-related registers UBnRXE = 1 (UBnCTL0) : Enable reception INTUBnTIRE interrupt = 1? : Reception error occurred? Error processing in...
Page 817 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) (7) Example of reception error processing in single mode Figure 16-17. Example of Reception Error Processing Flow in Single Mode START Read UBnSTR register : Check error flag Clear error flag Read UBnRX register : Extract receive data (error data) Caution Reception can be continued by completing this control flow before reception of the next data is completed.
Page 818 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) (8) Example of reception error processing flow in FIFO mode (1) Figure 16-18. Example of Reception Error Processing Flow in FIFO Mode (1) START Read UBnSTR register : Check error flag Clear error flag Note UBnRXE = 0 (UBnCTL0) : Stop reception...
Page 819 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) (9) Example of reception error processing flow in FIFO mode (2) Figure 16-19. Example of Reception Error Processing Flow in FIFO Mode (2) START Read UBnSTR register : Check error flag Clear error flag Read UBnFIS0 register : Check receive FIFOn pointer Read UBnRXAP register...
Page 820: Cautions
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) 16.9 Cautions Cautions concerning UARTBn are shown below. (1) When using DMA control Be sure to select the single mode when writing a transmit data or reading a received data by using the DMA control.
Page 821 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B (UARTB) (8) Initialization during continuous transmission (pointer mode) in FIFO mode Confirm that the UBnSTR.UBnTSF bit is 0 before executing initialization during transmission processing (this can also be done by checking the FIFO transmission completion interrupt request signal (INTUBnTIF)). If initialization is executed while the UBnTSF bit is 1, the transmit data is not guaranteed.
Page 822: Chapter 17 3-Wire Variable-Length Serial I/O B (Csib)
CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) 17.1 Port Settings of CSIB0 to CSIB5 17.1.1 For V850E/SJ3-H Table 17-1. Pin Configuration Mode Alternate-Function Pin Name Port <1> Port <2> Pin No. Port Alternate Function Pin No. Port Alternate Function −...
Page 823 CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) The SIB1, SOB1, and SCKB1 pins, TMP2 I/O pins (TIP20/TOP20), and address bus pins (A7 to A9) are alternate functions of the same pins, and therefore cannot be used simultaneously. (3) CSIB2 The serial reception data, serial transmission data, and serial clock pins (SIB2, SOB2, and SCKB2) of CSIB2 are assigned to P53, P54, and P55, respectively.
Page 824: For V850E/Sk3-H
CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) 17.1.2 For V850E/SK3-H Table 17-2. Pin Configuration Mode Alternate-Function Pin Name Port <1> Port <2> Pin No. Port Alternate Function Pin No. Port Alternate Function − − − CSIB0 SIB0 SDA01 − −...
Page 825 CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) (3) CSIB2 The serial reception data, serial transmission data, and serial clock pins (SIB2, SOB2, and SCKB2) of CSIB2 are assigned to P53, P54, and P55, respectively. In addition, the SIB2, SOB2, and SCKB2 pins are assigned to P38, P310, and P39, respectively, and can be used at either one of the pins only.
Page 826: Features
CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) 17.2 Features Transfer rate: 8 Mbps max. Master mode and slave mode selectable Transfer data length selectable in 1-bit units between 8 and 16 bits Transfer data MSB-first/LSB-first switchable Serial clock and data phase switchable Transmission mode, reception mode, transmission/reception mode specifiable •...
Page 827: Configuration
CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) 17.3 Configuration The following shows the block diagram of CSIBn. Figure 17-1. Block Diagram of CSIBn Internal bus CBnCTL1 CBnCTL0 CBnCTL2 CBnSTR INTCBnT Controller INTCBnR Phase control CCLK BRGm CBnTX SCKBn Phase SO latch SOBn control...
Page 828 CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) CSIBn includes the following hardware. Table 17-3. Configuration of CSIBn Item Configuration Registers CSIBn receive data register (CBnRX) CSIBn transmit data register (CBnTX) Control registers CSIBn control register 0 (CBnCTL0) CSIBn control register 1 (CBnCTL1) CSIBn control register 2 (CBnCTL2) CSIBn status register (CBnSTR) User’s Manual U19201EJ3V0UD...
Page 829 CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) (1) CSIBn receive data register (CBnRX) The CBnRX register is a 16-bit buffer register that holds receive data. This register is read-only, in 16-bit units. The receive operation is started by reading the CBnRX register in the reception enabled status. If the transfer data length is 8 bits, the lower 8 bits of this register are read-only in 8-bit units as the CBnRXL register.
Page 830: Registers
CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) 17.4 Registers The following registers are used to control CSIBn. • CSIBn control register 0 (CBnCTL0) • CSIBn control register 1 (CBnCTL1) • CSIBn control register 2 (CBnCTL2) • CSIBn status register (CBnSTR) (1) CSIBn control register 0 (CBnCTL0) CBnCTL0 is a register that controls the CSIBn serial transfer operation.
Page 831 CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) (2/3) Note CBnDIR Specification of transfer direction mode (MSB/LSB) MSB-first transfer LSB-first transfer Note CBnTMS Transfer mode specification Single transfer mode Continuous transfer mode [In single transfer mode] The reception completion interrupt request signal (INTCBnR) is generated. Even if transmission is enabled (CBnTXE bit = 1), the transmission enable interrupt request signal (INTCBnT) is not generated.
Page 832 CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) (3/3) CBnSCE Specification of start transfer disable/enable Communication start trigger invalid Communication start trigger valid • In master mode This bit enables or disables the communication start trigger. (a) In single transmission or transmission/reception mode, or continuous transmission or continuous transmission/reception mode The setting of the CBnSCE bit has no influence on communication operation.
Page 833 CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) (a) How to use CBnSCE bit (i) In single reception mode <1> When the reception of the last data is completed with INTCBnR interrupt servicing, clear the CBnSCE bit to 0, and then read the CBnRX register. <2>...
Page 834 CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) After reset 00H Address: CB0CTL1 FFFFFD01H, CB1CTL1 FFFFFD11H, CB2CTL1 FFFFFD21H, CB3CTL1 FFFFFD31H, CB4CTL1 FFFFFD41H, CB5CTL1 FFFFFD51H CBnCTL1 CBnCKP CBnDAP CBnCKS2 CBnCKS1 CBnCKS0 (n = 0 to 5) Specification of data transmission/ CBnCKP CBnDAP reception timing in relation to SCKBn Communication...
Page 835 CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) (3) CSIBn control register 2 (CBnCTL2) CBnCTL2 is an 8-bit register that controls the number of CSIBn serial transfer bits. This register can be read or written in 8-bit units. Reset sets this register to 00H. Caution The CBnCTL2 register can be rewritten only when the CBnCTL0.CBnPWR bit = 0 or when both the CBnTXE and CBnRXE bits = 0.
Page 836 CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) (a) Transfer data length change function The CSIBn transfer data length can be set in 1-bit units between 8 and 16 bits using the CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits. When the transfer bit length is set to a value other than 16 bits, set the data to the CBnTX or CBnRX register starting from the LSB, regardless of whether the transfer start bit is the MSB or LSB.
Page 837 CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) (4) CSIBn status register (CBnSTR) CBnSTR is an 8-bit register that displays the CSIBn status. This register can be read or written in 8-bit or 1-bit units, but the CBnTSF flag is read-only. Reset sets this register to 00H.
Page 838: Interrupt Request Signals
CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) 17.5 Interrupt Request Signals CSIBn can generate the following two types of interrupt request signals. • Reception completion interrupt request signal (INTCBnR) • Transmission enable interrupt request signal (INTCBnT) Of these two interrupt request signals, the reception completion interrupt request signal has the higher priority by default, and the priority of the transmission enable interrupt request signal is lower.
Page 839: Operation
CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) 17.6 Operation 17.6.1 Single transfer mode (master mode, transmission mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (f ) = f /2 (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 000), transfer data length CCLK = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000) Remark...
Page 840 CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) (2) Operation timing CBnTSF bit INTCBnR signal SCKBn pin SOBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1...
Page 841: Single Transfer Mode (Master Mode, Reception Mode)
CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) 17.6.2 Single transfer mode (master mode, reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (f ) = f /2 (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 000), transfer data length CCLK = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000) Remark...
Page 842 CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) (1) Operation flow START CBnCTL1 register ← 00H CBnCTL2 register ← 00H (1), (2), (3) CBnCTL0 register ← A1H CBnRX register dummy read Start reception INTCBnR interrupt generated? No (7) Reception completed? Read CBnRX register CBnSCE bit = 0 (CBnCTL0)
Page 843 CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) (2) Operation timing CBnTSF bit INTCBnR signal SCKBn pin SIBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2...
Page 844: Single Transfer Mode (Master Mode, Transmission/Reception Mode)
CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) 17.6.3 Single transfer mode (master mode, transmission/reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (f ) = f /2 (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 000), transfer data length CCLK = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000) Remark...
Page 845 CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) (1) Operation flow START CBnCTL1 register ← 00H CBnCTL2 register ← 00H (1), (2), (3) CBnCTL0 register ← E1H Write CBnTX register Start transmission/reception INTCBnR interrupt generated? (7), (9) Read CBnRX register No (8) Transmission/reception completed?
Page 846 CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) (2) Operation timing CBnTSF bit INTCBnR signal SCKBn pin SOBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1...
Page 847: Single Transfer Mode (Slave Mode, Transmission Mode)
CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) 17.6.4 Single transfer mode (slave mode, transmission mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (f ) = external clock (SCKBn) (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 111), CCLK transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000) (1) Operation flow...
Page 848 CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) (2) Operation timing CBnTSF bit INTCBnR signal SCKBn pin SOBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1...
Page 849: Single Transfer Mode (Slave Mode, Reception Mode)
CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) 17.6.5 Single transfer mode (slave mode, reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (f ) = external clock (SCKBn) (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 111), CCLK transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000) (1) Operation flow...
Page 850 CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) (2) Operation timing CBnTSF bit INTCBnR signal SCKBn pin SIBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0...
Page 851: Single Transfer Mode (Slave Mode, Transmission/Reception Mode)
CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) 17.6.6 Single transfer mode (slave mode, transmission/reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (f ) = external clock (SCKBn) (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 111), CCLK transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000) (1) Operation flow...
Page 852 CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) (2) Operation timing CBnTSF bit INTCBnR signal SCKBn pin SOBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0...
Page 853: Continuous Transfer Mode (Master Mode, Transmission Mode)
CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) 17.6.7 Continuous transfer mode (master mode, transmission mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (f ) = f /2 (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 000), transfer data length CCLK = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000) Remark...
Page 854 CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) (1) Operation flow START ← CBnCTL1 register ← CBnCTL2 register (1), (2), (3) ← CBnCTL0 register (4), (8) Write CBnTX register Start transmission INTCBnT interrupt (6), (9) generated? No (7) Transmission completed? CBnTSF bit = 0? (10) (CBnSTR register)
Page 855 CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) (2) Operation timing CBnTSF bit INTCBnT signal INTCBnR signal SCKBn pin SOBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2...
Page 856: Continuous Transfer Mode (Master Mode, Reception Mode)
CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) 17.6.8 Continuous transfer mode (master mode, reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (f ) = f /2 (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 000), transfer data length CCLK = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000) Remark...
Page 857 CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) (1) Operation flow START CBnCTL1 register ← 00H CBnCTL2 register ← 00H (1), (2), (3) CBnCTL0 register ← A3H CBnRX register dummy read Start reception INTCBnR interrupt generated? CBnOVE bit = 1? (CBnSTR) Is data being received CBnSCE bit = 0...
Page 858 CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) (2) Operation timing CBnTSF bit INTCBnR signal CBnSCE bit SCKBn pin SOBn pin SIBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1...
Page 859: Continuous Transfer Mode (Master Mode, Transmission/Reception Mode)
CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) 17.6.9 Continuous transfer mode (master mode, transmission/reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (f ) = f /2 (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 000), transfer data length CCLK = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000) Remark...
Page 860 CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) (1) Operation flow START CBnCTL1 register ← 00H CBnCTL2 register ← 00H (1), (2), (3) CBnCTL0 register ← E3H Write CBnTX register Start transmission/reception INTCBnT interrupt (6), (11) generated? (11) Is data being transmitted last data? Write CBnTX register INTCBnR interrupt...
Page 861 CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) (2) Operation timing (1/2) CBnTSF bit INTCBnT signal INTCBnR signal SCKBn pin SOBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2...
Page 862 CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) (2/2) (9) When a new transmit data is written to the CBnTX register before communication completion, the next communication is started following communication completion. (10) Read the CBnRX register. (11) The transfer of the transmit data from the CBnTX register to the shift register is completed and the INTCBnT signal is generated.
Page 863: Continuous Transfer Mode (Slave Mode, Transmission Mode)
CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) 17.6.10 Continuous transfer mode (slave mode, transmission mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (f ) = external clock (SCKBn) (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 111), CCLK transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000) (1) Operation flow...
Page 864 CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) (2) Operation timing CBnTSF bit INTCBnT signal SCKBn pin SOBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1...
Page 865: Continuous Transfer Mode (Slave Mode, Reception Mode)
CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) 17.6.11 Continuous transfer mode (slave mode, reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (f ) = external clock (SCKBn) (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 111), CCLK transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000) User’s Manual U19201EJ3V0UD...
Page 866 CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) (1) Operation flow START CBnCTL1 register ← 07H CBnCTL2 register ← 00H (1), (2), (3) CBnCTL0 register ← A3H CBnRX register dummy read SCKBn pin input started? Reception start INTCBnR interrupt generated? CBnOVE bit = 1? (CBnSTR) CBnSCE bit = 0...
Page 867 CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) (2) Operation timing CBnTSF bit INTCBnR signal CBnSCE bit SCKBn pin SIBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2...
Page 868: Continuous Transfer Mode (Slave Mode, Transmission/Reception Mode)
CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) 17.6.12 Continuous transfer mode (slave mode, transmission/reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (f ) = external clock (SCKBn) (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 111), CCLK transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000) User’s Manual U19201EJ3V0UD...
Page 869 CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) (1) Operation flow START CBnCTL1 register ← 07H CBnCTL2 register ← 00H (1), (2), (3) CBnCTL0 register ← E3H Write CBnTX register SCKBn pin input started? Start transmission/reception INTCBnT interrupt (6), (11) generated? (11) Is data being transmitted...
Page 870 CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) (2) Operation timing (1/2) CBnTSF bit INTCBnT signal INTCBnR signal SCKBn pin SOBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4...
Page 871 CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) (2/2) (12) When the clock of the transfer data length set with the CBnCTL2 register is input without writing to the CBnTX register, the INTCBnR signal is generated. Clear the CBnTSF bit to 0 to end transmission/reception.
Page 872: Reception Error
CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) 17.6.13 Reception error When transfer is performed with reception enabled (CBnCTL0.CBnRXE bit = 1) in the continuous transfer mode, the reception completion interrupt request signal (INTCBnR) is generated again when the next receive operation is completed before the CBnRX register is read after the INTCBnR signal is generated, and the overrun error flag (CBnSTR.CBnOVE) is set to 1.
Page 873: Clock Timing
CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) 17.6.14 Clock timing (1/2) (i) Communication type 1 (CBnCKP and CBnDAP bits = 00) SCKBn pin SIBn capture SOBn pin Reg-R/W INTCBnT Note 1 interrupt INTCBnR Note 2 interrupt CBnTSF bit (ii) Communication type 3 (CBnCKP and CBnDAP bits = 10) SCKBn pin SIBn capture SOBn pin...
Page 874 CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) (2/2) (iii) Communication type 2 (CBnCKP and CBnDAP bits = 01) SCKBn pin SIBn capture SOBn pin Reg-R/W INTCBnT Note 1 interrupt INTCBnR Note 2 interrupt CBnTSF bit (iv) Communication type 4 (CBnCKP and CBnDAP bits = 11) SCKBn pin SIBn capture SOBn pin...
Page 875: Output Pins
CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) 17.7 Output Pins (1) SCKBn pin When CSIBn operation is disabled (CBnCTL0.CBnPWR bit = 0), the SCKBn pin output status is as follows. CBnCKP CBnCKS2 CBnCKS1 CBnCKS0 SCKBn Pin Output High impedance Other than above Fixed to high level High impedance...
Page 876: Baud Rate Generator
CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) 17.8 Baud Rate Generator The BRG1 to BRG3 and CSIB0 to CSIB5 baud rate generators are connected as shown in the following block diagram. BRG1 BRG1 CSIB0 CSIB1 BRG2 BRG2 CSIB2 CSIB3 BRG3 BRG3 CSIB4...
Page 877 CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) (1) BRGm prescaler mode registers (PRSMm) The PRSM1 to PRSM3 registers control generation of the baud rate signal for CSIB. These registers can be read or written in 8-bit or 1-bit units. Reset sets these registers to 00H.
Page 878: Baud Rate Generation
CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) (2) BRGm prescaler compare registers (PRSCMm) The PRSCM1 to PRSCM3 registers are 8-bit compare registers. These registers can be read or written in 8-bit units. Reset sets these registers to 00H. After reset: 00H Address: PRSCM1 FFFFF321H, PRSCM2 FFFFF325H, PRSCM3 FFFFF329H PRSCMm...
Page 879: Cautions
CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O B (CSIB) 17.9 Cautions (1) When transferring transmit data and receive data using DMA transfer, error processing cannot be performed even if an overrun error occurs during serial transfer. Check that the no overrun error has occurred by reading the CBnSTR.CBnOVE bit after DMA transfer has been completed.
Page 880: Chapter 18 3-Wire Variable-Length Serial I/O E (Csie)
CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O E (CSIE) The V850E/SJ3-H and V850E/SK3-H provide a clocked serial interface called 3-wire variable-length serial I/O E (CSIE). The number of channels differs depending on the product in the V850E/SJ3-H and V850E/SK3-H as shown in the table below.
Page 881: V850E/Sk3-H
CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O E (CSIE) μ Cautions 1. The CSIE0 and CSIE1 functions are not included in the PD70F3931, 70F3932, and <R> 70F3933. 2. Do not switch port settings during operation. Be sure to disable operation of the unit which does not perform the port setting and is not being used.
Page 882: Features
CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O E (CSIE) 18.2 Features Transfer rate: 8 Mbps max. Master mode and slave mode selectable Transfer data length selectable in 1-bit units between 8 and 16 bits Transfer data MSB-first/LSB-first switchable Serial clock and data phase switchable Sixteen on-chip 16-bit transmission/reception buffers (CSIBUFn) available Transmission mode, reception mode, and transmission/reception mode specifiable •...
Page 883: Configuration
CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O E (CSIE) 18.3 Configuration The following shows the block diagram of CSIEn. Figure 18-1. Block Diagram of CSIEn (1/2) Internal bus CSIEn status register CSIEn transmission buffer INTCEnTIOF (CEnSTR) register (CEnTX0) Transfer data control CSI data buffer register n (CSIBUFn) Shift register n...
Page 884 CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O E (CSIE) Figure 18-1. Block Diagram of CSIEn (2/2) Remark 2. f Peripheral clock frequency (prescaler 1 input clock frequency) In clock mode 1, f In clock mode 2, f /2 (14.64 to 16 MHz) XMPLL In clock mode 3, f (29.28 to 32 MHz)
Page 885 CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O E (CSIE) (1) Serial I/O shift registers n (SIOn) The SIOn register is an 8-bit register for converting between serial data and parallel data. SIOn is used for both transmission and reception. Data is shifted in (reception) or shifted out (transmission) beginning at either the MSB side or the LSB side. (2) CSIEn receive data buffer register (CEnRX0) The CEnRX0 register is a 16-bit buffer register that stores receive data.
Page 886 CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O E (CSIE) (3) CSIEn transmit data buffer register (CEnTX0) The CEnTX0 register is a 16-bit buffer register that stores transmit data. When transmit data is written to this register, the data is sequentially stored in the CSIBUFn register while the CSIBUFn pointer for writing is incremented.
Page 887: Control Registers
CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O E (CSIE) 18.4 Control Registers The following registers are used to control CSIEn. • CSIEn control register 0 (CEnCTL0) • CSIEn control register 1 (CEnCTL1) • CSIEn control register 2 (CEnCTL2) • CSIEn control register 3 (CEnCTL3) •...
Page 888 CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O E (CSIE) (1) CSIEn control register 0 (CEnCTL0) The CEnCTL0 register controls the operation of CSIEn. These registers can be read or written in 8-bit or 1-bit units. Writing the CEnTMS, CEnDIR, and CEnSIT bits is enabled only when CEnTXE bit = 0 and CEnRXE bit = 0.
Page 889 CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O E (CSIE) (2/2) CEnRXE Enables or disables reception Disables reception. Enables reception. • The CEnRXE bit is reset when the CEnPWR bit is cleared to 0. • When the CEnPWR bit = 1, after the CEnRXE bit has been cleared to 0, setting the CEnRXE bit to 1 before 2 cycles of the operation clock (f ) elapse is disabled.
Page 890 CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O E (CSIE) (2) CSIEn control register 1 (CEnCTL1) The CEnCTL1 register is an 8-bit register that controls the operation clock and operating mode of CSIEn. These registers can be read or written in 8-bit or 1-bit units. Data can be written to the CEnCTL1 register only when the CEnCTL0.CEnTXE bit = 0 and CEnRXE bit = 0.
Page 891 CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O E (CSIE) (2/2) CEnCKS2 CEnCKS1 CEnCKS0 Set Value (N) Base clock (f Mode XCLK Master mode Master mode Master mode Master mode Master mode Master mode Master mode − External clock (SCKEn) Slave mode •...
Page 892 CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O E (CSIE) (3) CSIEn control register 2 (CEnCTL2) The CEnCTL2 register is used to select the transfer data length of CSIEn. These registers can be read or written in 8-bit or 1-bit units. The CEnCTL2 register may be transferring data when the CEnCTL0.CEnTXE bit or CEnRXE bit is 1. Be sure to clear the CEnTXE and CEnRXE bits to 0 before writing data to the CEnCTL2 register.
Page 893 CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O E (CSIE) (4) CSIEn status register (CEnCTL3) The CEnCTL3 register is used to set the number of transfer data of CSIEn in the continuous mode (CEnCTL0.CEnTMS bit = 1). Rewriting of the CEnCTL3 register is prohibited during transfer in the continuous mode (CEnSTR.CEnTSF bit = 1).
Page 894 CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O E (CSIE) (5) CSIEn status register (CEnSTR) These registers indicate the status of the CSIBUFn register or the transfer status. These registers can be read or written in 8-bit or 1-bit units (however, bits 6 to 0 can only be read. They do not change even if they are written).
Page 895 CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O E (CSIE) (1/2) Note Note <R> After reset: 20H Address: CE0STR FFFFF908H , CE1STR FFFFF948H < > < > < > < > CEnSTR CEnPCT CEnFLF CEnEMF CEnTSF CEnSFP3 CEnSFP2 CEnSFP1 CEnSFP0 (n = 0, 1) CEnPCT Specifies clearing of the CSIBUFn pointer No operation...
Page 896 CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O E (CSIE) (2/2) CEnTSF This flag indicates transfer status Idle status Transfer or transfer start processing in progress • This flag is cleared to 0 when the CEnCTL0.CEnPWR register is cleared to 0 and the CEnPCT bit is set to 1, or when the CEnCTL0.CEnTXE bit = 0 and CEnCTL0.CEnRXE bit = 0 register are cleared to 0.
Page 897: Baud Rate Generator N (Brgn)
CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O E (CSIE) 18.5 Baud Rate Generator n (BRGn) The transfer clock of CSIEn can be selected from the output of a dedicated baud rate generator or external clock (n = 0, 1). The serial clock source is specified by the CEnCTL1 register. In the master mode (CEnCTL1.CEnCKS2 to CEnCTL1.CEnCKS0 bits = other than 111 in the CSIEn register), BRGn is selected as the clock source.
Page 898 CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O E (CSIE) (2) Baud rate The baud rate is calculated by the following expression. Baud rate = [bps] N × 2 F = f K = Value set by CEnCTL1.CEnCKS2 to CEnCTL1.CEnCKS0 bits (K = 0, 1, 2, …, 6) N = Value set by CEnCTL1.CEnMDL2 to CEnCTL1.CEnMDL0 bits (N = 1, 2, 3, …, 7) Caution If the CEnCTL1.CEnCKS2 to CEnCTL1.CEnCKS0 bits are cleared to 000, setting the CEnCTL1.CEnMDL2 to CEnCTL1.CEnMDL0 bits to 001 is prohibited.
Page 899: Operation
CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O E (CSIE) 18.6 Operation (1) Operation modes Table 18-6. Operation Modes CEnTMS Bit CEnCKS2 to CEnCKS0 Bits CEnTXE, CEnRXE Bits CEnDIR Bit CEnSIT bit Single mode Master mode Transmission, reception, MSB/LSB Enables/disables INTCEnT delay transmission/reception first mode...
Page 900 CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O E (CSIE) (2) Function of CSI data buffer registers 0, 1 (CSIBUF0, CSIBUF1) By consecutively writing the transmit data to the CEnTX0 register from where it is transferred, up to sixteen 16- bit data can be stored in the CSIBUFn register while the CSIBUFn pointer for writing is automatically incremented (n = 0, 1).
Page 901 CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O E (CSIE) Figure 18-3. Function of CSI Data Buffer Register n (CSIBUFn) Transfer data 4 Write Incremented Transfer data 3 CSIBUFn pointer Transfer data 2 Transfer data 1 SIOn load Transfer data 0 Incremented CSIBUFn pointer CSI data buffer register n (CSIBUFn)
Page 902 CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O E (CSIE) (3) Data transfer direction specification function The data transfer direction can be changed by using the CEnCTL0.CEnDIR bit (n = 0, 1). (a) MSB first (CEnDIR bit = 0) Figure 18-4. Transfer Data Length: 8 Bits (CEnCTL2.CEnDLS3 to CEnCTL2.CEnDLS0 bits = 1000), Transfer Direction: MSB First (CEnCTL0.CEnDIR bit = 0) (1/2) (i) Transfer direction: MSB first SCKEn (I/O)
Page 903 CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O E (CSIE) Figure 18-4. Transfer Data Length: 8 Bits (CEnCTL2.CEnDLS3 to CEnCTL2.CEnDLS0 bits = 1000), Transfer Direction: MSB First (CEnCTL0.CEnDIR bit = 0) (2/2) (iii) Reading from CEnRX0 register (in single mode (CEnCTL0.CEnTMS bit = 0)) CEnRX0 Undefined value Data...
Page 904 CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O E (CSIE) (b) LSB first (CEnDIR bit = 1) Figure 18-5. Transfer Data Length: 8 Bits (CEnCTL2.CEnDLS3 to CEnCTL2.CEnDLS0 bits = 1000), Transfer Direction: LSB First (CEnCTL0.CEnDIR bit = 1) (1/2) (i) Transfer direction: LSB first SCKEn (I/O) SIEn (input) SOEn (output)
Page 905 CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O E (CSIE) Figure 18-5. Transfer Data Length: 8 Bits (CEnCTL2.CEnDLS3 to CEnCTL2.CEnDLS0 bits = 1000), Transfer Direction: LSB First (CEnCTL0.CEnDIR bit = 1) (2/2) (iii) Reading from CEnRX0 register (in single mode (CEnCTL0.CEnTMS bit = 0)) CEnRX0 Data (read value)
Page 906 CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O E (CSIE) (4) Transfer data length changing function The transfer data length can be set from 8 to 16 bits in 1-bit units, by using the CEnCTL2.CEnDLS3 to CEnCTL2.CEnDLS0 bits (n = 1, 0). Figure 18-6.
Page 907 CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O E (CSIE) (5) Function to select serial clock and data phase The serial clock and data phase can be changed by using the CEnCTL1.CEnCKP, CEnCTL1.CEnDAP bits (n = 0, 1). Figure 18-7. Clock Timing (a) When CEnCKP bit = 0, CEnDAP bit = 0 SCKEn SIEn capture...
Page 908 CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O E (CSIE) (6) Master mode The master mode is set and data is transferred with the serial clock output to the CEnCTL1.CEnCKS2 to CEnCTL1.CEnCKS0 bits are set to a value other than 111 (SCKEn pin input is invalid) (n = 0, 1). The default output level of the SCKEn pin is high when the CEnCTL1.CEnCKP bit is 0, and low when the CEnCKP bit is 1.
Page 909 CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O E (CSIE) (7) Slave mode The slave mode is set when the CEnCTL1.CEnCKS2 to CEnCTL1.CEnCKS0 bits are set to 111, and data is transferred with the serial clock input to the SCKEn pin (in the slave mode, set the CEnCTL1.CEnMDL2 to CEnCTL1.CEnMDL0 bits to 000) (n = 0, 1).
Page 910 CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O E (CSIE) (9) Single mode The single mode is set when the CEnCTL0.CEnTMS bit is 0 (n = 0, 1). In this mode, transfer is started when the CEnTXE bit or CEnRXE bit is set to 1 and when data is in the CSIBUFn register (CEnSTR.CEnEMF bit = 0).
Page 911 CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O E (CSIE) Figure 18-10. Single Mode Write Incremented CSIBUFn pointer Transfer data 4 Transfer data 3 SIOn load Transfer data 2 Incremented CSIBUFn pointer Transfer data 1 Transfer data 0 CSI data buffer register n Difference (CSIBUFn) CEnSFP3 to...
Page 912 CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O E (CSIE) The transfer start conditions in single mode are shown below. CSIEn starts data transfer when these conditions are satisfied. Table 18-7. Transfer Start Conditions in Single Mode Transfer Mode CEnTXE CEnRXE CSIBUFn Register CEnRX0 Register, SCKEn Pin SIOn Register...
Page 913 CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O E (CSIE) (10) Continuous mode The continuous mode is set when the CEnCTL0.CEnTMS bit is 1 (n = 0, 1). In this mode, transfer is started when the CEnTXE bit or CEnRXE bit is 1 and when data is in the CSIBUFn register (CEnSTR.CEnEMF register).
Page 914 CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O E (CSIE) Figure 18-11. Continuous Mode Write Incremented CSIBUFn pointer Transfer data 3 SIOn load/store Transfer data 2 Incremented CSIBUFn pointer Transfer data 1 Read Incremented Transfer data 0 CSIBUFn pointer CSI data buffer register n (CSIBUFn) CEnSPF3 to CEnTX0H...
Page 915 CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O E (CSIE) The transfer start conditions in continuous mode are shown below. CSIEn starts data transfer when these conditions are satisfied. Table 18-8. Transfer Start Conditions in Continuous Mode Transfer Mode CEnTXE CEnRXE CSIBUFn Register CEnRX0 Register, SCKEn Pin SIOn Register...
Page 916 CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O E (CSIE) (11) Transmission mode The transmission mode is set when the CEnCTL0.CEnTXE bit is set to 1 and the CEnRXE bit is cleared to 0. In this mode, transmission is started by a trigger that writes transmit data to the CEnTX0 register or sets the CEnTXE bit to 1 when transmit data is in the CSIBUFn register (n = 0, 1).
Page 917 CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O E (CSIE) (14) Delay control of transmission/reception completion interrupt (INTCEnT) In the master mode (CEnCTL1.CEnCKS2 to CEnCTL1.CEnCKS0 bits = other than 111), occurrence of the transmission/reception completion interrupt (INTCEnT) can be delayed by half a clock (1/2 serial clock), depending on the setting (1) of the CEnCTL0.CEnTMS bit.
Page 918 CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O E (CSIE) (15) Output pins (a) SCKEn pin The SCKEn pin output status when the CSIEn does not perform transmission/reception. Table 18-9. SCKEn Pin Output Level in Non-Communication State CEnPWR Bit CEnPCT Bit CEnCKP Bit CEnTXE, CEnRXE Bits CEnCKS2 to CEnCKS0 Bits SCKEn Pin Output Level...
Page 919 CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O E (CSIE) <6> Setting the CE0CTL0.CE0TXE or CE0CTL0.CE0RXE bit to 1 (setting the CE1CTL0.CE1TXE or CE1CTL0.CE1RXE bit to 1): Transmission or reception is enabled (both transmission/reception can also be enabled). <7> Setting the PMC6.PMC62 bit to 1 (setting the PMC6.PMC65 bit to 1): The pin is set as the alternate function (SCKE0 and SCKE1 pin outputs).
Page 920: How To Use
CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O E (CSIE) 18.7 How to Use (1) Single mode (in master mode and transmission mode) <1> When the CEnCTL0.CEnPWR register is set to 1, supplying the operating clock is enabled. <2> Specify the transfer mode by setting the CEnCTL1 and CEnCTL2 registers. <3>...
Page 921 CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O E (CSIE) (3) Single mode (in master mode and transmission/reception mode) <1> When the CEnCTL0.CEnPWR register is set to 1, supplying the operating clock is enabled. <2> Specify the transfer mode by setting the CEnCTL1 and CEnCTL2 registers. <3>...
Page 922 CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O E (CSIE) (5) Single mode (in slave mode and reception mode) <1> When the CEnCTL0.CEnPWR register is set to 1, supplying the operating clock is enabled. <2> Specify the transfer mode by setting the CEnCTL1 and CEnCTL2 registers. <3>...
Page 923 CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O E (CSIE) (7) Continuous mode (in master mode and transmission mode) <1> When the CEnCTL0.CEnPWR register is set to 1, supplying the operating clock is enabled. <2> Specify the transfer mode by setting the CEnCTL1 and CEnCTL2 registers. <3>...
Page 924 CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O E (CSIE) (9) Continuous mode (in master mode and transmission/reception mode) <1> When the CEnCTL0.CEnPWR register is set to 1, supplying the operating clock is enabled. <2> Specify the transfer mode by setting the CEnCTL1 and CEnCTL2 registers. <3>...
Page 925 CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O E (CSIE) (11) Continuous mode (in slave mode and reception mode) <1> When the CEnCTL0.CEnPWR register is set to 1, supplying the operating clock is enabled. <2> Specify the transfer mode by setting the CEnCTL1 and CEnCTL2 registers. <3>...
Page 926 CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O E (CSIE) (12) Continuous mode (in slave mode and transmission/reception mode) <1> When the CEnCTL0.CEnPWR register is set to 1, supplying the operating clock is enabled. <2> Specify the transfer mode by setting the CEnCTL1 and CEnCTL2 registers. <3>...
Page 927: Cautions
CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O E (CSIE) 18.8 Cautions Cautions concerning CSIEn are shown below (n = 0, 1). (1) Stopping CSIEn The CSIEn unit is reset and CSIEn is stopped when the CEnCTL0.CEnPWR bit is cleared to 0. To operate CSIEn, first set the CEnPWR bit to 1.
Page 928 CHAPTER 19 I C BUS To use the I C bus function, use the P38/SDA00, P39/SCL00, P40/SDA01, P41/SCL01, P90/SDA02, <R> Note Note P91/SCL02, P614/SDA03, P615/SCL03, P00/SDA04 , P20/SDA04 (V850E/SK3-H only), P01/SCL04 Note Note <R> P21/SCL04 (V850E/SK3-H only), P67/SDA05 , P82/SDA05 (V850E/SK3-H only), P68/SCL05 , and P83/SCL05 (V850E/SK3-H only) pins as alternate functions and set them to N-ch open-drain output.
Page 929: Chapter 19 I C Bus
CHAPTER 19 I C BUS 19.1 Port Settings of I C00 to I 19.1.1 For V850E/SJ3-H Table 19-2. Pin Configuration Mode Alternate-Function Pin Name Port <1> Port <2> Pin No. Port Alternate Function Pin No. Port Alternate Function − − −...
Page 930 CHAPTER 19 I C BUS (2) I The serial transmission/reception data and serial clock pins (SDA01 and SCL01) of I C01 are assigned to P40 and P41, respectively. When using I C01, specify P40 and P41 as the SDA01 and SCL01 pins in advance, using the PMC4 and PFC4 registers.
Page 931: For V850E/Sk3-H
CHAPTER 19 I C BUS 19.1.2 For V850E/SK3-H Table 19-3. Pin Configuration Mode Alternate-Function Pin Name Port <1> Port <2> Pin No. Port Alternate Function Pin No. Port Alternate Function − − − SDA00 TXDA2/SIB2 − − − SCL00 RXDA2/SCKB2 −...
Page 932 CHAPTER 19 I C BUS (4) I The serial transmission/reception data and serial clock pins (SDA03 and SCL03) of I C03 are assigned to P614 and P615, respectively. When using I C03, specify P614 and P615 as the SDA03 and SCL03 pins in advance, using the PMC6, PFC6, and PFCE6 registers.
Page 933: Features
CHAPTER 19 I C BUS 19.2 Features C0n has the following two modes. • Operation stopped mode • I C (Inter IC) bus mode (multimasters supported) (1) Operation stopped mode In this mode, serial transfers are not performed, thus enabling a reduction in power consumption. (2) I C bus mode (multimaster support) This mode is used for 8-bit data transfers with several devices via two lines: a serial clock pin (SCL0n) and a...
Page 934: Configuration
CHAPTER 19 I C BUS 19.3 Configuration The block diagram of the I C0n is shown below. Figure 19-1. Block Diagram of I C0n (1/2) Internal bus IIC status register n (IICSn) MSTSn ALDn EXCn COIn TRCn ACKDn STDn SPDn IIC control register n (IICCn) IICEn...
Page 935 CHAPTER 19 I C BUS Figure 19-1. Block Diagram of I C0n (2/2) Remarks 2. f Peripheral clock frequency (prescaler 1 input clock frequency) In clock mode 1, f In clock mode 2, f /2 (14.64 to 16 MHz) XMPLL In clock mode 3, f (29.28 to 32 MHz) XMPLL...
Page 936 CHAPTER 19 I C BUS C0n includes the following hardware. Table 19-4. Configuration of I Item Configuration Registers IIC shift register n (IICn) Slave address register n (SVAn) Control registers IIC control register n (IICCn) IIC status register n (IICSn) IIC flag register n (IICFn) IIC clock select register n (IICCLn) IIC function expansion register n (IICXn)
Page 937 CHAPTER 19 I C BUS (7) Interrupt request signal generator This circuit controls the generation of interrupt request signals (INTIICn). An I C interrupt is generated following either of two triggers. • Falling edge of eighth or ninth clock of the serial clock (set by IICCn.WTIMn bit) •...
Page 938: Registers
CHAPTER 19 I C BUS 19.4 Registers C0n is controlled by the following registers. • IIC control register n (IICCn) • IIC status register n (IICSn) • IIC flag register n (IICFn) • IIC clock select register n (IICCLn) • IIC function expansion register n (IICXn) •...
Page 939 CHAPTER 19 I C BUS (1/4) After reset: 00H Address: IICC0 FFFFFD82H, IICC1 FFFFFD92H, IICC2 FFFFFDA2H, <R> Note 1 Note 1 IICC3, FFFFFDB2H, IICC4 FFFFFDC2H , IICC5 FFFFFDD2H <7> <6> <5> <4> <3> <2> <1> <0> IICCn IICEn LRELn WRELn SPIEn WTIMn ACKEn...
Page 940 CHAPTER 19 I C BUS (2/4) Note SPIEn Enable/disable generation of interrupt request when stop condition is detected Disabled Enabled Condition for clearing (SPIEn bit = 0) Condition for setting (SPIEn bit = 1) • Cleared by instruction • Set by instruction •...
Page 941 CHAPTER 19 I C BUS (3/4) STTn Start condition trigger Start condition is not generated. When bus is released (in STOP mode): A start condition is generated (for starting as master). The SDA0n line is changed from high level to low level while the SCLn line is high level and then the start condition is generated.
Page 942 CHAPTER 19 I C BUS (4/4) SPTn Stop condition trigger Stop condition is not generated. Stop condition is generated (termination of master device’s transfer). After the SDA0n line goes to low level, either set the SCL0n line to high level or wait until the SCL0n pin goes to high level.
Page 943 CHAPTER 19 I C BUS (2) IIC status registers n (IICSn) The IICSn registers indicate the status of the I C0n bus. These registers are read-only, in 8-bit or 1-bit units. However, the IICSn register can only be read when the IICCn.STTn bit is 1 or during the wait period.
Page 944 CHAPTER 19 I C BUS (2/3) EXCn Detection of extension code reception Extension code was not received. Extension code was received. Condition for clearing (EXCn bit = 0) Condition for setting (EXCn bit = 1) • When a start condition is detected •...
Page 945 CHAPTER 19 I C BUS (3/3) ACKDn ACK detection ACK was not detected. ACK was detected. Condition for clearing (ACKDn bit = 0) Condition for setting (ACKDn bit = 1) • When a stop condition is detected • After the SDA0n bit is set to low level at the rising •...
Page 946 CHAPTER 19 I C BUS (3) IIC flag register n (IICFn) The IICFn registers set the I C0n operation mode and indicate the I C bus status. These registers can be read or written in 8-bit or 1-bit units. However, the STCFn and IICBSYn bits are read- only.
Page 947 CHAPTER 19 I C BUS (2/2) STCENn Initial start enable trigger Start conditions cannot be generated until a stop condition is detected following operation enable (IICEn bit = 1). Start conditions can be generated even if a stop condition is not detected following operation enable (IICEn bit = 1).
Page 948 CHAPTER 19 I C BUS (4) IIC clock select register n (IICCLn) The IICCLn registers set the transfer clock for the I C0n bus. These registers can be read or written in 8-bit or 1-bit units. However, the CLDn and DADn bits are read-only. Set the IICCLn register when the IICCn.IICEn bit = 0.
Page 949 CHAPTER 19 I C BUS (5) IIC function expansion register n (IICXn) The IICXn registers set I C0n function expansion (valid only in the high-speed mode). These registers can be read or written in 8-bit or 1-bit units. Setting of the CLXn bit is performed in combination with the SMCn, CLn1, and CLn0 bits of the IICCLn register and the OCKSTHm, OCKSm1, and OCKSm0 bits of the OCKSm register (see 19.4 (6) I C0n transfer clock setting method).
Page 950 CHAPTER 19 I C BUS M × T + t M/2 × T M/2 × T SCL0n SCL0n inversion SCL0n inversion SCL0n inversion The clock to be selected can be set by the combination of the SMCn, CLn1, and CLn0 bits of the IICCLn register, the CLXn bit of the IICXn register, and the OCKSTHm, OCKSm1, and OCKSm0 bits of the OCKSm register.
Page 951 CHAPTER 19 I C BUS Table 19-5. Clock Settings (1/3) IICXa IICCLa Selection Clock Transfer Settable Peripheral Clock Operating Clock Frequency (f ) Range Mode Bit 0 Bit 3 Bit 1 Bit 0 CLXa SMCa CLa1 CLa0 2.00 MHz ≤ f ≤...
Page 952 CHAPTER 19 I C BUS Table 19-5. Clock Settings (2/3) IICXb IICCLb Selection Clock Transfer Settable Peripheral Clock Operating Clock Frequency (f ) Range Mode Bit 0 Bit 3 Bit 1 Bit 0 CLXb SMCb CLb1 CLb0 2.00 MHz ≤ f ≤...
Page 953 CHAPTER 19 I C BUS Table 19-5. Clock Settings (3/3) IICXk IICCLk Selection Clock Transfer Settable Peripheral Clock Operating Clock Frequency (f ) Range Mode Bit 0 Bit 3 Bit 1 Bit 0 CLXk SMCk CLk1 CLk0 2.00 MHz ≤ f ≤...
Page 954 CHAPTER 19 I C BUS (7) IIC division clock select register m (OCKSm) The OCKSm registers control the I C0n division clock. These registers control the I C00 and I C03 division clock via the OCKS0 register, the I C01 and I C02 division clocks via the OCKS1 register, and the I C04 and I...
Page 955 CHAPTER 19 I C BUS (8) IIC shift register n (IICn) The IICn registers are used for serial transmission/reception (shift operations) synchronized with the serial clock. These registers can be read or written in 8-bit units, but data should not be written to the IICn register during a data transfer.
Page 956: I C Bus Mode Functions
CHAPTER 19 I C BUS 19.5 I C Bus Mode Functions 19.5.1 Pin configuration The serial clock pin (SCL0n) and serial data bus pin (SDA0n) are configured as follows. SCL0n ....This pin is used for serial clock input and output. This pin is an N-ch open-drain output for both master and slave devices.
Page 957: C Bus Definitions And Control Methods
CHAPTER 19 I C BUS 19.6 I C Bus Definitions and Control Methods The following section describes the I C bus’s serial data communication format and the signals used by the I C bus. The transfer timing for the “start condition”, “address”, “transfer direction specification”, “data”, and “stop condition” generated on the I C bus’s serial data bus is shown below.
Page 958: Start Condition
CHAPTER 19 I C BUS 19.6.1 Start condition A start condition is met when the SCL0n pin is high level and the SDA0n pin changes from high level to low level. The start condition for the SCL0n and SDA0n pins is generated that the master device to the slave device when starting a serial transfer.
Page 959: Addresses
CHAPTER 19 I C BUS 19.6.2 Addresses The 7 bits of data that follow the start condition are defined as an address. An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the master device via the bus lines.
Page 960: Transfer Direction Specification
CHAPTER 19 I C BUS 19.6.3 Transfer direction specification In addition to the 7-bit address data, the master device sends 1 bit that specifies the transfer direction. When this transfer direction specification bit has a value of 0, it indicates that the master device is transmitting data to a slave device.
Page 961: Ack
CHAPTER 19 I C BUS 19.6.4 ACK ACK is used to confirm the serial data status of the transmitting and receiving devices. The receiving device returns ACK for every 8 bits of data it receives. The transmitting device normally receives ACK after transmitting 8 bits of data. When ACK is returned from the receiving device, the reception is judged as normal and processing continues.
Page 962: Stop Condition
CHAPTER 19 I C BUS 19.6.5 Stop condition When the SCL0n pin is high level, changing the SDA0n pin from low level to high level generates a stop condition. A stop condition is generated when serial transfer from the master device to the slave device has been completed. When used as the slave device, the start condition can be detected.
Page 963: Wait State
CHAPTER 19 I C BUS 19.6.6 Wait state A wait state is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). Setting the SCL0n pin to low level notifies the communication partner of the wait state. When the wait state has been canceled for both the master and slave devices, the next data transfer can begin.
Page 964 CHAPTER 19 I C BUS Figure 19-10. Wait State (2/2) (b) When master and slave devices both have a nine-clock wait (master: transmission, slave: reception, and ACKEn bit = 1) Master and slave both wait Master after output of ninth clock. IICn data write (cancel wait state) IICn SCL0n...
Page 965: Wait State Cancellation Method
CHAPTER 19 I C BUS 19.6.7 Wait state cancellation method In the case of I C0n, wait state can be canceled normally in the following ways. • By writing data to the IICn register • By setting the IICCn.WRELn bit to 1 (wait state cancellation) •...
Page 966: I C Interrupt Request Signals (Intiicn)
CHAPTER 19 I C BUS 19.7 I C Interrupt Request Signals (INTIICn) The following shows the value of the IICSn register at the INTIICn interrupt request signal generation timing and at the INTIICn signal timing. Remarks 1. ST: Start condition AD6 to AD0: Address R/W: Transfer direction specification...
Page 967: Master Device Operation
CHAPTER 19 I C BUS 19.7.1 Master device operation (1) Start ~ Address ~ Data ~ Data ~ Stop (normal transmission/reception) <1> When IICCn.WTIMn bit = 0 IICCn.SPTn bit = 1 ↓ AD6 to AD0 D7 to D0 D7 to D0 Δ5 1: IICSn register = 1000X110B 2: IICSn register = 1000X000B...
Page 968 CHAPTER 19 I C BUS (2) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart) <1> When WTIMn bit = 0 STTn bit = 1 SPTn bit = 1 ↓ ↓ AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 Δ7...
Page 969 CHAPTER 19 I C BUS (3) Start ~ Code ~ Data ~ Data ~ Stop (extension code transmission) <1> When WTIMn bit = 0 SPTn bit = 1 ↓ AD6 to AD0 D7 to D0 D7 to D0 Δ5 1: IICSn register = 1010X110B 2: IICSn register = 1010X000B Note 3: IICSn register = 1010X000B (WTIMn bit = 1...
Page 970: Slave Device Operation (When Receiving Slave Address (Address Match))
CHAPTER 19 I C BUS 19.7.2 Slave device operation (when receiving slave address (address match)) (1) Start ~ Address ~ Data ~ Data ~ Stop <1> When IICCn.WTIMn bit = 0 AD6 to AD0 D7 to D0 D7 to D0 Δ4 1: IICSn register = 0001X110B 2: IICSn register = 0001X000B...
Page 971 CHAPTER 19 I C BUS (2) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, address match) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 Δ5 1: IICSn register = 0001X110B 2: IICSn register = 0001X000B...
Page 972 CHAPTER 19 I C BUS (3) Start ~ Address ~ Data ~ Start ~ Code ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, address mismatch (extension code reception)) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 Δ5 1: IICSn register = 0001X110B...
Page 973 CHAPTER 19 I C BUS (4) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, address mismatch (= not extension code)) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 Δ4 1: IICSn register = 0001X110B...
Page 974: Slave Device Operation (When Receiving Extension Code)
CHAPTER 19 I C BUS 19.7.3 Slave device operation (when receiving extension code) Always under communication when receiving the extension code. (1) Start ~ Code ~ Data ~ Data ~ Stop <1> When IICCn.WTIMn bit = 0 AD6 to AD0 D7 to D0 D7 to D0 Δ4...
Page 975 CHAPTER 19 I C BUS (2) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, address match) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 Δ5 1: IICSn register = 0010X010B 2: IICSn register = 0010X000B...
Page 976 CHAPTER 19 I C BUS (3) Start ~ Code ~ Data ~ Start ~ Code ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, extension code reception) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 Δ5 1: IICSn register = 0010X010B 2: IICSn register = 0010X000B...
Page 977 CHAPTER 19 I C BUS (4) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, address mismatch (= not extension code)) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 Δ4 1: IICSn register = 0010X010B...
Page 978: Operation Without Communication
CHAPTER 19 I C BUS 19.7.4 Operation without communication (1) Start ~ Code ~ Data ~ Data ~ Stop AD6 to AD0 D7 to D0 D7 to D0 Δ1 Δ 1: IICSn register = 00000001B Remarks 1. Δ: Generated only when SPIEn bit = 1 μ...
Page 979: Arbitration Loss Operation (Operation As Slave After Arbitration Loss)
CHAPTER 19 I C BUS 19.7.5 Arbitration loss operation (operation as slave after arbitration loss) When the device is used as the master in a multi-master system, read the IICSn.MSTSn bit to check the arbitration result each time the INTIICn interrupt has been generated. (1) When arbitration loss occurs during transmission of slave address data <1>...
Page 980 CHAPTER 19 I C BUS (2) When arbitration loss occurs during transmission of extension code <1> When WTIMn bit = 0 AD6 to AD0 D7 to D0 D7 to D0 Δ4 1: IICSn register = 0110X010B 2: IICSn register = 0010X000B 3: IICSn register = 0010X000B Δ...
Page 981: Operation When Arbitration Loss Occurs (No Communication After Arbitration Loss)
CHAPTER 19 I C BUS 19.7.6 Operation when arbitration loss occurs (no communication after arbitration loss) When the device is used as the master in a multi-master system, read the IICSn.MSTSn bit to check the arbitration result each time the INTIICn interrupt has been generated. (1) When arbitration loss occurs during transmission of slave address data AD6 to AD0 D7 to D0...
Page 982 CHAPTER 19 I C BUS (3) When arbitration loss occurs during data transfer <1> When IICCn.WTIMn bit = 0 AD6 to AD0 D7 to D0 D7 to D0 Δ3 1: IICSn register = 10001110B 2: IICSn register = 01000000B Δ 3: IICSn register = 00000001B Remarks 1.
Page 983 CHAPTER 19 I C BUS (4) When arbitration loss occurs due to restart condition during data transfer <1> Not extension code (Example: Address mismatch) AD6 to AD0 D7 to Dn AD6 to AD0 D7 to D0 Δ3 1: IICSn register = 1000X110B 2: IICSn register = 01000110B Δ...
Page 984 CHAPTER 19 I C BUS (5) When arbitration loss occurs due to stop condition during data transfer AD6 to AD0 D7 to Dn Δ2 1: IICSn register = 1000X110B Δ 2: IICSn register = 01000001B Remarks 1. : Always generated Δ: Generated only when SPIEn bit = 1 X: don’t care Dn = D6 to D0...
Page 985 CHAPTER 19 I C BUS (6) When arbitration loss occurs due to low level of SDA0n pin when attempting to generate a restart condition <1> When WTIMn bit = 0 IICCn.STTn bit = 1 ↓ AD6 to AD0 D7 to D0 D7 to D0 D7 to D0 Δ5...
Page 986 CHAPTER 19 I C BUS (7) When arbitration loss occurs due to a stop condition when attempting to generate a restart condition <1> When WTIMn bit = 0 STTn bit = 1 ↓ AD6 to AD0 D7 to D0 Δ4 1: IICSn register = 1000X110B 2: IICSn register = 1000X000B (WTIMn bit = 1) 3: IICSn register = 1000XX00B...
Page 987 CHAPTER 19 I C BUS (8) When arbitration loss occurs due to low level of SDA0n pin when attempting to generate a stop condition <1> When WTIMn bit = 0 IICCn.SPTn bit = 1 ↓ AD6 to AD0 D7 to D0 D7 to D0 D7 to D0 Δ5...
Page 988: Interrupt Request Signal (Intiicn) Generation Timing And Wait Control
CHAPTER 19 I C BUS 19.8 Interrupt Request Signal (INTIICn) Generation Timing and Wait Control The setting of the IICCn.WTIMn bit determines the timing by which the INTIICn register is generated and the corresponding wait control, as shown below. Table 19-6. INTIICn Generation Timing and Wait Control WTIMn Bit During Slave Device Operation During Master Device Operation...
Page 989: Address Match Detection Method
CHAPTER 19 I C BUS (4) Wait state cancellation method The four wait state cancellation methods are as follows. • By writing data to the IICn register • By setting the IICCn.WRELn bit to 1 (wait cancellation) • By setting the IICCn.STTn bit to 1 (start condition generation) Note •...
Page 990: Extension Code
CHAPTER 19 I C BUS 19.11 Extension Code μ <R> Remark Only PD70F3931 (V850E/SJ3-H), 70F3932 (V850E/SJ3-H), and 70F3933 (V850E/SJ3-H): n = 0 to 3 μ Other than PD70F3931 (V850E/SJ3-H), 70F3932 (V850E/SJ3-H), and 70F3933 (V850E/SJ3-H): n = 0 to 5 (1) When the higher 4 bits of the receive address are either 0000 or 1111, the extension code flag (IICSn.EXCn bit) is set for extension code reception and an interrupt request signal (INTIICn) is issued at the falling edge of the eighth clock.
Page 991: Arbitration
CHAPTER 19 I C BUS 19.12 Arbitration When several master devices simultaneously generate a start condition (when the IICCn.STTn bit is set to 1 before the IICSn.STDn bit is set to 1), communication between the master devices is performed while the number of clocks is adjusted until the data differs.
Page 992: Wakeup Function
CHAPTER 19 I C BUS Table 19-8. Status During Arbitration and Interrupt Request Signal Generation Timing Status During Arbitration Interrupt Request Generation Timing Note 1 Transmitting address transmission At falling edge of eighth or ninth clock following byte transfer Read/write data after address transmission Transmitting extension code Read/write data after extension code transmission Transmitting data...
Page 993: Communication Reservation
CHAPTER 19 I C BUS 19.14 Communication Reservation 19.14.1 When communication reservation function is enabled (IICFn.IICRSVn bit = 0) To start master device communications when not currently using the bus, a communication reservation can be made to enable transmission of a start condition when the bus is released. There are two modes in which the bus is not used.
Page 994 CHAPTER 19 I C BUS Table 19-9. Wait Periods CLXn Bit SMCn Bit CLn1 Bit CLn0 Bit OCKSm Register Wait Time 23 clocks 46 clocks 69 clocks 92 clocks 115 clocks 43 clocks 86 clocks 129 clocks 172 clocks 215 clocks 43 clocks Note 34 clocks...
Page 995 CHAPTER 19 I C BUS Figure 19-12. Communication Reservation Timing STTn Write Program processing to IICn Set SPDn Communication Hardware processing reservation STDn INTIICn SCL0n SDA0n Generated by master with bus access μ <R> Remark Only PD70F3931 (V850E/SJ3-H), 70F3932 (V850E/SJ3-H), and 70F3933 (V850E/SJ3-H): n = 0 to 3 μ...
Page 996 CHAPTER 19 I C BUS The communication reservation flowchart is illustrated below. Figure 19-14. Communication Reservation Flowchart Sets STTn bit (communication reservation). SET1 STTn Define communication Defines that communication reservation is in effect reservation (defines and sets user flag to any part of RAM). Secures wait period set by software (see Table 19-9).
Page 997: When Communication Reservation Function Is Disabled (Iicfn.iicrsvn Bit = 1)
CHAPTER 19 I C BUS 19.14.2 When communication reservation function is disabled (IICFn.IICRSVn bit = 1) When the IICCn.STTn bit is set when the bus is not used in a communication during bus communication, this request is rejected and a start condition is not generated. There are two modes in which the bus is not used. •...
Page 998: Cautions
CHAPTER 19 I C BUS 19.15 Cautions μ <R> Remark Only PD70F3931 (V850E/SJ3-H), 70F3932 (V850E/SJ3-H), and 70F3933 (V850E/SJ3-H): n = 0 to 3 μ Other than PD70F3931 (V850E/SJ3-H), 70F3932 (V850E/SJ3-H), and 70F3933 (V850E/SJ3-H): n = 0 to 5 (1) When IICFn.STCENn bit = 0 Immediately after the I C0n operation is enabled, the bus communication status (IICFn.IICBSYn bit = 1) is recognized regardless of the actual bus status.
Page 999 CHAPTER 19 I C BUS (7) Switching DMA transfer start factor (a) Switching DMA transfer start factor between INTUA1R and INTIIC2 signals Setting the DMA transfer start factor to other than the following combinations is prohibited. <1> When using UARTA1 and I C02 simultaneously, and the INTUA1R signal is specified as the DMA transfer start factor (V850E/SK3-H only) When the DTFRn.IFCn5 to IFCn0 bits = 28H, set the DTFROB1 bit of the option byte (0000007AH)
Page 1000: Communication Operations
CHAPTER 19 I C BUS 19.16 Communication Operations The following shows three operation procedures with the flowchart. (1) Master operation in single master system The flowchart when using the V850E/SJ3-H or V850E/SK3-H as the master in a single master system is shown below.

Renesas V850E/SJ3-H Series User Manual

Chapter 1 Introduction

Chapter 2 Pin Functions

Chapter 3 Cpu Function

Chapter 4 Port Functions

Chapter 5 Bus Control Function

Chapter 6 Clock Generation Function

Chapter 7 16-Bit Timer/Event Counter P (Tmp)

Chapter 8 16-Bit Timer/Event Counter Q (Tmq)

Chapter 9 16-Bit Interval Timer M (Tmm)

Chapter 10 Watch Functions

Chapter 11 Functions of Watchdog Timer 2

Chapter 12 Real-Time Output Function (Rto)

Chapter 13 A/D Converter

Chapter 14 D/A Converter

Chapter 15 Asynchronous Serial Interface a (Uarta)

Chapter 16 Asynchronous Serial Interface B (Uartb)

Chapter 17 3-Wire Variable-Length Serial I/O B (Csib)

Chapter 18 3-Wire Variable-Length Serial I/O E (Csie)

Chapter 19 I C Bus

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Summary of Contents for Renesas V850E/SJ3-H Series