Renesas M16C/64A Series User Manual page 102

M16C/64A Group
VW1C2 (Voltage change detection flag) (b2)
The VW1C2 bit is enabled when the VC26 bit in the VCR2 register is 1 (voltage detector 1 enabled).
This bit does not change even if set to 1.
Condition to become 0:
•
Setting this bit to 0
Conditions to become 1:
•
Refer to the following table.
Table 7.4 Conditions under Which the VW1C2 Bit Becomes 1
(1)
Bit Setting
WV1C1 VW1C6
0
0
1
0
1
1
Note:
1. Only set the values listed above.
VW1C3 (Voltage detector 1 signal monitor flag) (b3)
The VW1C3 bit is enabled when the VW12E bit in the VWCE register is 1 (voltage monitors 1 and 2
enabled) and the VC26 bit in the VCR2 register is 1 (voltage detector 1 enabled).
Condition to become 0:
•
VCC1 < Vdet1 (when the VW12E bit is 1 and the VC26 bit is 1)
Conditions to become 1:
VCC1 ≥ Vdet1 (when the VW12E bit is 1 and the VC26 bit is 1)
•
•
The VC26 bit in the VCR2 register is 0 (voltage detector 1 disabled).
After a hardware reset, power-on reset, voltage monitor 0 reset, voltage monitor 1 reset, or voltage
monitor 2 reset, the reference level of Vdet1 switches because value in the VD1LS register changes.
When monitoring the voltage detector 1 signal level, set the value to the VD1LS register again, then set
the VW1C3 bit.
The VW12E bit in the VWCE register becomes 0 from a reset. When monitoring the voltage detector 1
signal level, set the VW12E bit to 1 again.
VW1C6 (Voltage monitor 1 mode select bit) (b6)
The VW1C6 bit is enabled when the VW1C0 bit is 1 (voltage monitor 1 interrupt/reset enabled).
VW1C7 (Voltage monitor 1 interrupt/reset generation condition select bit) (b7)
The voltage monitor 1 interrupt/reset generation condition can be selected by the VW1C7 bit when the
VW1C6 bit is 0 (voltage monitor 1 interrupt at Vdet1 passage) and the VW1C1 bit is 1 (digital filter
disabled).
When the VW1C6 bit is 1 (voltage monitor 1 reset at Vdet1 passage), set the VW1C7 bit to 1 (when
VCC1 reaches Vdet1 or below). (Do not set the VW1C7 bit to 0.)
When the VW1C1 bit is 0 (digital filter enabled), regardless of the VW1C7 bit's setting, the voltage
monitor 1 interrupt is generated when VCC1 reaches, or goes above of below Vdet1.
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
VW1C7
0 or 1 The VW1C3 bit changes from 0 to 1 or from 1 to 0.
1 The VW1C3 bit changes from 1 to 0.
0 The VW1C3 bit changes from 0 to 1.
1 The VW1C3 bit changes from 1 to 0.
1 The VW1C3 bit changes from 1 to 0.
Condition
7. Voltage Detector
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