Renesas M16C/64A Series User Manual page 624

M16C/64A Group
CFALL1-CFALL0 (Falling timing select bit) (b5-b4)
The falling timing of the signal in transmission is specified. Do not write to bits CFALL1 to CFALL0 while
transmitting/receiving.
Table 26.7 Falling Timing of Signal in Transmission
Bits CFALL1 to CFALL0
00b
01b
10b
11b
CREGFLG (Receive edge detect flag) (b6)
See Figure 26.2 "Operation of Bits CREGFLG and CREGCLR".
Condition to become 0:
•
Set the CREGCLR bit in the CECC3 register to 1.
Condition to become 1:
•
Detect a low level input to CEC while the CREGCLR bit is 0.
CABTWEN (Error low pulse output wait control bit) (b7)
This bit is enabled when the CABTEN bit is 1 (low pulse output enabled in reception error).
If a receive error occurs when the CABTWEN bit is set to 1 (low pulse output at rising edge of the CEC
signal) and the CEC input is low, a 3.6 ms low-level pulse is output from the rising edge of the CEC
signal after the error. If there is no rising edge of the CEC signal within 3.6 ms from the reception error,
a low-level pulse is not output because it is assumed that another device output an error low-level
pulse.
Do not write to the CABTWEN bit while transmitting/receiving.
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
Start bit
Standard value
Standard value - 40 μ s
Standard value - 100 μ s
Standard value - 160 μ s
26. Consumer Electronics Control (CEC) Function
Falling Timing
Standard value
Standard value - 190 μ s
Standard value - 250 μ s
Standard value - 310 μ s
Data bit
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