Renesas M16C/64A Series User Manual page 180

M16C/64A Group
RDY Signal
11.3.5.6
This signal is provided for accessing external devices which need to be accessed at low speed. If
input to the RDY pin is low at the last falling edge of BCLK in the bus cycle, one wait state is inserted
in the bus cycle. While in wait state, the following signals retain the state in which they were when the
RDY signal was acknowledged:
A0 to A19, D0 to D15, CS0 to CS3 , RD , WRL , WRH , WR , BHE , ALE, HLDA
Then, when input to the RDY pin is detected high at the falling edge of BCLK, the remaining bus cycle
is executed. Figure 11.4 shows Examples in Which Wait State Was Inserted into Read Cycle by RDY
Signal. To use the RDY signal, set the corresponding bit (among bits CS3W to CS0W) in the CSR
register to 0 (with wait state). When not using the RDY signal, pull-up the RDY pin.
Separate bus
BCLK
RD
CSi
(i = 0 to 3)
RDY
Multiplexed bus
BCLK
RD
CSi
(i = 0 to 3)
RDY
tsu(RDY - BCLK)
The above diagrams assume bits CSEi1W to CSEi0W (i = 0 to 3) in the CSE register are 00b (one wait).
Examples in Which Wait State Was Inserted into Read Cycle by RDY Signal
Figure 11.4
11.3.5.7 BCLK Output
When the PM07 bit in the PM0 register is set to 0 (output enabled), a clock with the same frequency
as the CPU clock is output as BCLK from the BCLK pin. Refer to 8.4 "CPU Clock and Peripheral
Function Clocks".
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
tsu(RDY - BCLK)
Accept timing of RDY signal
Accept timing of RDY signal
: Wait using RDY signal
: Wait using software
: Duration for RDY input setup
tsu(RDY - BCLK)
11. Bus
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