Uarti Special Mode Register 2 (Uismr2) (I = 0 To 2, 5 To 7) - Renesas M16C/64A Series User Manual

M16C/64A Group

23.2.11 UARTi Special Mode Register 2 (UiSMR2) (i = 0 to 2, 5 to 7)

UARTi Special Mode Register 2 (i = 0 to 2, 5 to 7)
b7 b6 b5 b4 b3 b2 b1
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
Symbol
b0
U0SMR2, U1SMR2, U2SMR2
U5SMR2, U6SMR2, U7SMR2
Bit Symbol Bit Name
2
IICM2 I C mode select bit 2
CSC Clock synchronization bit
SWC SCL wait auto insert bit
ALS SDA output auto stop bit
STAC UARTi auto initialize bit
SWC2 SCL wait output bit 2
SDHI SDA output disable bit
—
No register bit. If necessary, set to 0. The read value is undefined.
(b7)
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
Address
0246h, 0256h, 0266h
0286h, 0296h, 02A6h
Function
0 : Use NACK/ACK interrupt
1 : Use transmit/receive interrupt
0 : Clock synchronization disabled
1 : Clock synchronization enabled
0 : No wait-state/wait-state cleared
1 : Hold the SCLi pin low after the eighth bit
is received
When arbitration lost is detected,
0 : Do not stop the SDAi output
1 : Stop the SDAi output
When the start condition is detected,
0 : Do not initialize the circuit
1 : Initialize the circuit
0: Output the transmit/receive clock at the
SCLi pin
1: Hold the SCLi pin low
0: Output data
1: Stop the output (high-impedance)
Reset Value
X000 0000b
X000 0000b
RW
RW
RW
RW
RW
RW
RW
RW
—
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