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M16C/64A Group
6.2.2
Reset Source Determine Register (RSTFR)
Reset Source Determine Register
b7
b6 b5 b4
b3
b2
b1
0
Table 6.5
RSTFR Register Reset Value
Reset
Hardware reset
Power-on reset
Voltage monitor 0 reset
Voltage monitor 1 reset
Voltage monitor 2 reset
Oscillator stop detect reset
Watchdog timer reset
Software reset
CWR (Cold/warm start discrimination flag) (b0)
The CWR bit also changes when the either of following condition is met:
Condition to become 0:
•
Power-on
Condition to become 1:
•
Setting this bit to 1
OSDR (Oscillator stop detect reset detect flag) (b6)
The OSDR bit also changes when either of following condition is met:
Conditions to become 0:
•
Power-on
•
Setting this bit to 0
This bit will not become 1 even when written to 1.
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
b0
Symbol
RSTFR
Bit Symbol
Bit Name
Cold start/warm start
CWR
discrimination flag
HWR
Hardware reset detection flag
SWR
Software reset detection flag
Watchdog timer reset detect
WDR
flag
Voltage monitor 1 reset
LVD1R
detection flag
Voltage monitor 2 reset
LVD2R
detection flag
Oscillator stop detect reset
OSDR
detect flag
—
Reserved bit
(b7)
OSDR
LVD2R
No change
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
Address
0018h
0 : Cold start
1 : Warm start
0 : Not detected
1 : Detected
0 : Not detected
1 : Detected
0 : Not detected
1 : Detected
0 : Not detected
1 : Detected
0 : Not detected
1 : Detected
0 : Not detected
1 : Detected
If necessary, set to 0. When read, the
read value is undefined.
Bits in the RSTFR Register
LVD1R
WDR
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
Reset Value
See Table 6.5.
Function
RW
RW
RO
RO
RO
RO
RO
RW
RW
SWR
HWR
0
1
No change
0
0
0
0
0
0
No change
0
0
No change
0
0
No change
0
0
No change
1
0
No change
Page 47 of 800
6. Resets
CWR
0
0
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