Renesas M16C/64A Series User Manual page 194

M16C/64A Group
In the example below, the CS pin of a 4-MB ROM is connected to the MCU's CS0 pin. The 4-MB ROM
address input pins AD21, AD20, and AD19 are connected to the MCU's CS3 , CS2 , and CS1 pins,
respectively. The address input AD18 pin is connected to the MCU's A19 pin. Figure 12.6 to Figure 12.8
show the relationship of addresses between the 4-MB ROM and the MCU in the connection example of
Figure 12.5.
In microprocessor mode or memory expansion mode, where the PM13 bit in the PM1 register is 0,
banks are located every 512 KB. Setting the OFS bit in the DBR register to 1 (offset) allows the
accessed address to be offset by 40000h, allowing even data overlapping at a bank boundary to be
accessed in succession.
In memory expansion mode, where the PM13 bit is 1, each 512-KB bank can be accessed in 256 KB
units by switching them with the OFS bit.
Because the SRAM can be accessed when the chip select signals S2 is high and S1 is low, CS0 and
CS2 can be connected to S2 and S1 , respectively. If SRAM does not have the input pins that accept
high active and low active chip select signals ( S1 , S2), CS0 and CS2 should be decoded externally to
the chip.
Note:
Figure 12.5 External Memory Connection Example in 4-MB Mode
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
D0 to D7
A0 to A16
A17
A19
CS1
CS2
CS3
RD
CS0
WR
1. If only one chip select pin (S1 or S2) is present, use an external circuit for decoding.
12. Memory Space Expansion Function
8
DQ0 to DQ7
17
AD0 to AD16
AD17
AD18
AD19
AD20
AD21
OE
CS
DQ0 to
DQ7
AD0 to
AD16
OE
S2
(1)
S1
W
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