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M16C/64A Group
Table 23.22
Registers Used and Settings in Special Mode 2
Register
PCLKR
UiTB
UiRB
8, 11, 13 to 15
UiBRG
SMD2 to SMD0
UiMR
CLK0, CLK1
UiC0
UiC1
UiSMR
UiSMR2
UiSMR3
0, 2, 4 to 7
UiSMR4
UCON
CLKMD0
CLKMD1, RCSP, 7 Set to 0.
i = 0 to 2, 5 to 7
j = 2, 5 to 7
;
Notes:
1.
This table does not describe a procedure.
2.
The TXD2 pin is N-channel open drain output. Nothing is assigned to the NCH bit in the U2C0
register. Only write 0 to this bit.
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
Bits
PCLK1
Select the count source for the UiBRG register.
0 to 7
Set transmission data.
8
- (does not need to be set) If necessary, set to 0.
0 to 7
Reception data can be read.
OER
Overrun error flag
When read, the read value is undefined.
0 to 7
Set bit rate.
Set to 001b.
CKDIR
Set to 0.
4 to 6
Set to 0.
IOPOL
Set to 0.
Select the count source for the UiBRG register.
CRS
Disabled because CRD is 1
TXEPT
Transmit register empty flag
CRD
Set to 1.
NCH
Select TXDi pin output format.
Clock phases can be set in combination with the CKPH bit in the
CKPOL
UiSMR3 register.
UFORM
Select the LSB first or MSB first.
TE
Set to 1 to enable transmission/reception.
TI
Transmit buffer empty flag
RE
Set to 1 to enable reception.
RI
Reception complete flag
UjIRS
Select UARTj transmit interrupt source.
UjRRM
Set to 1 to use continuous receive mode.
UiLCH
Set to 1 to use inverted data logic.
UiERE
Set to 0.
0 to 7
Set to 0.
0 to 7
Set to 0.
Clock phases can be set in combination with the CKPOL bit in the
CKPH
UiC0 register.
NODC
Set to 0.
Set to 0.
0 to 7
Set to 0.
U0IRS
Select UART0 transmit interrupt source.
U1IRS
Select UART1 transmit interrupt source.
U0RRM
Set to 1 to use continuous receive mode.
U1RRM
Set to 1 to use continuous receive mode.
Disabled because CLKMD1 is 0
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
(1)
Function
(2)
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