Notes On Real-Time Clock; Starting And Stopping The Count; Register Settings (Time Data, Etc.); Register Settings (Compare Data) - Renesas M16C/64A Series User Manual

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M16C/64A Group
20.5

Notes on Real-Time Clock

20.5.1

Starting and Stopping the Count

The real-time clock uses the TSTART bit for instructing the count to start or stop, and the TCSTF bit
which indicates count started or stopped. Bits TSTART and TCSTF are in the RTCCR1 register.
The real-time clock starts counting and the TCSTF bit becomes 1 (count started) when the TSTART bit
is set to 1 (count started). It takes up to two cycles of the count source until the TCSTF bit becomes 1
after setting the TSTART bit to 1. During this time, do not access registers associated with the real-time
(1)
clock
other than the TCSTF bit.
Similarly, when setting the TSTART bit to 0 (count stopped), the real-time clock stops counting and the
TCSTF bit becomes 0 (count stopped). It takes up to three cycles of the count source until the TCSTF
bit becomes 0 after setting the TSTART bit to 0. During this time, do not access registers associated
with the real-time clock other than the TCSTF bit.
Note:
1.
Registers associated with the real-time clock: RTCSEC, RTCMIN, RTCHR, RTCWK, RTCCR1,
RTCCR2, RTCCSR, RTCCSEC, RTCCMIN, and RTCCHR.
20.5.2

Register Settings (Time Data, etc.)

Write to the following registers/bits when the real-time clock is stopped:
Registers RTCSEC, RTCMIN, RTCHR, RTCWK, and RTCCR2
Bits H12H24 and RTCPM in the RTCCR1 register
Bits RCS0 to RCS4 in the RTCCSR register
The real-time clock is stopped when bits TSTART and TCSTF in the RTCCR1 register are 0 (real-time
clock stopped).
Set the RTCCR2 register after setting the registers and bits mentioned above (immediately before the
real-time clock count starts).
Figure 20.4 shows Time and Day Change Procedure (No Compare Mode or Compare Mode 1), and
Figure 20.5 shows Time and Day Change Procedure (Compare Mode 2 or Compare Mode 3).
20.5.3

Register Settings (Compare Data)

Write to the following registers when the BSY bit in the RTCSEC register is 0 (not while data is
updated).
Registers RTCCSEC, RTCCMIN, and RTCCHR
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
20. Real-Time Clock
Page 391 of 800

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