Pll Clock; 125 Khz On-Chip Oscillator Clock (Foco-S) - Renesas M16C/64A Series User Manual

M16C/64A Group
8.3.2

PLL Clock

PLL clock is generated by the PLL frequency synthesizer. This clock is used as the clock source for the
CPU and peripheral function clocks.
After reset, the PLL frequency synthesizer is stopped.
PLL clock is a clock which divides the main clock by the selected values of bits PLC05 to PLC04 in the
PLC0 register, and then multiplied by the selected values of bits PLC02 to PLC00. Set bits PLC05 and
PLC04 to fit divided frequency between 2 MHz and 5 MHz. Figure 8.3 shows Relation between Main
Clock and PLL Clock.
Main clock
Figure 8.3 Relation between Main Clock and PLL Clock
Table 8.5 Example Settings for PLL Clock Frequencies
Main Clock
10 MHz
5 MHz
12 MHz
6 MHz
8.3.3

125 kHz On-Chip Oscillator Clock (fOCO-S)

This clock is approximately 125 kHz, and is supplied by the 125 kHz on-chip oscillator. It is used as the
clock source for the CPU and peripheral function clocks. In addition, when the CSPRO bit in the CSPR
register is 1 (count source protection mode enabled), this clock is used as the count source for the
watchdog timer (refer to 15.4.2 "Count Source Protection Mode Enabled").
After reset, fOCO-S divided by 8 becomes the CPU clock.
If the main clock stops oscillating, when the CM20 bit in the CM2 register is 1 (oscillator stop/restart
detect function enabled) and the CM27 bit is 1 (oscillator stop/restart detect interrupt), the 125 kHz on-
chip oscillator automatically starts operating and supplying the necessary clock for the MCU.
Follow the steps below to start or stop fOCO-S. Refer to 8.2 "Registers" for details on register and bit
access.
To start fOCO-S:
(1) Set the CM14 bit in the CM1 register to 0 (125 kHz on-chip oscillator on).
(2) Wait for tsu(fOCO-S).
To start fOCO-S:
(1) Set the CM14 bit in the CM1 register to 1 (125 kHz on-chip oscillator off).
When the CM21 bit is 1 (on-chip oscillator used as the clock source for the CPU), the CM14 bit
becomes 0 (125 kHz on-chip oscillator on).
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
Divided by n
n: 1, 2, 4 (selected by setting bits PLC05 and PLC04 in the PLC0 register)
m: 2, 4, 6, 8 (selected by setting bits PLC02 to PLC00 in the PLC0 register)
Notes:
1. Set the frequency divided by n to between 2 MHz and 5 MHz.
2. Set the PLL clock frequency to be within the f(PLL) range.
Setting Value
Bits PLC05 to PLC04
01b (divide-by-2)
00b (not divided)
10b (divide-by-4)
01b (divide-by-2)
Multiplied by m
(See Note 1)
Bits PLC02 to PLC00
010b (multiply-by-4)
010b (multiply-by-4)
100b (multiply-by-8)
100b (multiply-by-8)
8. Clock Generator
PLL clock
(See Note 2)
PLL Clock
20 MHz
24 MHz
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