Renesas 78K0/F 2 Series User Manual
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Renesas 78K0/F 2 Series User Manual

Renesas 78K0/F 2 Series User Manual

8-bit single-chip microcontrollers
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On April 1
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Summary of Contents for Renesas 78K0/F 2 Series

  • Page 1 On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding.
  • Page 2 Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as “Specific”...
  • Page 3 User’s Manual 78K0/Fx2 8-Bit Single-Chip Microcontrollers μ 78K0/FC2: PD78F0881A(A), 78F0882A(A), 78F0883A(A), 78F0884A(A), 78F0885A(A), 78F0886A(A), 78F0894A(A), 78F0895A(A), 78F0881A(A2), 78F0882A(A2), 78F0883A(A2), 78F0884A(A2), 78F0885A(A2), 78F0886A(A2) , 78F0894A(A2), 78F0895A(A2) μ 78K0/FE2: PD78F0887A(A), 78F0888A(A), 78F0889A(A), 78F0890A(A), 78F0887A(A2), 78F0888A(A2), 78F0889A(A2), 78F0890A(A2) μ 78K0/FF2: PD78F0891A(A), 78F0892A(A), 78F0893A(A), 78F0891A(A2), 78F0892A(A2), 78F0893A(A2) Document No.
  • Page 4 [MEMO] User’s Manual U19180EJ1V0UD...
  • Page 5 NOTES FOR CMOS DEVICES VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V (MAX) and V (MIN) due to noise, etc., the device may malfunction.
  • Page 6 EEPROM is a trademark of NEC Electronics Corporation. Windows is a registered trademark or trademark of Microsoft Corporation in the United States and/or other countries. SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States and Japan.
  • Page 7 ® Caution: This product uses SuperFlash technology licensed from Silicon Storage Technology, inc. • The information in this document is current as of March, 2009. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products.
  • Page 8 INTRODUCTION Readers This manual is intended for user engineers who wish to understand the functions of the μ expanded-specification products ( PD78F08xxA) of the 78K0/Fx2 microcontrollers and design and develop application systems and programs for these devices. The target products are as follows. •...
  • Page 9 Purpose This manual is intended to give users an understanding of the functions described in the Organization below. Organization The manual for the expanded-specification products of 78K0/Fx2 microcontrollers is separated into two parts: this manual and the instructions edition (common to the 78K0 microcontrollers).
  • Page 10 Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices Document Name Document No. 78K0/Fx2 User’s Manual This manual 78K/0 Series Instructions User’s Manual U12326E Documents Related to Development Tools (Hardware) (User’s Manuals) Document Name Document No.
  • Page 11 Documents Related to Development Tools (Software) (User’s Manuals) Document Name Document No. Note 1 RA78K0 Ver.3.80 Assembler Package Operation U17199E Language U17198E Structured Assembly Language U17197E Note 1 78K0 Assembler Package RA78K0 Ver.4.01 Operating Precautions ZUD-CD-07-0181-E Note 2 CC78K0 Ver.3.70 C Compiler Operation U17201E Language...

  • Page 12: Table Of Contents

    CONTENTS CHAPTER 1 OUTLINE ..........................19 μ 1.1 Differences Between Conventional-specification Products ( PD78F08xx) and Expanded- μ specification Products ( PD78F08xxA) ................... 19 1.1.1 A/D conversion time .......................... 20 1.1.2 Number of flash memory rewrites and retention time of (A) grade products and (A2) grade products ................................
  • Page 13 CHAPTER 3 CPU ARCHITECTURE...................... 72 3.1 Memory Space..........................72 3.1.1 Internal program memory space ......................80 μ 3.1.2 Memory bank ( PD78F0889A, 78F0890A, 78F0892A to 78F0895A only).........82 3.1.3 Internal data memory space.......................84 3.1.4 Special function register (SFR) area ....................84 3.1.5 Data memory addressing ........................85 3.2 Processor Registers ........................
  • Page 14 5.2.8 Port 8..............................155 5.2.9 Port 9..............................157 5.2.10 Port 12............................159 5.2.11 Port 13............................162 5.3 Registers Controlling Port Function ..................166 5.4 Port Function Operations ......................178 5.4.1 Writing to I/O port ..........................178 5.4.2 Reading from I/O port........................178 5.4.3 Operations on I/O port........................178 5.5 Settings of Port Mode Register and Output Latch When Using Alternate Function...
  • Page 15 7.5.2 Setting LVS0n and LVR0n .......................281 7.6 Cautions for 16-Bit Timer/Event Counters 00 to 03..............283 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 ............288 8.1 Functions of 8-Bit Timer/Event Counters 50 and 51............... 288 8.2 Configuration of 8-Bit Timer/Event Counters 50 and 51 ............290 8.3 Registers Controlling 8-Bit Timer/Event Counters 50 and 51 ..........
  • Page 16 CHAPTER 13 A/D CONVERTER ......................353 13.1 Function of A/D Converter....................... 353 13.2 Configuration of A/D Converter ....................354 13.3 Registers Used in A/D Converter.................... 356 13.4 A/D Converter Operations ....................... 366 13.4.1 Basic operations of A/D converter ....................366 13.4.2 Input voltage and conversion results ....................368 13.4.3 A/D converter operation mode......................370 13.5 How to Read A/D Converter Characteristics Table...............
  • Page 17 16.5 Internal Registers of CAN Controller ..................480 16.5.1 CAN controller configuration ......................480 16.5.2 Register access type........................481 16.5.3 Register bit configuration .......................490 16.6 Bit Set/Clear Function......................494 16.7 Control Registers ........................496 16.8 CAN Controller Initialization ....................531 16.8.1 Initialization of CAN module ......................531 16.8.2 Initialization of message buffer.......................531 16.8.3 Redefinition of message buffer ......................531 16.8.4 Transition from initialization mode to operation mode ..............532...
  • Page 18 17.4.2 Software interrupt request acknowledgement ................612 17.4.3 Multiple interrupt servicing......................613 17.4.4 Interrupt request hold ........................616 CHAPTER 18 STANDBY FUNCTION ....................617 18.1 Standby Function and Configuration ..................617 18.1.1 Standby function..........................617 18.1.2 Registers controlling standby function....................617 18.2 Standby Function Operation ....................620 18.2.1 HALT mode ............................620 18.2.2 STOP mode............................625 CHAPTER 19 RESET FUNCTION......................
  • Page 19 24.6 Connection of Pins on Board....................695 24.6.1 FLMD0 pin .............................695 24.6.2 Serial interface pins........................695 24.6.3 RESET pin .............................697 24.6.4 Port pins............................697 24.6.5 REGC pin ............................697 24.6.6 Other signal pins ..........................697 24.6.7 Power supply..........................698 24.7 Programming Method ......................699 24.7.1 Controlling flash memory .......................699 24.7.2 Flash memory programming mode ....................699 24.7.3 Selecting communication mode .....................700 24.7.4 Communication commands......................701...
  • Page 20 28.5 Data Retention Characteristics ....................786 28.6 Flash EEPROM Programming Characteristics..............787 CHAPTER 29 PACKAGE DRAWINGS ....................788 29.1 78K0/FC2 ........................... 788 29.2 78K0/FE2 ........................... 790 29.3 78K0/FF2............................ 792 CHAPTER 30 RECOMMENDED SOLDERING CONDITIONS............794 CHAPTER 31 CAUTIONS FOR WAIT....................795 31.1 Cautions for Wait........................

  • Page 21: Chapter 1 Outline

    CHAPTER 1 OUTLINE μ 1.1 Differences Between Conventional-specification Products ( PD78F08xx) and Expanded- μ specification Products ( PD78F08xxA) μ This manual describes the functions of the expanded-specification products ( PD78F08xxA) of the 78K0/Fx2 microcontrollers. μ The differences between the conventional-specification products ( PD78F08xx) and expanded-specification μ...

  • Page 22: A/D Conversion Time

    CHAPTER 1 OUTLINE 1.1.1 A/D conversion time The conversion time of A/D converter is as follows. μ (1) Conventional-specification products ( PD78F08xx) Parameter Symbol Conditions MIN. MAX. Unit μ 4.0 V ≤ AV ≤ 5.5 V Conversion 36.7 CONW time 2.7 V ≤...

  • Page 23: Processing Time For Self Programming Library

    CHAPTER 1 OUTLINE 1.1.3 Processing time for self programming library μ (1) Conventional-specification products ( PD78F08xx) (1/3) <1> When internal high-speed oscillation clock is used and entry RAM is located outside short direct addressing range μ Library Name Processing Time ( Normal Model of C Compiler Static Model of C Compiler/Assembler Min.
  • Page 24 CHAPTER 1 OUTLINE μ (1) Conventional-specification products ( PD78F08xx) (2/3) <3> When high-speed system clock (X1 oscillation or external clock input) is used and entry RAM is located outside short direct addressing range μ Library Name Processing Time ( Normal Model of C Compiler Static Model of C Compiler/Assembler Min.
  • Page 25 CHAPTER 1 OUTLINE μ (1) Conventional-specification products ( PD78F08xx) (3/3) <4> When high-speed system clock (X1 oscillation or external clock input) is used and entry RAM is located in short direct addressing range μ Library Name Processing Time ( Normal Model of C Compiler Static Model of C Compiler/Assembler Min.
  • Page 26 CHAPTER 1 OUTLINE μ (2) Expanded-specification products ( PD78F08xxA) (1/3) <1> When internal high-speed oscillation clock is used and entry RAM is located outside short direct addressing range μ Library Name Processing Time ( Normal Model of C Compiler Static Model of C Compiler/Assembler Min.
  • Page 27 CHAPTER 1 OUTLINE μ (2) Expanded-specification products ( PD78F08xxA) (2/3) <3> When high-speed system clock (X1 oscillation or external clock input) is used and entry RAM is located outside short direct addressing range μ Library Name Processing Time ( Normal Model of C Compiler Static Model of C Compiler/Assembler Min.
  • Page 28 CHAPTER 1 OUTLINE μ (2) Expanded-specification products ( PD78F08xxA) (3/3) <4> When high-speed system clock (X1 oscillation or external clock input) is used and entry RAM is located in short direct addressing range μ Library Name Processing Time ( Normal Model of C Compiler Static Model of C Compiler/Assembler Min.

  • Page 29: Interrupt Response Time For Self Programming Library

    CHAPTER 1 OUTLINE 1.1.4 Interrupt response time for self programming library μ (1) Conventional-specification products ( PD78F08xx) (1/2) <1> When internal high-speed oscillation clock is used μ Library Name Interrupt Response Time ( s (Max.)) Normal Model of C Compiler Static Model of C Compiler/Assembler Entry RAM location Entry RAM location...
  • Page 30 CHAPTER 1 OUTLINE μ (1) Conventional-specification products ( PD78F08xx) (2/2) <3> When high-speed system clock is used (static model of C compiler/assembler) μ Library Name Interrupt Response Time ( s (Max.)) RSTOP = 0, RSTS = 1 RSTOP = 1 Entry RAM location Entry RAM location Entry RAM location...
  • Page 31 CHAPTER 1 OUTLINE μ (2) Expanded-specification products ( PD78F08xxA) (1/2) <1> When internal high-speed oscillation clock is used μ Library Name Interrupt Response Time ( s (Max.)) Normal Model of C Compiler Static Model of C Compiler/Assembler Entry RAM location Entry RAM location Entry RAM location Entry RAM location...
  • Page 32 CHAPTER 1 OUTLINE μ (2) Expanded-specification products ( PD78F08xxA) (2/2) <3> When high-speed system clock is used (static model of C compiler/assembler) μ Library Name Interrupt Response Time ( s (Max.)) RSTOP = 0, RSTS = 1 RSTOP = 1 Entry RAM location Entry RAM location Entry RAM location...

  • Page 33: Features

    CHAPTER 1 OUTLINE 1.2 Features μ Minimum instruction execution time can be changed from high speed (0.1 s: @ 20 MHz operation with high- μ speed system clock) to ultra low-speed (122 s: @ 32.768 kHz operation with subsystem clock) General-purpose register: 8 bits ×...

  • Page 34: Applications

    CHAPTER 1 OUTLINE 1.3 Applications Automotive electrical appliances (Body control, Door control, Front light control) Industrial equipment (Industrial robot, Building control) 1.4 Ordering Information [Part Number] μ PD78F08xy A XX X - XXX - G Semiconductor Lead- Product contains no lead in any area free (Terminal finish is Ni/Pd/Au plating) Quality Grade...
  • Page 35 CHAPTER 1 OUTLINE [List of Part Number] 78K0/Fx2 Package Part Number Microcontrollers μ 78K0/FC2 44-pin plastic LQFP PD78F0881AGBA-GAF-G, 78F0882AGBA-GAF-G, 78F0883AGBA-GAF-G, (10x10) 78F0881AGBA2-GAF-G, 78F0882AGBA2-GAF-G, 78F0883AGBA2-GAF-G μ 48-pin plastic LQFP PD78F0884AGAA-GAM-G, 78F0885AGAA-GAM-G, 78F0886AGAA-GAM-G, (fine pitch) (7x7) 78F0894AGAA-GAM-G, 78F0895AGAA-GAM-G, 78F0884AGAA2-GAM-G, 78F0885AGAA2-GAM-G, 78F0886AGAA2-GAM-G, 78F0894AGAA2-GAM-G, 78F0895AGAA2-GAM-G μ...

  • Page 36: Pin Configuration (Top View)

    CHAPTER 1 OUTLINE 1.5 Pin Configuration (Top View) 1.5.1 78K0/FC2 • 44-pin plastic LQFP (10x10) 44 43 42 41 40 39 38 37 36 35 34 RESET P10/SCK10/TxD61 P124/XT2/EXCLKS P11/SI10/RxD61 P123/XT1 P12/SO10 FLMD0 P13/TxD60 P122/X2/EXCLK P14/RxD60 P121/X1 P15/TOH0 REGC P16/TOH1/INTP5 P17/TI50/TO50 P30/INTP1 12 13 14 15 16 17 18 19 20 21 22...
  • Page 37 CHAPTER 1 OUTLINE • 48-pin plastic LQFP (Fine pitch) (7x7) 48 47 46 45 44 43 42 41 40 39 38 37 P120/INTP0/EXLVI P10/SCK10/TxD61 RESET P11/SI10/RxD61 P124/XT2/EXCLKS P12/SO10 P123/XT1 P13/TxD60 FLMD0 P14/RxD60 P122/X2/EXCLK P15/TOH0 P121/X1 P16/TOH1/INTP5 REGC P17/TI50/TO50 P30/INTP1 P31/INTP2 13 14 15 16 17 18 19 20 21 22 23 24 Cautions 1.

  • Page 38: 78K0/Fe2

    CHAPTER 1 OUTLINE 1.5.2 78K0/FE2 • 64-pin plastic LQFP (12x12) • 64-pin plastic LQFP (Fine pitch) (10x10) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 P120/INTP0/EXLVI P10/SCK10/TxD61 P11/SI10/RxD61 P12/SO10 RESET P13/TxD60 P124/XT2/EXCLKS P14/RxD60 P123/XT1 P15/TOH0...

  • Page 39: 78K0/Ff2

    CHAPTER 1 OUTLINE 1.5.3 78K0/FF2 • 80-pin plastic LQFP (14x14) • 80-pin plastic LQFP (Fine pitch) (12x12) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 P120/INTP0/EXLVI P10/SCK10/TxD61 P11/SI10/RxD61 P12/SO10 RESET P13/TxD60...

  • Page 40: Pin Identification

    CHAPTER 1 OUTLINE 1.6 Pin Identification ANI0 to ANI15: Analog Input P90 to P97: Port 9 Analog Reference Voltage P120 to P124: Port 12 Analog Ground P130 to P132: Port 13 BUZ: Buzzer Output PCL: Programmable Clock Output CRxD: Receive Data for CAN REGC: Regulator Capacitance CTxD:...

  • Page 41: Block Diagram

    CHAPTER 1 OUTLINE 1.7 Block Diagram 1.7.1 78K0/FC2 • μ PD78F0881A, 78F0882A, 78F0883A TO00/TI010/P01 16-bit timer/ Port 0 P00, P01 event counter 00 TI000/P00 (LINSEL) RxD60/P14 (LINSEL) Port 1 P10-P17 16-bit timer/ event counter 01 Port 3 P30-P33 TOH0/P15 8-bit timer H0 Port 4 P40, P41 Port 6...
  • Page 42 CHAPTER 1 OUTLINE μ • PD78F0884A, 78F0885A, 78F0886A, 78F0894A, 78F0895A TO00/TI010/P01 16-bit timer/ Port 0 P00, P01, P06 event counter 00 TI000/P00 (LINSEL) RxD60/P14 (LINSEL) Port 1 P10-P17 16-bit timer/ TO01/TI011/P06 event counter 01 Port 3 P30-P33 TOH0/P15 8-bit timer H0 Port 4 P40, P41 Port 6...

  • Page 43: 78K0/Fe2

    CHAPTER 1 OUTLINE 1.7.2 78K0/FE2 TO00/TI010/P01 16-bit timer/ Port 0 P00, P01, P05, P06 event counter 00 TI000/P00 (LINSEL) RxD60/P14 (LINSEL) Port 1 P10-P17 TO01/TI011/P06 16-bit timer/ event counter 01 TI001/P05 Port 3 P30-P33 TO02/TI012/P32 16-bit timer/ event counter 02 TI002/P31 Port 4 P40-P43...

  • Page 44: 78K0/Ff2

    CHAPTER 1 OUTLINE 1.7.3 78K0/FF2 TO00/TI010/P01 16-bit timer/ Port 0 P00.P01,P05, P06 event counter 00 TI000/P00 (LINSEL) RxD60/P14 (LINSEL) Port 1 P10 to P17 TO01/TI011/P06 16-bit timer/ event counter 01 TI001/P05 Port 3 P30 to P33 TO02/TI012/P32 16-bit timer/ event counter 02 Port 4 TI002/P31 P40 to P47...

  • Page 45: Outline Of Functions

    CHAPTER 1 OUTLINE 1.8 Outline of Functions (1/2) 78K0/Fx2 78K0/FC2 μ PD78F088yA, 78F0894A, 78F0895A: y = 1 to 6) 44 Pins 48 Pins Item Note 1 Flash memory (KB) High-Speed RAM (KB) Expansion RAM (KB) − Bank (flash memory) Power supply voltage (A) grade products: V = 1.8 to 5.5 V, (A2) grade products: V = 2.7 to 5.5 V...
  • Page 46 CHAPTER 1 OUTLINE (2/2) 78K0/Fx2 78K0/FE2 78K0/FF2 μ μ PD78F088yA, 78F0890A: y = 7 to 9) PD78F089yA: y = 1 to 3) 64 Pins 80 Pins Item Note 1 Flash memory (KB) High-Speed RAM (KB) Expansion RAM (KB) − − Bank (flash memory) Power supply voltage (A) grade products: V...
  • Page 47 CHAPTER 1 OUTLINE An outline of the timer is shown below. 16-Bit Timer/ 8-Bit Timer/ 8-Bit Timers H0 Watch Timer Watchdog Event Counters 00 to 03 Event Counters and H1 Timer 50 and 51 TM00 TM01 TM02 TM03 TM50 TM51 TMH0 TMH1 Note...

  • Page 48: Chapter 2 Pin Functions

    CHAPTER 2 PIN FUNCTIONS 2.1 Pin Function List Pin I/O buffer power supplies depend on the product. The relationship between these power supplies and the pins is shown below. Table 2-1. Pin I/O Buffer Power Supplies (AV , EV • 78K0/FC2: 44-pin plastic LQFP (10x10), 48-pin plastic LQFP (fine pitch) (7x7) Power Supply Corresponding Pins Note...

  • Page 49: 78K0/Fc2

    CHAPTER 2 PIN FUNCTIONS 2.1.1 78K0/FC2 (1) Port pins: 78K0/FC2 Table 2-3. Port pins: 78K0/FC2 (1/2) Pin Name Function After Reset Alternate Function Port 0. Input TI000 3-bit I/O port. TI010/TO00 Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a Note TI011/TO01 software setting.
  • Page 50 CHAPTER 2 PIN FUNCTIONS Table 2-3. Port pins: 78K0/FC2 (2/2) Pin Name Function After Reset Alternate Function P120 Port 12. Input INTP0/EXLVI 5-bit I/O port. P121 Only for P120, use of an on-chip pull-up resistor can be P122 X2/EXCLK specified by a software setting. P123 P124 XT2/EXCLKS...
  • Page 51 CHAPTER 2 PIN FUNCTIONS Table 2-4. Non-port pins: 78K0/FC2 (2/2) Pin Name Function After Reset Alternate Function TO50 Output 8-bit timer/event counter 50 output Input P17/TI50 TO51 8-bit timer/event counter 51 output P33/TI51/INTP4 TOH0 Output 8-bit timer H0 output Input TOH1 8-bit timer H1 output P16/INTP5...

  • Page 52: 78K0/Fe2

    CHAPTER 2 PIN FUNCTIONS 2.1.2 78K0/FE2 (1) Port pins: 78K0/FE2 Table 2-5. Port pins: 78K0/FE2 (1/2) Pin Name Function After Reset Alternate Function Port 0. Input TI000 4-bit I/O port. TI010/TO00 Input/output can be specified in 1-bit units. SSI11/TI001 Use of an on-chip pull-up resistor can be specified by a TI011/TO01 software setting.
  • Page 53 CHAPTER 2 PIN FUNCTIONS Table 2-5. Port pins: 78K0/FE2 (2/2) Pin Name Function After Reset Alternate Function P90 to P93 Port 9. Input ANI8 to ANI11 4-bit I/O port. Input/output can be specified in 1-bit units. Port 12. P120 Input INTP0/EXLVI 5-bit I/O port.
  • Page 54 CHAPTER 2 PIN FUNCTIONS Table 2-6. Non-port pins: 78K0/FE2 (2/3) Pin Name Function After Reset Alternate Function TI001 Input External count clock input to 16-bit timer/event counter 01 Input P05/SSI11 Capture trigger input to capture registers (CR001, CR011) of 16-bit timer/event counter 01 External count clock input to 16-bit timer/event counter 02 TI002 P31/INTP2...

  • Page 55: 78K0/Ff2

    CHAPTER 2 PIN FUNCTIONS Table 2-6. Non-port pins: 78K0/FE2 (3/3) Pin Name Function After Reset Alternate Function EXCLK Input External clock input for main system clock Input P122/X2 EXCLKS Input External clock input for subsystem clock Input P124/XT2 EXLVI Input Potential input for external low-voltage detection Input P120/INTP0...
  • Page 56 CHAPTER 2 PIN FUNCTIONS Table 2-7. Port pins: 78K0/FF2 (2/2) Pin Name Function After Reset Alternate Function − P60 to P63 Port 6. N-ch open drain I/O port. Input 8-bit I/O port P64 to P67 Use of an on-chip pull-up resister Input/output can be can be specified by a software specified in 1-bit units.
  • Page 57 CHAPTER 2 PIN FUNCTIONS Table 2-8. Non-port pins: 78K0/FF2 (2/3) Pin Name Function After Reset Alternate Function SO10 Output Serial data output from serial interface Input SO11 SCK10 Clock input/output for serial interface Input P10/TxD61 SCK11 SSI11 Input Serial interface chip select input Input P05/TI001 RxD60...
  • Page 58 CHAPTER 2 PIN FUNCTIONS Table 2-8. Non-port pins: 78K0/FF2 (3/3) Pin Name Function After Reset Alternate Function CTxD Input CAN transmit data output Input CRxD Output CAN receive data input Input − − Input A/D converter reference voltage input and positive power supply for port 2 −...

  • Page 59: Description Of Pin Functions

    CHAPTER 2 PIN FUNCTIONS 2.2 Description of Pin Functions Remark The pins mounted depend on the product. See 1.4 Ordering Information and 2.1 Pin Function List. 2.2.1 P00, P01, P05, P06 (port 0) P00, P01, P05 and P06 function as a 4-bit I/O port. These pins also function as timer I/O and serial interface chip select input.

  • Page 60: P10 To P17 (Port 1)

    CHAPTER 2 PIN FUNCTIONS 2.2.2 P10 to P17 (port 1) P10 to P17 function as an 8-bit I/O port. These pins also function as pins for external interrupt request input, serial interface data I/O, clock I/O, and timer I/O. 78K0/FC2 78K0/FE2 78K0/FF2 μ...

  • Page 61: P30 To P33 (Port 3)

    CHAPTER 2 PIN FUNCTIONS (h) INTP5 This is an external interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. 2.2.3 P30 to P33 (port 3) P30 to P33 function as a 4-bit I/O port. These pins also function as pins for external interrupt request input and timer I/O.

  • Page 62: P40 To P47 (Port 4)

    CHAPTER 2 PIN FUNCTIONS (e) TI51 This is an external count clock input pin to 8-bit timer/event counter 51. (f) TO51 This is a timer output pin. Cautions 1. Be sure to pull the P31/TI002/INTP2 pin down before a reset release, to prevent malfunction. 2.

  • Page 63: P50 To P57 (Port 5)

    CHAPTER 2 PIN FUNCTIONS 2.2.5 P50 to P57 (port 5) P50 to P57 function as a 8-bit I/O port. P50 to P57 can be set to input or output in 1-bit units using port mode register 5 (PM5). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 5 (PU5). 78K0/FC2 78K0/FE2 78K0/FF2...

  • Page 64: P70 To P76 (Port 7)

    CHAPTER 2 PIN FUNCTIONS 2.2.7 P70 to P76 (port 7) P70 to P76 function as a 7-bit I/O port. These pins also function as external interrupt request input, clock output pins, buzzer output pins, CAN I/F I/O, serial interface data I/O and clock I/O. 78K0/FC2 78K0/FE2 78K0/FF2...

  • Page 65: P80 To P87 (Port 8)

    CHAPTER 2 PIN FUNCTIONS (g) SO11 This is a serial interface serial data output pin. (h) SCK11 This is the serial interface serial clock I/O pin. 2.2.8 P80 to P87 (port 8) P80 to P87 function as an 8-bit I/O port. These pins also function as pins for A/D converter analog input. 78K0/FC2 78K0/FE2 78K0/FF2...

  • Page 66: P90 To P97 (Port 9)

    CHAPTER 2 PIN FUNCTIONS 2.2.9 P90 to P97 (port 9) P90 to P97 function as an 8-bit I/O port. These pins also function as pins for A/D converter analog input. 78K0/FC2 78K0/FE2 78K0/FF2 μ μ μ PD78F088yA, 78F089zA) PD78F088yA, 78F0890A) PD78F089yA) y = 1 to 3 y = 4 to 6, z = 4, 5...
  • Page 67 CHAPTER 2 PIN FUNCTIONS The following operation modes can be specified in 1-bit units. Port mode P120 to P124 function as a 5-bit I/O port. P120 to P124 can be set to input or output using port mode register 12 (PM12).

  • Page 68: P130 To P132 (Port 13)

    CHAPTER 2 PIN FUNCTIONS 2.2.11 P130 to P132 (port 13) P130 functions as a 1-bit output-only port. P131 and P132 function as a 2-bit I/O port. These pins also function as pins for timer I/O. 78K0/FC2 78K0/FE2 78K0/FF2 μ μ μ...

  • Page 69: Reset

    CHAPTER 2 PIN FUNCTIONS (a) AV This is the A/D converter reference voltage input pin. Note When the A/D converter is not used, connect this pin directly to EV or V Note Connect port 8 and port 9 directly to EV when it is used as a digital port.

  • Page 70: Pin I/O Circuits And Recommended Connection Of Unused Pins

    CHAPTER 2 PIN FUNCTIONS 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins Table 2-9 shows the types of pin I/O circuits and the recommended connections of unused pins. Refer to Figure 2-1 for the configuration of the I/O circuit of each type. Remark The pins mounted depend on the product.
  • Page 71 CHAPTER 2 PIN FUNCTIONS Table 2-9. Pin I/O Circuit Types (2/2) Pin Name I/O Circuit Recommended Connection of Unused Pins Type P70/CTxD Note 1 P71/CRxD 5-AH P72/PCL/INTP6 P73/BUZ/INTP7 P74/SO11 5-AG P75/SI11 5-AH P76/SCK11 Note 2 P80/ANI0 to P87/ANI7 11-G <Analog setting> Note 2 P90/ANI8 to P97/ANI15 Connect to AV...
  • Page 72 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List (1/2) Type 2 Type 5-AH Pullup P-ch enable Data P-ch IN/OUT Schmitt-triggered input with hysteresis characteristics Output N-ch disable Input enable Type 5-H Type 3-C Pullup P-ch enable P-ch Output Data P-ch data...
  • Page 73 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List (2/2) Type 13-P Type 37 Reset Data P-ch IN/OUT Output N-ch Data disable N-ch Output disable EVss Input enable Reset Data P-ch input enable Output N-ch disable Input enable User’s Manual U19180EJ1V0UD...

  • Page 74: Chapter 3 Cpu Architecture

    CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space Products in the 78K0/Fx2 microcontrollers can each access a 64 KB memory space. Figures 3-1 to 3-5 show the memory map. Cautions 1. Regardless of the internal memory capacity, the initial values of the internal memory size switching register (IMS) and internal expansion RAM size switching register (IXS) of all products in the 78K0/Fx2 microcontrollers are fixed (IMS = CFH, IXS = 0CH).
  • Page 75 CHAPTER 3 CPU ARCHITECTURE μ Figure 3-1. Memory Map ( PD78F0881A, 78F0884A) FFFFH Special function registers (SFR) FF20H 256 × 8 bits FF1FH FF00H FEFFH General-purpose registers Short direct 32 × 8 bits FEE0H addressing FEDFH Internal high-speed RAM 7 F F F H 1024 ×...
  • Page 76 CHAPTER 3 CPU ARCHITECTURE μ Figure 3-2. Memory Map ( PD78F0882A, 78F0885A, 78F0887A) FFFFH Special function registers (SFR) FF20H 256 × 8 bits FF1FH FF00H FEFFH General-purpose registers Short direct 32 × 8 bits FEE0H addressing FEDFH Internal high-speed RAM B F F F H 1024 ×...
  • Page 77 CHAPTER 3 CPU ARCHITECTURE μ Figure 3-3. Memory Map ( PD78F0883A, 78F0886A, 78F0888A, 78F0891A) FFFFH Special function registers (SFR) FF20H 256 × 8 bits FF1FH FF00H FEFFH General-purpose registers Short direct 32 × 8 bits FEE0H addressing FEDFH Internal high-speed RAM E F F F H 1024 ×...
  • Page 78 CHAPTER 3 CPU ARCHITECTURE μ Figure 3-4. Memory Map ( PD78F0889A, 78F0892A, 78F0894A) FFFFH Special function registers (SFR) FF20H 256 × 8 bits FF1FH FF00H FEFFH General-purpose registers Short direct 32 × 8 bits FEE0H addressing FEDFH Internal high-speed RAM 1024 ×...
  • Page 79 CHAPTER 3 CPU ARCHITECTURE μ Figure 3-5. Memory Map ( PD78F0890A, 78F0893A, 78F0895A) FFFFH Special function registers (SFR) FF20H 256 × 8 bits FF1FH FF00H FEFFH General-purpose registers Short direct FEE0H 32 × 8 bits addressing FEDFH Internal high-speed RAM 1024 ×...
  • Page 80 CHAPTER 3 CPU ARCHITECTURE Correspondence between the address values and block numbers in the flash memory are shown below. Table 3-2. Correspondence Between Address Values and Block Numbers in Flash Memory (1/2) μ PD78F088xA (x = 1 to 8), 78F0891A Block Block Block...
  • Page 81 CHAPTER 3 CPU ARCHITECTURE Table 3-2. Correspondence Between Address Values and Block Numbers in Flash Memory (2/2) μ PD78F0889A, 78F089xA (x = 0, 2 to 5) Address Value Block Address Value Block Address Value Block Address Value Block Number Number Number Number 0000H to 03FFH...

  • Page 82: Internal Program Memory Space

    CHAPTER 3 CPU ARCHITECTURE 3.1.1 Internal program memory space The internal program memory space stores the program and table data. Normally, it is addressed with the program counter (PC). 78K0/Fx2 microcontrollers incorporate internal ROM (flash memory), as shown below. Table 3-3. Internal ROM Capacity 78K0/FC2 78K0/FE2 78K0/FF2...
  • Page 83 CHAPTER 3 CPU ARCHITECTURE Table 3-4. Vector Code Vector Code Address Interrupt Source √ √ √ 0000H RESET input, POC, LVI, WDT √ √ √ 0004H INTLVI √ √ √ 0006H INTP0 √ √ √ 0008H INTP1 √ √ Note 1 000AH INTP2/INTTM002 INTP2...

  • Page 84: Memory Bank ( Μ Pd78F0889A, 78F0890A, 78F0892A To 78F0895A Only)

    CHAPTER 3 CPU ARCHITECTURE (2) CALLT instruction table area The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT). (3) Option byte area The option byte area is assigned to the 1-byte area of 0080H. Refer to CHAPTER 23 OPTION BYTE for details.
  • Page 85 CHAPTER 3 CPU ARCHITECTURE μ PD78F0890A, 78F0893A, 78F0895A B F F F H Bank Bank Bank Bank Bank Bank area 0 area 1 area 2 area 3 area 4 area 5 16384 × 16384 × 16384 × 16384 × 16384 × 16384 ×...

  • Page 86: Internal Data Memory Space

    CHAPTER 3 CPU ARCHITECTURE 3.1.3 Internal data memory space 78K0/Fx2 microcontrollers incorporate the following RAM. (1) Internal high-speed RAM Table 3-6. Internal High-Speed RAM Capacity 78K0/FC2 78K0/FE2 78K0/FF2 Internal high-speed RAM 44 Pins 48 Pins Capacity μ μ 1024 × 8 bits (FB00H to FEFFH) −...

  • Page 87: Data Memory Addressing

    CHAPTER 3 CPU ARCHITECTURE 3.1.5 Data memory addressing Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the 78K0/Fx2 micro controllers, based on operability and other considerations.
  • Page 88 CHAPTER 3 CPU ARCHITECTURE μ Figure 3-7. Correspondence Between Data Memory and Addressing ( PD78F0881A, 78F0884A) FFFFH Special function registers (SFR) SFR addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH General-purpose registers Register addressing Short direct 32 × 8 bits addressing FEE0H FEDFH...
  • Page 89 CHAPTER 3 CPU ARCHITECTURE μ Figure 3-8. Correspondence Between Data Memory and Addressing ( PD78F0882A, 78F0885A, 78F0887A) FFFFH Special function registers (SFR) SFR addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH General-purpose registers Register addressing 32 × 8 bits Short direct FEE0H addressing...
  • Page 90 CHAPTER 3 CPU ARCHITECTURE Figure 3-9. Correspondence Between Data Memory and Addressing μ PD78F0883A, 78F0886A, 78F0888A, 78F0891A) FFFFH Special function registers (SFR) SFR addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH General-purpose registers Register addressing 32 × 8 bits Short direct FEE0H addressing...
  • Page 91 CHAPTER 3 CPU ARCHITECTURE μ Figure 3-10. Correspondence Between Data Memory and Addressing ( PD78F0889A, 78F0892A, 78F0894A) FFFFH Special function registers (SFR) SFR addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH General-purpose registers Register addressing 32 × 8 bits Short direct FEE0H addressing...
  • Page 92 CHAPTER 3 CPU ARCHITECTURE μ Figure 3-11. Correspondence Between Data Memory and Addressing ( PD78F0890A, 78F0893A, 78F0895A) FFFFH Special function registers (SFR) SFR addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH General-purpose registers Register addressing 32 × 8 bits Short direct FEE0H addressing...

  • Page 93: Processor Registers

    CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers 78K0/Fx2 microcontrollers incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a stack pointer (SP). (1) Program counter (PC) The program counter is a 16-bit register that holds the address information of the next program to be executed.
  • Page 94 CHAPTER 3 CPU ARCHITECTURE (c) Register bank select flags (RBS0 and RBS1) These are 2-bit flags to select one of the four register banks. In these flags, the 2-bit information that indicates the register bank selected by SEL RBn instruction execution is stored.
  • Page 95 CHAPTER 3 CPU ARCHITECTURE Figure 3-15. Data to Be Saved to Stack Memory (a) PUSH rp instruction (when SP = FEE0H) FEE0H FEE0H FEDFH Register pair higher FEDEH Register pair lower FEDEH (b) CALL, CALLF, CALLT instructions (when SP = FEE0H) FEE0H FEE0H FEDFH...
  • Page 96 CHAPTER 3 CPU ARCHITECTURE Figure 3-16. Data to Be Restored from Stack Memory (a) POP rp instruction (when SP = FEDEH) FEE0H FEE0H FEDFH Register pair higher FEDEH Register pair lower FEDEH (b) RET instruction (when SP = FEDEH) FEE0H FEE0H FEDFH PC15 to PC8...

  • Page 97: General-Purpose Registers

    CHAPTER 3 CPU ARCHITECTURE 3.2.2 General-purpose registers General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. The general-purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register (AX, BC, DE, and HL).

  • Page 98: Special Function Registers (Sfrs)

    CHAPTER 3 CPU ARCHITECTURE 3.2.3 Special Function Registers (SFRs) Unlike a general-purpose register, each special function register has a special function. SFRs are allocated to the FF00H to FFFFH area. Special function registers can be manipulated like general-purpose registers, using operation, transfer and bit manipulation instructions.
  • Page 99 CHAPTER 3 CPU ARCHITECTURE Table 3-8. Special Function Register List (1/6) Address Special Function Register (SFR) Name Symbol Manipulatable Bit Unit After Reset 1 Bit 8 Bits 16 Bits √ √ − √ √ √ FF00H Port register 0 √ √...
  • Page 100 CHAPTER 3 CPU ARCHITECTURE Table 3-8. Special Function Register List (2/6) Address Special Function Register (SFR) Name Symbol Manipulatable Bit Unit After Reset 1 Bit 8 Bits 16 Bits √ √ − √ √ √ FF2AH A/D converter mode register √...
  • Page 101 CHAPTER 3 CPU ARCHITECTURE Table 3-8. Special Function Register List (3/6) Address Special Function Register (SFR) Name Symbol Manipulatable Bit Unit After Reset 1 Bit 8 Bits 16 Bits √ √ − √ √ √ FF4FH Input switch control register √...
  • Page 102 CHAPTER 3 CPU ARCHITECTURE Table 3-8. Special Function Register List (4/6) Address Special Function Register (SFR) Name Symbol Manipulatable Bit Unit After Reset 1 Bit 8 Bits 16 Bits − − √ √ √ √ FF76H CAN Module Mask 2 Register H C0MASK2H Undefined FF77H...
  • Page 103 CHAPTER 3 CPU ARCHITECTURE Tables 3-8. Special Function Register List (5/6) Address Special Function Register (SFR) Name Symbol Manipulatable Bit Unit After Reset 1 Bit 8 Bits 16 Bits √ √ − √ √ √ FFA3H Oscillation stabilization time counter status OSTC register √...
  • Page 104 CHAPTER 3 CPU ARCHITECTURE Tables 3-8. Special Function Register List (6/6) Address Special Function Register (SFR) Name Symbol Manipulatable Bit Unit After Reset 1 Bit 8 Bits 16 Bits √ √ √ √ √ √ FFE4H Interrupt mask flag register 0L MK0L R/W √...

  • Page 105: Instruction Address Addressing

    CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing An instruction address is determined by program counter (PC) contents and is normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed.

  • Page 106: Immediate Addressing

    CHAPTER 3 CPU ARCHITECTURE 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. CALL !addr16 and BR !addr16 instructions can be branched to the entire memory space.
  • Page 107 CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (PC) and branched. This function is carried out when the CALLT [addr5] instruction is executed.

  • Page 108: Register Addressing

    CHAPTER 3 CPU ARCHITECTURE 3.3.4 Register addressing [Function] Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the BR AX instruction is executed. [Illustration] User’s Manual U19180EJ1V0UD...

  • Page 109: Operand Address Addressing

    CHAPTER 3 CPU ARCHITECTURE 3.4 Operand Address Addressing The following methods are available to specify the register and memory (addressing) to undergo manipulation during instruction execution. 3.4.1 Implied addressing [Function] The register that functions as an accumulator (A and AX) among the general-purpose registers is automatically (implicitly) addressed.

  • Page 110: Register Addressing

    CHAPTER 3 CPU ARCHITECTURE 3.4.2 Register addressing [Function] The general-purpose register to be specified is accessed as an operand with the register bank select flags (RBS0 to RBS1) and the register specify codes (Rn and RPn) of an operation code. Register addressing is carried out when an instruction with the following operand format is executed.

  • Page 111: Direct Addressing

    CHAPTER 3 CPU ARCHITECTURE 3.4.3 Direct addressing [Function] The memory to be manipulated is directly addressed with immediate data in an instruction word becoming an operand address. [Operand format] Identifier Description addr16 Label or 16-bit immediate data [Description example] MOV A, !0FE00H; when setting !addr16 to FE00H Operation code OP code [Illustration]...

  • Page 112: Short Direct Addressing

    CHAPTER 3 CPU ARCHITECTURE 3.4.4 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. This addressing is applied to the 256-byte space FE20H to FF1FH. Internal RAM and special function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.

  • Page 113: Special Function Register (Sfr) Addressing

    CHAPTER 3 CPU ARCHITECTURE 3.4.5 Special function register (SFR) addressing [Function] A memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFRs mapped at FF00H to FF1FH can be accessed with short direct addressing.

  • Page 114: Register Indirect Addressing

    CHAPTER 3 CPU ARCHITECTURE 3.4.6 Register indirect addressing [Function] Register pair contents specified by a register pair specify code in an instruction word and by a register bank select flag (RBS0 and RBS1) serve as an operand address for addressing the memory. This addressing can be carried out for all the memory spaces.

  • Page 115: Based Addressing

    CHAPTER 3 CPU ARCHITECTURE 3.4.7 Based addressing [Function] 8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address the memory.

  • Page 116: Based Indexed Addressing

    CHAPTER 3 CPU ARCHITECTURE 3.4.8 Based indexed addressing [Function] The B or C register contents specified in an instruction word are added to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address the memory.

  • Page 117: Stack Addressing

    CHAPTER 3 CPU ARCHITECTURE 3.4.9 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call and return instructions are executed or the register is saved/reset upon generation of an interrupt request. With stack addressing, only the internal high-speed RAM area can be accessed.

  • Page 118: Chapter 4 Memory Bank Select Function ( 78F0895A Only)

    CHAPTER 4 MEMORY BANK SELECT FUNCTION μ PD78F0889A, 78F0890A, 78F0892A to 78F0895A ONLY) 4.1 Memory Bank μ PD78F0889A, 78F0890A, 78F0892A to 78F0895A implement a ROM capacity of 96 KB or 128 KB by selecting a memory bank from a memory space of 8000H to BFFFH. μ...

  • Page 119: Difference In Representation Of Memory Space

    μ CHAPTER 4 MEMORY BANK SELECT FUNCTION ( PD78F0889A, 78F0890A, 78F0892A to 78F0895A ONLY) 4.2 Difference in Representation of Memory Space With the 78K0/Fx2 microcontrollers which support the memory bank, addresses can be viewed in the following two different ways. •...

  • Page 120: Memory Bank Select Register (Bank)

    μ CHAPTER 4 MEMORY BANK SELECT FUNCTION ( PD78F0889A, 78F0890A, 78F0892A to 78F0895A ONLY) Table 4-1. Memory Bank Address Representation Memory Bank Number CPU Address Flash Memory Real Address Address Representation in Note 1 Simulator and Debugger Note 2 Memory bank 0 08000H-0BFFFH 08000H-0BFFFH 08000H-0BFFFH...

  • Page 121: Selecting Memory Bank

    μ CHAPTER 4 MEMORY BANK SELECT FUNCTION ( PD78F0889A, 78F0890A, 78F0892A to 78F0895A ONLY) 4.4 Selecting Memory Bank The memory bank selected by the memory bank select register (BANK) is reflected on the bank area and can be addressed. Therefore, to access a memory bank different from the one currently selected, that memory bank must be selected by using the BANK register.
  • Page 122 μ CHAPTER 4 MEMORY BANK SELECT FUNCTION ( PD78F0889A, 78F0890A, 78F0892A to 78F0895A ONLY) • Software example (to store a value to be referenced in register A) RAMD DSEG SADDR R_BNKA: ; Secures RAM for specifying an address at the reference destination. R_BNKN: ;...

  • Page 123: Branching Instruction Between Memory Banks

    μ CHAPTER 4 MEMORY BANK SELECT FUNCTION ( PD78F0889A, 78F0890A, 78F0892A to 78F0895A ONLY) 4.4.2 Branching instruction between memory banks Instructions cannot branch directly from one memory bank to another. To branch an instruction from one memory bank to another, branch once to the common area (0000H to 7FFFH), change the setting of the BANK register there, and then execute the branch instruction again.
  • Page 124 μ CHAPTER 4 MEMORY BANK SELECT FUNCTION ( PD78F0889A, 78F0890A, 78F0892A to 78F0895A ONLY) • Software example 1 (to branch from all areas) RAMD DSEG SADDR R_BNKA: ; Secures RAM for specifying a memory bank at the branch destination. R_BNKN: ;...

  • Page 125: Subroutine Call Between Memory Banks

    μ CHAPTER 4 MEMORY BANK SELECT FUNCTION ( PD78F0889A, 78F0890A, 78F0892A to 78F0895A ONLY) 4.4.3 Subroutine call between memory banks Subroutines cannot be directly called between memory banks. To call a subroutine between memory banks, branch once to the common area (0000H to 7FFFH), specify the memory bank at the calling destination by using the BANK register there, execute the CALL instruction, and branch to the call destination by that instruction.
  • Page 126 μ CHAPTER 4 MEMORY BANK SELECT FUNCTION ( PD78F0889A, 78F0890A, 78F0892A to 78F0895A ONLY) • Software example RAMD DSEG SADDR R_BNKA: ; Secures RAM for specifying an address at the calling destination. R_BNKN: ; Secures RAM for specifying a memory bank number at the calling destination. R_BNKRN: DS ;...

  • Page 127: Instruction Branch To Bank Area By Interrupt

    μ CHAPTER 4 MEMORY BANK SELECT FUNCTION ( PD78F0889A, 78F0890A, 78F0892A to 78F0895A ONLY) 4.4.4 Instruction branch to bank area by interrupt When an interrupt occurs, instructions can branch to the memory bank specified by the BANK register by using the vector table, but it is difficult to identify the BANK register when the interrupt occurs.
  • Page 128 μ CHAPTER 4 MEMORY BANK SELECT FUNCTION ( PD78F0889A, 78F0890A, 78F0892A to 78F0895A ONLY) Remark Note the following points to use the memory bank select function efficiently. • Allocate a routine that is used often in the common area. • If a value that is planned to be referenced is placed in RAM, it can be referenced from all of the areas. •...

  • Page 129: Chapter 5 Port Functions

    CHAPTER 5 PORT FUNCTIONS 5.1 Port Functions Pin I/O buffer power supplies depend on the product. The relationship between these power supplies and the pins is shown below. Table 5-1. Pin I/O Buffer Power Supplies (AV , EV • 78K0/FC2: 44-pin plastic LQFP (10x10), 48-pin plastic LQFP (fine pitch) (7x7) Power Supply Corresponding Pins Note...
  • Page 130 CHAPTER 5 PORT FUNCTIONS Table 5-3. Port Functions (1/2) Pin Name Function After Reset Alternate Function √ √ √ Port 0. Input TI000 4-bit I/O port. √ √ √ TI010/TO00 Input/output can be specified in 1-bit units. − √ √ SSI11/TI001 Use of an on-chip pull-up resistor can be specified √...
  • Page 131 CHAPTER 5 PORT FUNCTIONS Table 5-3. Port Functions (2/2) Pin Name Function After Reset Alternate Function √ √ √ P80 to P87 Port 8. Input ANI0 to ANI7 8-bit I/O port. Input/output can be specified in 1-bit units. √ √ Note Port 9.

  • Page 132: Port Configuration

    CHAPTER 5 PORT FUNCTIONS 5.2 Port Configuration Ports include the following hardware. Table 5-4. Port Configuration Item Configuration • 44-pin products of 78K0/FC2 Control registers Port mode register (PM0, PM1, PM3, PM4, PM6 to PM8, PM12) Port register (P0, P1, P3, P4, P6 to P8, P12, P13) Pull-up resistor option register (PU0, PU1, PU3, PU4, PU7, PU12) A/D port configuration register (ADPC) •...

  • Page 133: Port 0

    CHAPTER 5 PORT FUNCTIONS 5.2.1 Port 0 78K0/FC2 78K0/FE2 78K0/FF2 μ μ μ PD78F088yA, 78F089zA) PD78F088yA, 78F0890A) PD78F089yA) y = 1 to 3 y = 4 to 6, z = 4, 5 y = 7 to 9 y = 1 to 3 √...
  • Page 134 CHAPTER 5 PORT FUNCTIONS Figure 5-1. Block Diagram of P00 and P05 PU00, PU05 P-ch Alternate function PORT Output latch P00/TI000, (P00, P05) P05/SSI11/TI001 PM00, PM05 Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 Read signal WR××: Write signal User’s Manual U19180EJ1V0UD...
  • Page 135 CHAPTER 5 PORT FUNCTIONS Figure 5-2. Block Diagram of P01 and P06 PU01, PU06 P-ch Alternate function PORT Output latch P01/TI010/TO00, (P01, P06) P06/TI011/TO01 PM01, PM06 Alternate function Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 Read signal WR××: Write signal User’s Manual U19180EJ1V0UD...

  • Page 136: Port 1

    CHAPTER 5 PORT FUNCTIONS 5.2.2 Port 1 78K0/FC2 78K0/FE2 78K0/FF2 μ μ μ PD78F088yA, 78F089zA) PD78F088yA, 78F0890A) PD78F089yA) y = 1 to 6, z = 4, 5 y = 7 to 9 y = 1 to 3 √ P10/SCK10/TxD61 √ P11/SI10/RxD61 √...
  • Page 137 CHAPTER 5 PORT FUNCTIONS Figure 5-3. Block Diagram of P10 PU10 P-ch Alternate function PORT Output latch P10/SCK10/TxD61 (P10) PM10 Alternate function Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 Read signal WR××: Write signal User’s Manual U19180EJ1V0UD...
  • Page 138 CHAPTER 5 PORT FUNCTIONS Figure 5-4. Block Diagram of P11 and P14 PU11, PU14 P-ch Alternate function PORT Output latch P11/SI10/RxD61, (P11, P14) P14/RxD60 PM11, PM14 Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 Read signal WR××: Write signal User’s Manual U19180EJ1V0UD...
  • Page 139 CHAPTER 5 PORT FUNCTIONS Figure 5-5. Block Diagram of P12 and P15 PU12, PU15 P-ch PORT Output latch (P12, P15) P12/SO10, P15/TOH0 PM12, PM15 Alternate function Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 Read signal WR××: Write signal User’s Manual U19180EJ1V0UD...
  • Page 140 CHAPTER 5 PORT FUNCTIONS Figure 5-6. Block Diagram of P13 PU13 P-ch PORT Output latch P13/TxD60 (P13) PM13 Alternate function Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 Read signal WR××: Write signal User’s Manual U19180EJ1V0UD...
  • Page 141 CHAPTER 5 PORT FUNCTIONS Figure 5-7. Block Diagram of P16 and P17 PU16, PU17 P-ch Alternate function PORT Output latch P16/TOH1/INTP5, (P16, P17) P17/TI50/TO50 PM16, PM17 Alternate function Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 Read signal WR××: Write signal User’s Manual U19180EJ1V0UD...

  • Page 142: Port 3

    CHAPTER 5 PORT FUNCTIONS 5.2.3 Port 3 78K0/FC2 78K0/FE2 78K0/FF2 μ μ μ PD78F088yA, 78F089zA) PD78F088yA, 78F0890A) PD78F089yA) y = 1 to 6, z = 4, 5 y = 7 to 9 y = 1 to 3 √ √ P30/INTP1 √...
  • Page 143 CHAPTER 5 PORT FUNCTIONS Figure 5-8. Block Diagram of P30 and P31 PU30, PU31 P-ch Alternate function PORT Output latch P30/INTP1, (P30, P31) Note P31/INTP2/TI002 PM30, PM31 Note TI002 is 78K0/FE2, 78K0/FF2 only. Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 Read signal...
  • Page 144 CHAPTER 5 PORT FUNCTIONS Figure 5-9. Block Diagram of P32 (1/2) (1) 78K0/FC2 PU32 P-ch Alternate function PORT Output latch P32/INTP3 (P32) PM32 Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 Read signal WR××: Write signal User’s Manual U19180EJ1V0UD...
  • Page 145 CHAPTER 5 PORT FUNCTIONS Figure 5-9. Block Diagram of P32 and P33 (2/2) (2) 78K0/FE2, 78K0/FF2 PU32 P-ch Alternate function PORT Output latch P32/INTP3/TI012/TO02 (P32) PM32 Alternate function Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 Read signal WR××: Write signal User’s Manual U19180EJ1V0UD...
  • Page 146 CHAPTER 5 PORT FUNCTIONS Figure 5-10. Block Diagram of P33 PU33 P-ch Alternate function PORT Output latch P33/INTP4/TI51/TO51 (P33) PM33 Alternate function Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 Read signal WR××: Write signal User’s Manual U19180EJ1V0UD...

  • Page 147: Port 4

    CHAPTER 5 PORT FUNCTIONS 5.2.4 Port 4 78K0/FC2 78K0/FE2 78K0/FF2 μ μ μ PD78F088yA, 78F089zA) PD78F088yA, 78F0890A) PD78F089yA) y = 1 to 6, z = 4, 5 y = 7 to 9 y = 1 to 3 √ √ √ √...

  • Page 148: Port 5

    CHAPTER 5 PORT FUNCTIONS 5.2.5 Port 5 78K0/FC2 78K0/FE2 78K0/FF2 μ μ μ PD78F088yA, 78F089zA) PD78F088yA, 78F0890A) PD78F089yA) y = 1 to 6, z = 4, 5 y = 7 to 9 y = 1 to 3 − √ √ −...

  • Page 149: Port 6

    CHAPTER 5 PORT FUNCTIONS 5.2.6 Port 6 78K0/FC2 78K0/FE2 78K0/FF2 μ μ μ PD78F088yA, 78F089zA) PD78F088yA, 78F0890A) PD78F089yA) y = 1 to 3 y = 4 to 6, z = 4, 5 y = 7 to 9 y = 1 to 3 √...
  • Page 150 CHAPTER 5 PORT FUNCTIONS Figure 5-13. Block Diagram of P60 to P63 Selector PORT Output latch P60 to P63 (P60 to P63) PM60 to PM63 Port register 6 PM6: Port mode register 6 Read signal WR××: Write signal User’s Manual U19180EJ1V0UD...
  • Page 151 CHAPTER 5 PORT FUNCTIONS Figure 5-14. Block Diagram of P64 to P67 PU64 to PU67 P-ch Selector PORT Output latch P64 to P67 (P64 to P67) PM64 to PM67 Port register 6 PU6: Pull-up resistor option register 6 PM6: Port mode register 6 Read signal WR××: Write signal User’s Manual U19180EJ1V0UD...

  • Page 152: Port 7

    CHAPTER 5 PORT FUNCTIONS 5.2.7 Port 7 78K0/FC2 78K0/FE2 78K0/FF2 μ μ μ PD78F088yA, 78F089zA) PD78F088yA, 78F0890A) PD78F089yA) y = 1 to 6, z = 4, 5 y = 7 to 9 y = 1 to 3 √ √ √ P70/CTxD √...
  • Page 153 CHAPTER 5 PORT FUNCTIONS Figure 5-15. Block Diagram of P70 and P74 PU70, PU74 P-ch PORT Output latch P70/CTxD, (P70, P74) P74/SO11 PM70, PM74 Alternate function Port register 7 PU7: Pull-up resistor option register 7 PM7: Port mode register 7 Read signal WR××: Write signal User’s Manual U19180EJ1V0UD...
  • Page 154 CHAPTER 5 PORT FUNCTIONS Figure 5-16. Block Diagram of P71 and P75 PU71 and PU75 P-ch Alternate function PORT Output latch P71/CRxD (P71 and P75) P75/SI11 PM71 and PM75 Port register 7 PU7: Pull-up resistor option register 7 PM7: Port mode register 7 Read signal WR××: Write signal User’s Manual U19180EJ1V0UD...
  • Page 155 CHAPTER 5 PORT FUNCTIONS Figure 5-17. Block Diagram of P72 and P73 PU72 and PU73 P-ch Alternate function PORT Output latch P72/PCL/INTP6 (P72 and P73) P73/BUZ/INTP7 PM72 and PM73 Alternate function Port register 7 PU7: Pull-up resistor option register 7 PM7: Port mode register 7 Read signal...
  • Page 156 CHAPTER 5 PORT FUNCTIONS Figure 5-18. Block Diagram of P76 PU76 P-ch Alternate function PORT Output latch P76/SCK11 (P76) PM76 Alternate function Port register 7 PU7: Pull-up resistor option register 7 PM7: Port mode register 7 Read signal WR××: Write signal User’s Manual U19180EJ1V0UD...

  • Page 157: Port 8

    CHAPTER 5 PORT FUNCTIONS 5.2.8 Port 8 78K0/FC2 78K0/FE2 78K0/FF2 μ μ μ PD78F088yA, 78F089zA) PD78F088yA, 78F0890A) PD78F089yA) y = 1 to 6, z = 4, 5 y = 7 to 9 y = 1 to 3 √ P80/ANI0 √ P81/ANI1 √...
  • Page 158 CHAPTER 5 PORT FUNCTIONS Figure 5-19. Block Diagram of P80 to P87 PORT Output latch P80/ANI0 to (P80 to P87) P87/ANI7 PM80 to PM87 A/D converter Port register 8 PM8: Port mode register 8 Read signal WR××: Write signal User’s Manual U19180EJ1V0UD...

  • Page 159: Port 9

    CHAPTER 5 PORT FUNCTIONS 5.2.9 Port 9 78K0/FC2 78K0/FE2 78K0/FF2 μ μ μ PD78F088yA, 78F089zA) PD78F088yA, 78F0890A) PD78F089yA) y = 1 to 3 y = 4 to 6, z = 4, 5 y = 7 to 9 y = 1 to 3 −...
  • Page 160 CHAPTER 5 PORT FUNCTIONS Figure 5-20. Block Diagram of P90 to P97 PORT Output latch P90/ANI8 to (P90 to P97) P97/ANI15 PM90 to PM97 A/D converter Port register 9 PM9: Port mode register 9 Read signal WR××: Write signal User’s Manual U19180EJ1V0UD...

  • Page 161: Port 12

    CHAPTER 5 PORT FUNCTIONS 5.2.10 Port 12 78K0/FC2 78K0/FE2 78K0/FF2 μ μ μ PD78F088yA, 78F089zA) PD78F088yA, 78F0890A) PD78F089yA) y = 1 to 6, z = 4, 5 y = 7 to 9 y = 1 to 3 √ P120/INTP0/EXLVI √ P121/X1 √...
  • Page 162 CHAPTER 5 PORT FUNCTIONS Figure 5-21. Block Diagram of P120 PU12 PU120 P-ch Alternate function PORT Output latch P120/INTP0/EXLVI (P120) PM12 PM120 P12: Port register 12 PU12: Pull-up resistor option register 12 PM12: Port mode register 12 Read signal WR××: Write signal User’s Manual U19180EJ1V0UD...
  • Page 163 CHAPTER 5 PORT FUNCTIONS Figure 5-22. Block Diagram of P121 to P124 OSCCTL OSCSEL/ OSCSELS PORT Output latch P122/X2/EXCLK, (P122/P124) P124/XT2/EXCLKS PM12 PM122/PM124 OSCCTL OSCSEL/ OSCSELS OSCCTL EXCLK, OSCSEL/ EXCLKS, OSCSELS PORT Output latch (P121/P123) P121/X1, P123/XT1 PM12 PM121/PM123 OSCCTL OSCSEL/OSCSELS OSCCTL EXCLK/EXCLKS...

  • Page 164: Port 13

    CHAPTER 5 PORT FUNCTIONS 5.2.11 Port 13 78K0/FC2 78K0/FE2 78K0/FF2 μ μ μ PD78F088yA, 78F089zA) PD78F088yA, 78F0890A) PD78F089yA) y = 1 to 3 y = 4 to 6, z = 4, 5 y = 7 to 9 y = 1 to 3 √...
  • Page 165 CHAPTER 5 PORT FUNCTIONS Figure 5-24. Block Diagram of P131 (1/2) μ PD78F0884A, 78F0885A, 78F0886A, 78F0894A, and 78F0895A of 78K0/FC2 PU13 PU131 P-ch Selector PORT Output latch P131 (P131) PM13 PM131 P13: Port register 13 PU13: Pull-up resistor option register 13 PM13: Port mode register 13 Read signal...
  • Page 166 CHAPTER 5 PORT FUNCTIONS Figure 5-24. Block Diagram of P131 (2/2) (1) 78K0/FF2, 78F0/FE2 PU13 PU131 P-ch Alternate function PORT Output latch P131/TI003 (P131) PM13 PM131 P13: Port register 13 PU13: Pull-up resistor option register 13 PM13: Port mode register 13 Read signal WR××: Write signal User’s Manual U19180EJ1V0UD...
  • Page 167 CHAPTER 5 PORT FUNCTIONS Figure 5-25. Block Diagram of P132 PU13 PU132 P-ch Alternate function PORT Output latch P132/TI013/TO03 (P132) PM13 PM132 Alternate function P13: Port register 13 PU13: Pull-up resistor option register 13 PM13: Port mode register 13 Read signal WR××: Write signal User’s Manual U19180EJ1V0UD...

  • Page 168: Registers Controlling Port Function

    CHAPTER 5 PORT FUNCTIONS 5.3 Registers Controlling Port Function Port functions are controlled by the following four types of registers. • Port mode registers (PMxx) • Port registers (Pxx) • Pull-up resistor option registers (PUxx) • A/D port configuration register (ADPC) User’s Manual U19180EJ1V0UD...
  • Page 169 CHAPTER 5 PORT FUNCTIONS (1) Port mode registers (PMxx) These registers specify input or output mode for the port in 1-bit units. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to FFH except for PM13. PM13 is set to FEH. When port pins are used as alternate-function pins, set the port mode register and output latch as shown in Table 5-7.
  • Page 170 CHAPTER 5 PORT FUNCTIONS Figure 5-27. Format of Port Mode Register (78K0/FE2) Symbol Address After reset PM06 PM05 PM01 PM00 FF20H PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 FF21H PM33 PM32 PM31 PM30 FF23H PM43 PM42 PM41 PM40 FF24H PM53 PM52 PM51...
  • Page 171 CHAPTER 5 PORT FUNCTIONS Figure 5-28. Format of Port Mode Register (78K0/FF2) Symbol Address After reset PM06 PM05 PM01 PM00 FF20H PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 FF21H PM33 PM32 PM31 PM30 FF23H PM47 PM46 PM45 PM44 PM43 PM42 PM41 PM40...
  • Page 172 CHAPTER 5 PORT FUNCTIONS (2) Port registers (Pxx) These registers write the data that is output from the chip when data is output from a port. If the data is read in the input mode, the pin level is read. If it is read in the output mode, the value of the output latch is read.
  • Page 173 CHAPTER 5 PORT FUNCTIONS Figure 5-30. Format of Port Register (78K0/FE2) Symbol Address After reset FF00H 00H (output latch) FF01H 00H (output latch) FF03H 00H (output latch) FF04H 00H (output latch) FF05H 00H (output latch) FF06H 00H (output latch) FF07H 00H (output latch) 00H (output latch) FF08H...
  • Page 174 CHAPTER 5 PORT FUNCTIONS Figure 5-31. Format of Port Register (78K0/FF2) Symbol Address After reset FF00H 00H (output latch) FF01H 00H (output latch) FF03H 00H (output latch) FF04H 00H (output latch) FF05H 00H (output latch) FF06H 00H (output latch) FF07H 00H (output latch) 00H (output latch) FF08H...
  • Page 175 CHAPTER 5 PORT FUNCTIONS Pull-up resistor option registers (PUxx) These registers specify whether the on-chip pull-up resistors are to be used or not. On-chip pull-up resistors can be used in 1-bit units only for the bits set to input mode of the pins to which the use of an on-chip pull-up resistor has been specified in these registers.
  • Page 176 CHAPTER 5 PORT FUNCTIONS Figure 5-33. Format of Pull-up Resistor Option Register (78K0/FE2) Symbol Address After reset PU06 PU05 PU01 PU00 FF30H PU17 PU16 PU15 PU14 PU13 PU12 PU11 PU10 FF31H PU33 PU32 PU31 PU30 FF33H PU43 PU42 PU41 PU40 FF34H PU53 PU52...
  • Page 177 CHAPTER 5 PORT FUNCTIONS Figure 5-34. Format of Pull-up Resistor Option Register (78K0/FF2) Symbol Address After reset PU06 PU05 PU01 PU00 FF30H PU17 PU16 PU15 PU14 PU13 PU12 PU11 PU10 FF31H PU33 PU32 PU31 PU30 FF33H PU47 PU46 PU45 PU44 PU43 PU42 PU41...
  • Page 178 CHAPTER 5 PORT FUNCTIONS (4) A/D port configuration register (ADPC) This register switches the P80/ANI0 to P87/ANI7, P90/ANI8 to P97/ANI15 pins to analog input of A/D converter or digital I/O of port. ADPC can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
  • Page 179 CHAPTER 5 PORT FUNCTIONS Figure 5-35. Format of A/D Port Configuration Register (ADPC) Address: FF22H After reset: 00H Symbol ADPC ADPC4 ADPC3 ADPC2 ADPC1 ADPC0 Analog input (A)/ digital input (D) switching P97/ P96/ P95/ P94/ P93/ P92/ P91/ P90/ P87/ P86/ P85/...

  • Page 180: Port Function Operations

    CHAPTER 5 PORT FUNCTIONS 5.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 5.4.1 Writing to I/O port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin. Once data is written to the output latch, it is retained until data is written to the output latch again.

  • Page 181: Settings Of Port Mode Register And Output Latch When Using Alternate Function

    CHAPTER 5 PORT FUNCTIONS 5.5 Settings of Port Mode Register and Output Latch When Using Alternate Function To use the alternate function of a port pin, set the port mode register and output latch as shown in Table 5-7. Remark The port pins mounted depend on the product. See Table 5-3. Port Functions. Table 5-7.
  • Page 182 CHAPTER 5 PORT FUNCTIONS Table 5-7. Settings of Port Mode Register and Output Latch When Using Alternate Function (2/2) Alternate Function PM×× P×× Pin Name Function Name Output × INTP7 Input SO11 Output × SI11 Input × SCK11 Input Output ×...

  • Page 183: Cautions On 1-Bit Manipulation Instruction For Port Register N (Pn)

    CHAPTER 5 PORT FUNCTIONS 5.6 Cautions on 1-Bit Manipulation Instruction for Port Register n (Pn) When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the output latch value of an input port that is not subject to manipulation may be written in addition to the targeted bit. Therefore, it is recommended to rewrite the output latch when switching a port from input mode to output mode.

  • Page 184: Chapter 6 Clock Generator

    CHAPTER 6 CLOCK GENERATOR 6.1 Functions of Clock Generator The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following system clocks and clock oscillators are selectable. (1) Main system clock <1> X1 oscillator This circuit oscillates a clock of f = 4 to 20 MHz.

  • Page 185: Configuration Of Clock Generator

    CHAPTER 6 CLOCK GENERATOR 6.2 Configuration of Clock Generator The clock generator includes the following hardware. Table 6-1. Configuration of Clock Generator Item Configuration Control registers Processor clock control register (PCC) Internal oscillator mode register (RCM) Main clock mode register (MCM) Main OSC control register (MOC) Clock operation mode select register (OSCCTL) Oscillation stabilization time counter status register (OSTC)
  • Page 186 Figure 6-1. Block Diagram of Clock Generator Internal bus Main OSC Main clock Clock operation mode Main clock Processor clock Oscillation stabilization control register mode register select register mode register control register time select register (OSTS) (MOC) (MCM) (OSCCTL) (MCM) (PCC) AMPH EXCLK OSCSEL...

  • Page 187: Registers Controlling Clock Generator

    CHAPTER 6 CLOCK GENERATOR Remark f X1 clock oscillation frequency Internal high-speed oscillation clock frequency External main system clock frequency EXCLK High-speed system clock oscillation frequency Main system clock oscillation frequency Peripheral hardware clock frequency CPU clock oscillation frequency XT1 clock oscillation frequency : External subsystem clock frequency EXCLKS Subsystem clock frequency...
  • Page 188 CHAPTER 6 CLOCK GENERATOR Figure 6-2. Format of Processor Clock Control Register (PCC) Note 1 Address: FFFBH After reset: 01H Symbol <5> <4> PCC2 PCC1 PCC0 CPU clock status Main system clock Subsystem clock Note 2 PCC2 PCC1 PCC0 CPU clock (f ) selection /2 (default) Other than above...
  • Page 189 CHAPTER 6 CLOCK GENERATOR (2) Internal oscillator mode register (RCM) This register sets the operation mode of internal oscillator. RCM can be set by a 1-bit or 8-bit memory manipulation instruction. Note 1 Reset signal generation sets this register to 80H Figure 6-3.
  • Page 190 CHAPTER 6 CLOCK GENERATOR (3) Main clock mode register (MCM) This register selects the main system clock supplied to CPU clock and clock supplied to peripheral hardware clock. MCM can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
  • Page 191 CHAPTER 6 CLOCK GENERATOR (4) Main OSC control register (MOC) This register selects the operation mode of the high-speed system clock. This register is used to stop the X1 oscillator or to disable an external clock input from the EXCLK pin when the CPU operates with a clock other than the high-speed system clock.
  • Page 192 CHAPTER 6 CLOCK GENERATOR (5) Clock operation mode select register (OSCCTL) This register selects the operation modes of the high-speed system and subsystem clocks. OSCCTL can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 6-6.
  • Page 193 CHAPTER 6 CLOCK GENERATOR Cautions 6. To change the value of EXCLK and OSCSEL, be sure to confirm that bit 7 (MSTOP) of the main OSC control register (MOC) is 1 (the X1 oscillator stops or the external clock from the EXCLK pin is disabled). 7.
  • Page 194 CHAPTER 6 CLOCK GENERATOR (6) Oscillation stabilization time counter status register (OSTC) This is the status register of the X1 clock oscillation stabilization time counter. If the internal high-speed oscillation clock or subsystem clock is used as the CPU clock, the X1 clock oscillation stabilization time can be checked.
  • Page 195 CHAPTER 6 CLOCK GENERATOR (7) Oscillation stabilization time select register (OSTS) This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released. The wait time set by OSTS is valid only after the STOP mode is released with the X1 clock selected as the CPU clock.

  • Page 196: System Clock Oscillator

    CHAPTER 6 CLOCK GENERATOR 6.4 System Clock Oscillator 6.4.1 X1 oscillator The X1 oscillator oscillates with a crystal resonator or ceramic resonator (4 to 20 MHz) connected to the X1 and X2 pins. An external clock can also be input. In this case, input the clock signal to the EXCLK pin. Figure 6-9 shows an example of the external circuit of the X1 oscillator.
  • Page 197 CHAPTER 6 CLOCK GENERATOR Caution When using the X1 oscillator and XT1 oscillator, wire as follows in the area enclosed by the broken lines in the Figures 6-9 and 6-10 to avoid an adverse effect from wiring capacitance. • Keep the wiring length as short as possible. •...
  • Page 198 CHAPTER 6 CLOCK GENERATOR Figure 6-11. Examples of Incorrect Resonator Connection (2/2) (c) Wiring near high alternating current (d) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) High current (e) Signals are fetched Remark When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively.

  • Page 199: When Subsystem Clock Is Not Used

    CHAPTER 6 CLOCK GENERATOR 6.4.3 When subsystem clock is not used If it is not necessary to use the subsystem clock for low power consumption operations, or if not using the subsystem clock as an I/O port, set the XT1 and XT2 pins to I/O mode (OSCSELS = 0) and connect them as follows. Input (PM123/PM124 = 1): Independently connect to V or V...

  • Page 200: Clock Generator Operation

    CHAPTER 6 CLOCK GENERATOR 6.5 Clock Generator Operation The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby mode. • Main system clock f • High-speed system clock f X1 clock f External main system clock f EXCLK •...
  • Page 201 CHAPTER 6 CLOCK GENERATOR Figure 6-12 Operation of the clock generating circuit when power supply voltage injection (When 1.59 V POC mode setup (option byte: LVISTART = 0)) Power supply 1.8 V voltage (V 1.59 V (TYP.) 0.5 V/ms Notes 1, 2 (MIN.
  • Page 202 CHAPTER 6 CLOCK GENERATOR Notes 3. The internal voltage stabilization time includes the oscillation accuracy stabilization time of the internal high-speed oscillation clock. When releasing a reset (above figure) or releasing STOP mode while the CPU is operating on the internal high-speed oscillation clock, confirm the oscillation stabilization time for the X1 clock using the oscillation stabilization time counter status register (OSTC).
  • Page 203 CHAPTER 6 CLOCK GENERATOR Cautions 1. When the standup of voltage until it reaches 1.8 V from the time of a power supply injection is looser than 0.5 V/ms (MIN.), input a low level into RESET pin, or set up 2.7 V/1.59 V POC mode (LVISTART = 1) from an option byte until it reaches 1.8 V from the time of a power supply injection (refer to Figure 6-13).
  • Page 204 CHAPTER 6 CLOCK GENERATOR Figure 6-13 Operation of the clock generating circuit when power supply voltage injection (When 2.7 V/1.59V POC mode setup (option byte: LVISTART = 1)) 2.7 V (TYP.) Power supply voltage (V Internal reset signal <1> Reset processing <3>...

  • Page 205: Controlling Clock

    CHAPTER 6 CLOCK GENERATOR Remark The clock which is not used as a CPU clock can be suspended by setup of software during microcomputer operation. Moreover, high-speed oscillation clock and a high-speed system clock can suspend a clock by execution of a STOP command (see (4) in 6.6.1 Controlling high-speed system clock, (3) in 6.6.2 Example of controlling internal high-speed oscillation clock, and (4) in 6.6.3 Example of controlling subsystem clock).
  • Page 206 CHAPTER 6 CLOCK GENERATOR <4> Waiting for the stabilization of the oscillation of X1 clock Check the OSTC register and wait for the necessary time. During the wait time, other software processing can be executed with the internal high-speed oscillation clock.
  • Page 207 CHAPTER 6 CLOCK GENERATOR <2> Setting the high-speed system clock as the main system clock (MCM register) When XSEL and MCM0 are set to 1, the high-speed system clock is supplied as the main system clock and peripheral hardware clock. XSEL MCM0 Selection of Main System Clock and Clock Supplied to Peripheral Hardware...

  • Page 208: Example Of Controlling Internal High-Speed Oscillation Clock

    CHAPTER 6 CLOCK GENERATOR (b) To stop X1 oscillation (disabling external clock input) by setting MSTOP to 1 <1> Confirming the CPU clock status (PCC and MCM registers) Confirm with CLS and MCS that the CPU is operating on a clock other than the high-speed system clock.
  • Page 209 CHAPTER 6 CLOCK GENERATOR Note The setting of <1> is not necessary when the internal high-speed oscillation clock or high- speed system clock is already operating. <2> Selecting the clock supplied as the main system clock and peripheral hardware clock (MCM register) Set the main system clock and peripheral hardware clock using XSEL and MCM0.

  • Page 210: Example Of Controlling Subsystem Clock

    CHAPTER 6 CLOCK GENERATOR (b) To stop internal high-speed oscillation clock by setting RSTOP to 1 <1> Confirming the CPU clock status (PCC and MCM registers) Confirm with CLS and MCS that the CPU is operating on a clock other than the internal high-speed oscillation clock.
  • Page 211 CHAPTER 6 CLOCK GENERATOR (2) Example of setting procedure when using the external subsystem clock <1> Setting XT1 and XT2 pins, selecting XT1 clock/external clock and controlling oscillation (PCC and OSCCTL registers) When XTSTART is cleared to 0 and EXCLKS and OSCSELS are set to 1, the mode is switched from port mode to external clock input mode.

  • Page 212: Controlling Internal Low-Speed Oscillation Clock

    CHAPTER 6 CLOCK GENERATOR 6.6.4 Controlling internal low-speed oscillation clock The internal low-speed oscillation clock is a clock for the watchdog timer. It cannot be used as the CPU clock. With this clock, only the following peripheral hardware can operate. •...

  • Page 213: Cpu Clock Status Transition Diagram

    CHAPTER 6 CLOCK GENERATOR 6.6.6 CPU clock status transition diagram Figure 6-14 shows the CPU clock status transition diagram of this product. Figure 6-14. CPU Clock Status Transition Diagram (When 1.59 V POC Mode Is Set (Option Byte: LVISTART = 0)) Internal low-speed oscillation: Woken up Power ON Internal high-speed oscillation: Woken up...
  • Page 214 CHAPTER 6 CLOCK GENERATOR Table 6-4 shows transition of the CPU clock and examples of setting the SFR registers. Table 6-4. CPU Clock Transition and SFR Register Setting Examples (1/4) (1) CPU operating with high-speed system clock (C) after reset release (A) (The CPU operates with the internal high-speed oscillation clock immediately after a reset release (B).) (Setting sequence of SFR registers) Setting Flag of SFR Register...
  • Page 215 CHAPTER 6 CLOCK GENERATOR Table 6-4. CPU Clock Transition and SFR Register Setting Examples (2/4) (4) CPU clock changing from internal high-speed oscillation clock (B) to high-speed system clock (C) (Setting sequence of SFR registers) Setting Flag of SFR Register AMPH EXCLK OSCSEL...
  • Page 216 CHAPTER 6 CLOCK GENERATOR Table 6-4. CPU Clock Transition and SFR Register Setting Examples (3/4) (6) CPU clock changing from high-speed system clock (C) to internal high-speed oscillation clock (B) (Setting sequence of SFR registers) Setting Flag of SFR Register RSTOP RSTS MCM0...
  • Page 217 CHAPTER 6 CLOCK GENERATOR Table 6-4. CPU Clock Transition and SFR Register Setting Examples (4/4) (9) CPU clock changing from subsystem clock (D) to internal high-speed oscillation clock (B) (Setting sequence of SFR registers) Setting Flag of SFR Register RSTOP RSTS MCM0 Status Transition...

  • Page 218: Condition Before Changing Cpu Clock And Processing After Changing Cpu Clock

    CHAPTER 6 CLOCK GENERATOR 6.6.7 Condition before changing CPU clock and processing after changing CPU clock Condition before changing the CPU clock and processing after changing the CPU clock are shown below. Table 6-5. Changing CPU Clock CPU Clock Condition Before Change Processing After Change Before Change After Change...

  • Page 219: Time Required For Switchover Of Cpu Clock And Main System Clock

    CHAPTER 6 CLOCK GENERATOR 6.6.8 Time required for switchover of CPU clock and main system clock By setting bits 0 to 2 (PCC0 to PCC2) and bit 4 (CSS) of the processor clock control register (PCC), the CPU clock can be switched (between the main system clock and the subsystem clock) and the division ratio of the main system clock can be changed.

  • Page 220: Conditions Before Clock Oscillation Is Stopped

    CHAPTER 6 CLOCK GENERATOR Table 6-7. Maximum Time Required for Main System Clock Switchover Set Value Before Switchover Set Value After Switchover MCM0 MCM0 1 + 2f clock 1 + 2f clock Caution When switching the internal high-speed oscillation clock to the high-speed system clock, bit 2 (XSEL) of MCM must be set to 1 in advance.

  • Page 221: Chapter 7 16-Bit Timer/Event Counters 00 To 03

    CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 78K0/FC2 78K0/FE2 78K0/FF2 μ μ μ PD78F088yA, 78F089zA) PD78F088yA, 78F0890A) PD78F089yA) y = 1 to 3 y = 4 to 6, z = 4, 5 y = 7 to 9 y = 1 to 3 16-bit timer/event √...

  • Page 222: Functions Of 16-Bit Timer/Event Counters 00 To 03

    CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 7.1 Functions of 16-Bit Timer/Event Counters 00 to 03 16-bit timer/event counters 00 to 03 have the following functions. • Interval timer • PPG output • Pulse width measurement • External event counter •...

  • Page 223: Configuration Of 16-Bit Timer/Event Counters 00 To 03

    CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 7.2 Configuration of 16-Bit Timer/Event Counters 00 to 03 16-bit timer/event counters 00 to 03 include the following hardware. Table 7-1. Configuration of 16-Bit Timer/Event Counters 00 to 03 Item Configuration Timer counter 16 bits (TM0n) Register 16-bit timer capture/compare register: 16 bits (CR00n, CR01n)
  • Page 224 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 μ Figure 7-2. Block Diagram of 16-Bit Timer/Event Counter 01 ( PD78F0881A, 78F0882A, 78F0883A of 78K0/FC2) Internal bus Capture/compare control register 01 (CRC01) CRC012CRC011 CRC010 INTTM001 Noise 16-bit timer capture/compare elimi- register 001 (CR001) nator Match 16-bit timer counter 01...
  • Page 225 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-4. Block Diagram of 16-Bit Timer/Event Counter 01 (78K0/FE2, 78K0/FF2) Internal bus Capture/compare control register 01 (CRC01) CRC012CRC011 CRC010 INTTM001 Noise 16-bit timer capture/compare TI011/TO01/P06 elimi- register 001 (CR001) nator Match 16-bit timer counter 01 Clear (TM01)
  • Page 226 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-6. Block Diagram of 16-Bit Timer/Event Counter 03 Internal bus Capture/compare control register 03 (CRC03) CRC032CRC031 CRC030 INTTM003 16-bit timer capture/compare Noise elimi- TI013/TO03/P132 register 003 (CR003) nator Match 16-bit timer counter 03 Clear (TM03) Output...
  • Page 227 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 (1) 16-bit timer counter 0n (TM0n) TM0n is a 16-bit read-only register that counts count pulses. The counter is incremented in synchronization with the rising edge of the count clock. If the count value is read during operation, then input of the count clock is temporarily stopped, and the count value at that point is read.
  • Page 228 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 (2) 16-bit timer capture/compare register 00n (CR00n) CR00n is a 16-bit register that has the functions of both a capture register and a compare register. Whether it is used as a capture register or as a compare register is set by bit 0 (CRC0n0) of capture/compare control register 0n (CRC0n).
  • Page 229 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Table 7-2. CR00n Capture Trigger and Valid Edges of TI00n and TI01n Pins (1) TI00n pin valid edge selected as capture trigger (CRC0n1 = 1, CRC0n0 = 1) CR00n Capture Trigger TI00n Pin Valid Edge ES0n1 ES0n0 Falling edge...
  • Page 230 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 (3) 16-bit timer capture/compare register 01n (CR01n) CR01n is a 16-bit register that has the functions of both a capture register and a compare register. Whether it is used as a capture register or a compare register is set by bit 2 (CRC0n2) of capture/compare control register 0n (CRC0n).
  • Page 231 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Table 7-3. CR01n Capture Trigger and Valid Edge of TI00n Pin (CRC0n2 = 1) CR01n Capture Trigger TI00n Pin Valid Edge ES0n1 ES0n0 Falling edge Falling edge Rising edge Rising edge Both rising and falling edges Both rising and falling edges Cautions 1.
  • Page 232 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 (4) Setting range when CR00n or CR01n is used as a compare register When CR00n or CR01n is used as a compare register, set it as shown below. Operation CR00n Register Setting Range CR01n Register Setting Range Note 0000H <...
  • Page 233 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Table 7-4. Capture Operation of CR00n and CR01n External Input Signal TI00n Pin Input TI01n Pin Input Capture Operation Capture operation of CRC0n1 = 1 Set values of ES0n1 and CRC0n1 bit = 0 Set values of ES1n1 and CR00n TI00n pin input...

  • Page 234: Registers Controlling 16-Bit Timer/Event Counters 00 To 03

    CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 7.3 Registers Controlling 16-Bit Timer/Event Counters 00 to 03 The following six registers are used to control 16-bit timer/event counters 00 to 03. • 16-bit timer mode control register 0n (TMC0n) • Capture/compare control register 0n (CRC0n) •...
  • Page 235 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-10. Format of 16-Bit Timer Mode Control Register 00 (TMC00) Address: FFBAH After reset: 00H Symbol <0> TMC00 TMC003 TMC002 TMC001 OVF00 TMC003 TMC002 Operation enable of 16-bit timer/event counter 00 Disables 16-bit timer/event counter 00 operation.
  • Page 236 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-11. Format of 16-Bit Timer Mode Control Register 01 (TMC01) Address: FFB6H After reset: 00H Symbol <0> TMC01 TMC013 TMC012 TMC011 OVF01 TMC013 TMC012 Operation enable of 16-bit timer/event counter 01 Disables 16-bit timer/event counter 01 operation.
  • Page 237 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-12. Format of 16-Bit Timer Mode Control Register 02 (TMC02) Address: FF54H After reset: 00H Symbol <0> TMC02 TMC023 TMC022 TMC021 OVF02 TMC023 TMC022 Operation enable of 16-bit timer/event counter 02 Disables 16-bit timer/event counter 02 operation.
  • Page 238 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-13. Format of 16-Bit Timer Mode Control Register 03 (TMC03) Address: FFADH After reset: 00H Symbol <0> TMC03 TMC033 TMC032 TMC031 OVF03 TMC033 TMC032 Operation enable of 16-bit timer/event counter 03 Disables 16-bit timer/event counter 03 operation.
  • Page 239 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 (2) Capture/compare control register 0n (CRC0n) CRC0n is the register that controls the operation of CR00n and CR01n. Changing the value of CRC0n is prohibited during operation (when TMC0n3 and TMC0n2 = other than 00). CRC0n can be set by a 1-bit or 8-bit memory manipulation instruction.
  • Page 240 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-15. Example of CR01n Capture Operation (When Rising Edge Is Specified) Valid edge Count clock N − 3 N − 2 N − 1 TM0n N + 1 TI00n Rising edge detection CR01n INTTM01n Remark n = 0, 1:...
  • Page 241 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-17. Format of Capture/Compare Control Register 02 (CRC02) Address: FF5CH After reset: 00H Symbol CRC02 CRC022 CRC021 CRC020 CRC022 CR012 operating mode selection Operates as compare register Operates as capture register CRC021 CR002 capture trigger selection Captures on valid edge of TI012 pin...
  • Page 242 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-18. Format of Capture/Compare Control Register 03 (CRC03) Address: FF52H After reset: 00H Symbol CRC03 CRC032 CRC031 CRC030 CRC032 CR013 operating mode selection Operates as compare register Operates as capture register CRC031 CR003 capture trigger selection Captures on valid edge of TI013 pin...
  • Page 243 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 (3) 16-bit timer output control register 0n (TOC0n) TOC0n is an 8-bit register that controls the TO0n pin output. TOC0n can be rewritten while only OSPT0n is operating (when TMC0n3 and TMC0n2 = other than 00). Rewriting the other bits is prohibited during operation.
  • Page 244 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-19. Format of 16-Bit Timer Output Control Register 00 (TOC00) Address: FFBDH After reset: 00H Symbol <6> <5> <3> <2> <0> TOC00 OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00 OSPT00 One-shot pulse output trigger via software −...
  • Page 245 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-20. Format of 16-Bit Timer Output Control Register 01 (TOC01) Address: FFB9H After reset: 00H Symbol <6> <5> <3> <2> <0> Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 TOC01...
  • Page 246 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-21. Format of 16-Bit Timer Output Control Register 02 (TOC02) Address: FFA5H After reset: 00H Symbol <6> <5> <3> <2> <0> TOC02 OSPT02 OSPE02 TOC024 LVS02 LVR02 TOC021 TOE02 OSPT02 One-shot pulse output trigger via software −...
  • Page 247 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-22. Format of 16-Bit Timer Output Control Register 03 (TOC03) Address: FFF9H After reset: 00H Symbol <6> <5> <3> <2> <0> TOC03 OSPT03 OSPE03 TOC034 LVS03 LVR03 TOC031 TOE03 OSPT03 One-shot pulse output trigger via software −...
  • Page 248 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 (4) Prescaler mode register 0n (PRM0n) PRM0n is the register that sets the TM0n count clock and TI00n and TI01n pin input valid edges. Rewriting PRM0n is prohibited during operation (when TMC0n3 and TMC0n2 = other than 00). PRM0n can be set by a 1-bit or 8-bit memory manipulation instruction.
  • Page 249 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-23. Format of Prescaler Mode Register 00 (PRM00) Address: FFBBH After reset: 00H Symbol PRM00 ES101 ES100 ES001 ES000 PRM001 PRM000 ES101 ES100 TI010 pin valid edge selection Falling edge Rising edge Setting prohibited Both falling and rising edges ES001...
  • Page 250 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-24. Format of Prescaler Mode Register 01 (PRM01) Address: FFB7H After reset: 00H Symbol Note 1 Note 1 Note 2 Note 2 PRM01 ES111 ES110 ES011 ES010 PRM011 PRM010 ES111 ES110 TI011 pin valid edge selection Falling edge Rising edge...
  • Page 251 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-25. Format of Prescaler Mode Register 02 (PRM02) Address: FF59H After reset: 00H Symbol PRM02 ES121 ES120 ES021 ES020 PRM021 PRM020 ES121 ES120 TI012 pin valid edge selection Falling edge Rising edge Setting prohibited Both falling and rising edges ES021...
  • Page 252 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-26. Format of Prescaler Mode Register 03 (PRM03) Address: FF51H After reset: 00H Symbol PRM03 ES131 ES130 ES031 ES030 PRM031 PRM030 ES131 ES130 TI013 pin valid edge selection Falling edge Rising edge Setting prohibited Both falling and rising edges ES031...
  • Page 253 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 (5) Port mode register 0 (PM0) This register sets port 0 input/output in 1-bit units. When using the P01/TO00/TI010 and P06/TO01/TI011 pins for timer output, set PM01 and PM06 and the output latch of P01 and P06 to 0.
  • Page 254 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 (7) Port mode register 13 (PM13) This register sets port 13 input/output in 1-bit units. When using the P132/TO03/TI013 pin for timer output, set PM132 and the output latch of P132 to 0. When using the P131/TI003 and P132/TI013/TO03 pins for timer input, set PM131 and PM132 to 1.

  • Page 255: Operation Of 16-Bit Timer/Event Counters 00 To 03

    CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 7.4 Operation of 16-Bit Timer/Event Counters 00 to 03 7.4.1 Interval timer operation Setting 16-bit timer mode control register 0n (TMC0n) and capture/compare control register 0n (CRC0n) as shown in Figure 7-28 allows operation as an interval timer. Setting The basic operation setting procedure is as follows.
  • Page 256 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-30. Control Register Settings for Interval Timer Operation (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 OVF0n TMC0n Clears and starts on match between TM0n and CR00n. (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n0...
  • Page 257 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-31. Interval Timer Configuration Diagram 16-bit timer capture/compare register 00n (CR00n) INTTM00n Note 1 Note 1 Note 2 16-bit timer counter 0n OVF0n Note 1 (TM0n) Noise TI000/P00 eliminator (TI001/P05) Clear TI002/P31 circuit Note 1...

  • Page 258: Ppg Output Operations

    CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 7.4.2 PPG output operations Setting 16-bit timer mode control register 0n (TMC0n) and capture/compare control register 0n (CRC0n) as shown in Figure 7-33 allows operation as PPG (Programmable Pulse Generator) output. Setting The basic operation setting procedure is as follows.
  • Page 259 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-33. Control Register Settings for PPG Output Operation (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 OVF0n TMC0n Clears and starts on match between TM0n and CR00n. (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n0...
  • Page 260 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-34. Configuration Diagram of PPG Output 16-bit timer capture/compare register 00n (CR00n) Note Note Clear 16-bit timer counter 0n Note circuit (TM0n) Noise TI000/P00 eliminator (TI001/P05) TI002/P31 TO00/TI010/P01 Note (TI003/P131) (TO01/TI011/P06) TO02/TI012/P32 Note (TO03/TI013/P132)

  • Page 261: Pulse Width Measurement Operations

    CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 7.4.3 Pulse width measurement operations It is possible to measure the pulse width of the signals input to the TI00n pin and TI01n pin using 16-bit timer counter 0n (TM0n). There are two measurement methods: measuring with TM0n used in free-running mode, and measuring by restarting the timer in synchronization with the edge of the signal input to the TI00n pin.
  • Page 262 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 (1) Pulse width measurement with free-running counter and one capture register When 16-bit timer counter 0n (TM0n) is operated in free-running mode, and the edge specified by prescaler mode register 0n (PRM0n) is input to the TI00n pin, the value of TM0n is taken into 16-bit timer capture/compare register 01n (CR01n) and an external interrupt request signal (INTTM01n) is set.
  • Page 263 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-38. Configuration Diagram for Pulse Width Measurement with Free-Running Counter Note 16-bit timer counter 0n Note OVF0n (TM0n) Note 16-bit timer capture/compare TI00n register 01n (CR01n) INTTM01n Internal bus Note Frequencies without parentheses are for 16-bit timer/event counter 00 and 02, and those in parentheses are for 16-bit timer/event counter 01 and 03.
  • Page 264 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 (2) Measurement of two pulse widths with free-running counter When 16-bit timer counter 0n (TM0n) is operated in free-running mode, it is possible to simultaneously measure the pulse widths of the two signals input to the TI00n pin and the TI01n pin. When the edge specified by bits 4 and 5 (ES0n0 and ES0n1) of prescaler mode register 0n (PRM0n) is input to the TI00n pin, the value of TM0n is taken into 16-bit timer capture/compare register 01n (CR01n) and an interrupt request signal (INTTM01n) is set.
  • Page 265 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-40. Control Register Settings for Measurement of Two Pulse Widths with Free-Running Counter (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 OVF0n TMC0n Free-running mode (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n0...
  • Page 266 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-41. Timing of Pulse Width Measurement Operation with Free-Running Counter (with Both Edges Specified) Count clock 0000H 0001H D0 + 1 D1 + 1 FFFFH 0000H D2 + 1 D2 + 2 TM0n count value TI00n pin input CR01n capture value...
  • Page 267 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 (3) Pulse width measurement with free-running counter and two capture registers When 16-bit timer counter 0n (TM0n) is operated in free-running mode, it is possible to measure the pulse width of the signal input to the TI00n pin. When the rising or falling edge specified by bits 4 and 5 (ES0n0 and ES0n1) of prescaler mode register 0n (PRM0n) is input to the TI00n pin, the value of TM0n is taken into 16-bit timer capture/compare register 01n (CR01n) and an interrupt request signal (INTTM01n) is set.
  • Page 268 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-42. Control Register Settings for Pulse Width Measurement with Free-Running Counter and Two Capture Registers (with Rising Edge Specified) (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 OVF0n TMC0n Free-running mode (b) Capture/compare control register 0n (CRC0n)
  • Page 269 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-43. Timing of Pulse Width Measurement Operation with Free-Running Counter and Two Capture Registers (with Rising Edge Specified) Count clock TM0n count value 0000H 0001H D0 + 1 D1 + 1 FFFFH 0000H D2 + 1...
  • Page 270 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-44. Control Register Settings for Pulse Width Measurement by Means of Restart (with Rising Edge Specified) (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 OVF0n TMC0n Clears and starts at valid edge of TI00n pin. (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1...
  • Page 271 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-45. Timing of Pulse Width Measurement Operation by Means of Restart (with Rising Edge Specified) Count clock 0000H 0001H 0000H 0001H 0000H 0001H TM0n count value TI00n pin input CR01n capture value CR00n capture value INTTM01n D1 ×...

  • Page 272: External Event Counter Operation

    CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 7.4.4 External event counter operation Setting The basic operation setting procedure is as follows. <1> Set the CRC0n register (see Figure 7-46 for the set value). <2> Set the count clock by using the PRM0n register. <3>...
  • Page 273 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-46. Control Register Settings in External Event Counter Mode (with Rising Edge Specified) (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 OVF0n TMC0n Clears and starts on match between TM0n and CR00n. (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1...
  • Page 274 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-47. Configuration Diagram of External Event Counter Internal bus 16-bit timer capture/compare register 00n (CR00n) Match INTTM00n Clear Note Valid edge of TI00n pin Noise eliminator OVF0n 16-bit timer counter 0n (TM0n) Note OVF0n is set to 1 only when CR00n is set to FFFFH.

  • Page 275: Square-Wave Output Operation

    CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 7.4.5 Square-wave output operation Setting The basic operation setting procedure is as follows. <1> Set the count clock by using the PRM0n register. <2> Set the CRC0n register (see Figure 7-49 for the set value). <3>...
  • Page 276 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-49. Control Register Settings in Square-Wave Output Mode (2/2) (c) 16-bit timer output control register 0n (TOC0n) OSPT0n OSPE0n TOC0n4 LVS0n LVR0n TOC0n1 TOE0n TOC0n Enables TO0n output. Inverts output on match between TM0n and CR00n. Specifies initial value of TO0n output F/F (setting “11”...

  • Page 277: One-Shot Pulse Output Operation

    CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 7.4.6 One-shot pulse output operation 16-bit timer/event counter 0n can output a one-shot pulse in synchronization with a software trigger or an external trigger (TI00n pin input). Setting The basic operation setting procedure is as follows. <1>...
  • Page 278 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 (1) One-shot pulse output with software trigger A one-shot pulse can be output from the TO0n pin by setting 16-bit timer mode control register 0n (TMC0n), capture/compare control register 0n (CRC0n), and 16-bit timer output control register 0n (TOC0n) as shown in Figure 7-49, and by setting bit 6 (OSPT0n) of the TOC0n register to 1 by software.
  • Page 279 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-51. Control Register Settings for One-Shot Pulse Output with Software Trigger (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 OVF0n TMC0n Free-running mode (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n0 CRC0n CR00n as compare register...
  • Page 280 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-52. Timing of One-Shot Pulse Output Operation with Software Trigger Set TMC0n to 04H (TM0n count starts) Count clock TM0n count 0000H 0001H N + 1 0000H N – 1 M – 1 M + 1 M + 2 CR01n set value CR00n set value...
  • Page 281 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-53. Control Register Settings for One-Shot Pulse Output with External Trigger (with Rising Edge Specified) (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 OVF0n TMC0n Clears and starts at valid edge of TI00n pin.
  • Page 282 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Cautions 1. Do not set the CR00n and CR01n registers to 0000H. 2. Only 16-bit timer/event counter 00 can use the One-shot pulse output with external trigger of 78K0/FC2. μ 3. Selecting TI001 and TI011 pins are prohibited at PD78F0881A, 78F0882A, 78F0883A of the 78K0/FC2.

  • Page 283: Special Use Of Tm0N

    CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 7.5 Special Use of TM0n 7.5.1 Rewriting CR01n during TM0n operation In principle, rewriting CR00n and CR01n of the 78K0/Fx2 microcontroller when they are used as compare registers is prohibited while TM0n is operating (TMC0n3 and TMC0n2 = other than 00). However, the value of CR01n can be changed, even while TM0n is operating, using the following procedure if CR01n is used for PPG output and the duty factor is changed (When changing the value of CR01n to a smaller value than the current one, rewrite it immediately after its value matches the value of TM0n.
  • Page 284 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 (2) Setting LVS0n and LVR0n Set LVS0n and LVR0n using the following procedure. Figure 7-55. Example of Flow for Setting LVS0n and LVR0n Bits Setting TOC0n.OSPE0n, TOC0n4, TOC0n1 bits <1> Setting of timer output operation Setting TOC0n.TOE0n Setting...

  • Page 285: Cautions For 16-Bit Timer/Event Counters 00 To 03

    CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 7.6 Cautions for 16-Bit Timer/Event Counters 00 to 03 (1) Restrictions for each channel of 16-bit timer/event counter 0n Table 7-5 shows the restrictions for each channel. Table 7-5. Restrictions for Each Channel of 16-Bit Timer/Event Counter 0n Operation Restriction −...
  • Page 286 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 (4) Timing of holding data by capture register (a) When the valid edge is input to the TI00n/TI01n pin and the reverse phase of the TI00n pin is detected while CR00n/CR01n is read, CR01n performs a capture operation but the read value of CR00n/CR01n is not guaranteed.
  • Page 287 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 (7) Operation of OVF0n flag (a) Setting OVF0n flag (1) The OVF0n flag is set to 1 in the following case, as well as when TM0n overflows. Select the clear & start mode entered upon a match between TM0n and CR00n. ↓...
  • Page 288 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 (9) Capture operation (a) When valid edge of TI00n is specified as count clock When the valid edge of TI00n is specified as the count clock, the capture register for which TI00n is specified as a trigger does not operate correctly.
  • Page 289 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 (12) 16-bit timer/event counter 01 of 78K0/FC2 Since the composition of a timer I/O pin changes with products, the 16-bit timer/event counter 01 has the difference of function in a 16-bir timer/event counter00. The difference in the function by the product is shown below.

  • Page 290: Chapter 8 8-Bit Timer/Event Counters 50 And 51

    CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.1 Functions of 8-Bit Timer/Event Counters 50 and 51 8-bit timer/event counters 50 and 51 are mounted onto all 78K0/Fx2 microcontroller products. 8-bit timer/event counters 50 and 51 have the following functions. •...
  • Page 291 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 8-2. Block Diagram of 8-Bit Timer/Event Counter 51 Internal bus 8-bit timer compare Selector INTTM51 register 51 (CR51) TI51/TO51/P33/INTP4 Note 1 Match 8-bit timer TO51/TI51/ counter 51 (TM51) P33/INTP4 Clear Note 2 Output latch PM33 (P33)

  • Page 292: Configuration Of 8-Bit Timer/Event Counters 50 And 51

    CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.2 Configuration of 8-Bit Timer/Event Counters 50 and 51 8-bit timer/event counters 50 and 51 include the following hardware. Table 8-1. Configuration of 8-Bit Timer/Event Counters 50 and 51 Item Configuration Timer register 8-bit timer counter 5n (TM5n) Register 8-bit timer compare register 5n (CR5n)
  • Page 293 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (2) 8-bit timer compare register 5n (CR5n) CR5n can be read and written by an 8-bit memory manipulation instruction. Except in PWM mode, the value set in CR5n is constantly compared with the 8-bit timer counter 5n (TM5n) count value, and an interrupt request (INTTM5n) is generated if they match.

  • Page 294: Registers Controlling 8-Bit Timer/Event Counters 50 And 51

    CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.3 Registers Controlling 8-Bit Timer/Event Counters 50 and 51 The following four registers are used to control 8-bit timer/event counters 50 and 51. • Timer clock selection register 5n (TCL5n) • 8-bit timer mode control register 5n (TMC5n) •...
  • Page 295 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (1) Timer clock selection register 5n (TCL5n) This register sets the count clock of 8-bit timer/event counter 5n and the valid edge of the TI5n pin input. TCL5n can be set by an 8-bit memory manipulation instruction. Reset signal generation clears TCL5n to 00H.
  • Page 296 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 8-6. Format of Timer Clock Selection Register 51 (TCL51) Address: FF8CH After reset: 00H Symbol TCL51 TCL512 TCL511 TCL510 Note 1 TCL512 TCL511 TCL510 Count clock selection = 10 = 20 TI51 pin falling edge TI51 pin rising edge Note 2...
  • Page 297 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (2) 8-bit timer mode control register 5n (TMC5n) TMC5n is a register that performs the following five types of settings. <1> 8-bit timer counter 5n (TM5n) count operation control <2> 8-bit timer counter 5n (TM5n) operating mode selection <3>...
  • Page 298 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 8-8. Format of 8-Bit Timer Mode Control Register 51 (TMC51) Note Address: FF43H After reset: 00H Symbol <7> <3> <2> <0> TMC51 TCE51 TMC516 LVS51 LVR51 TMC511 TOE51 TCE51 TM51 count operation control After clearing to 0, count operation disabled (counter stopped) Count operation start TMC516...
  • Page 299 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (3) Port mode registers 1 and 3 (PM1, PM3) These registers set port 1 and 3 input/output in 1-bit units. When using the P17/TO50/TI50 and P33/TO51/TI51/INTP4 pins for timer output, clear PM17 and PM33 and the output latches of P17 and P33 to 0.

  • Page 300: Operations Of 8-Bit Timer/Event Counters 50 And 51

    CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.4 Operations of 8-Bit Timer/Event Counters 50 and 51 8.4.1 Operation as interval timer 8-bit timer/event counter 5n operates as an interval timer that generates interrupt requests repeatedly at intervals of the count value preset to 8-bit timer compare register 5n (CR5n). When the count value of 8-bit timer counter 5n (TM5n) matches the value set to CR5n, counting continues with the TM5n value cleared to 0 and an interrupt request signal (INTTM5n) is generated.
  • Page 301 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 8-11. Interval Timer Operation Timing (2/2) (b) When CR5n = 00H Count clock TM5n CR5n TCE5n INTTM5n Interval time (c) When CR5n = FFH Count clock TM5n CR5n TCE5n INTTM5n Interrupt acknowledged Interrupt acknowledged Interval time...

  • Page 302: Operation As External Event Counter

    CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.4.2 Operation as external event counter The external event counter counts the number of external clock pulses to be input to the TI5n pin by 8-bit timer counter 5n (TM5n). TM5n is incremented each time the valid edge specified by timer clock selection register 5n (TCL5n) is input. Either the rising or falling edge can be selected.

  • Page 303: Square-Wave Output Operation

    CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.4.3 Square-wave output operation A square wave with any selected frequency is output at intervals determined by the value preset to 8-bit timer compare register 5n (CR5n). The TO5n pin output status is inverted at intervals determined by the count value preset to CR5n by setting bit 0 (TOE5n) of 8-bit timer mode control register 5n (TMC5n) to 1.

  • Page 304: Pwm Output Operation

    CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 8-13. Square-Wave Output Operation Timing Count clock N − 1 N − 1 TM5n count value Count start CR5n Note TO5n Note The initial value of TO5n output can be set by bits 2 and 3 (LVR5n, LVS5n) of 8-bit timer mode control register 5n (TMC5n).
  • Page 305 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (1) PWM output basic operation Setting <1> Set each register. Note Note • Clear the port output latch (P17 or P33) and port mode register (PM17 or PM33) to 0. • TCL5n: Select the count clock. •...
  • Page 306 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 8-14. PWM Output Operation Timing (a) Basic operation (active level = H) Count clock TM5n 00H 01H FFH 00H 01H 02H N N + 1 FFH 00H 01H 02H CR5n TCE5n INTTM5n TO5n <5>...
  • Page 307 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (2) Operation with CR5n changed Figure 8-15. Timing of Operation with CR5n Changed (a) CR5n value is changed from N to M before clock rising edge of FFH → Value is transferred to CR5n at overflow immediately after change. Count clock TM5n N N + 1 N + 2...

  • Page 308: Cautions For 8-Bit Timer/Event Counters 50 And 51

    CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.5 Cautions for 8-Bit Timer/Event Counters 50 and 51 (1) Timer start error An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is because 8-bit timer counters 50 and 51 (TM50, TM51) are started asynchronously to the count clock.

  • Page 309: Chapter 9 8-Bit Timers H0 And H1

    CHAPTER 9 8-BIT TIMERS H0 AND H1 9.1 Functions of 8-Bit Timers H0 and H1 8-bit timers H0 and H1 are mounted onto all 78K0/Fx2 microcontroller products. 8-bit timers H0 and H1 have the following functions. • Interval timer • PWM output mode •...
  • Page 310 Figure 9-1. Block Diagram of 8-Bit Timer H0 Internal bus 8-bit timer H mode register 0 (TMHMD0) TMHE0 CKS02 CKS01 CKS00 TMMD01 TMMD00 TOLEV0 TOEN0 8-bit timer H 8-bit timer H compare register compare register 10 (CMP10) 00 (CMP00) Decoder TOH0/P15 Selector Output latch...
  • Page 311 Figure 9-2. Block Diagram of 8-Bit Timer H1 Internal bus 8-bit timer H mode 8-bit timer H carrier register 1 (TMHMD1) control register 1 (TMCYC1) TMHE1 CKS12 CKS11 CKS10 TMMD11 TMMD10 TOLEV1 TOEN1 8-bit timer H 8-bit timer H RMC1 NRZB1 NRZ1 compare compare register 1 1...
  • Page 312 CHAPTER 9 8-BIT TIMERS H0 AND H1 (1) 8-bit timer H compare register 0n (CMP0n) This register can be read or written by an 8-bit memory manipulation instruction. This register is used in all of the timer operation modes. This register constantly compares the value set to CMP0n with the count value of the 8-bit timer counter Hn and, when the two values match, generates an interrupt request signal (INTTMHn) and inverts the output level of TOHn.

  • Page 313: Registers Controlling 8-Bit Timers H0 And H1

    CHAPTER 9 8-BIT TIMERS H0 AND H1 9.3 Registers Controlling 8-Bit Timers H0 and H1 The following four registers are used to control 8-bit timers H0 and H1. • 8-bit timer H mode register n (TMHMDn) Note • 8-bit timer H carrier control register 1 (TMCYC1) •...
  • Page 314 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-5. Format of 8-Bit Timer H Mode Register 0 (TMHMD0) Address: FF69H After reset: 00H Symbol <7> <1> <0> TMHMD0 TMHE0 CKS02 CKS01 CKS00 TMMD01 TMMD00 TOLEV0 TOEN0 TMHE0 Timer operation enable Stops timer count operation (Counter is cleared to 0) Enables timer count operation (Count operation started by inputting clock) Note 1...
  • Page 315 CHAPTER 9 8-BIT TIMERS H0 AND H1 Notes 2. If the peripheral hardware clock (f ) operates on the internal high-speed oscillation clock (f ) (XSEL = 0), when 1.8 V ≤ V < 2.7 V, the setting of CKS02 = CKS01 = CKS00 = 0 (count clock: f ) is prohibited.
  • Page 316 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-6. Format of 8-Bit Timer H Mode Register 1 (TMHMD1) Address: FFFAH After reset: 00H Symbol <7> <1> <0> TMHMD1 TMHE1 CKS12 CKS11 CKS10 TMMD11 TMMD10 TOLEV1 TOEN1 TMHE1 Timer operation enable Stops timer count operation (Counter is cleared to 0) Enables timer count operation (Count operation started by inputting clock) Note 1...
  • Page 317 CHAPTER 9 8-BIT TIMERS H0 AND H1 Notes 2. If the peripheral hardware clock (f ) operates on the internal high-speed oscillation clock (f ) (XSEL = 0), when 1.8 V ≤ V < 2.7 V, the setting of CKS12 = CKS11 = CKS10 = 0 (count clock: f ) is prohibited.
  • Page 318 CHAPTER 9 8-BIT TIMERS H0 AND H1 (3) Port mode register 1 (PM1) This register sets port 1 input/output in 1-bit units. When using the P15/TOH0 and P16/TOH1/INTP5 pins for timer output, clear PM15 and PM16 and the output latches of P15 and P16 to 0. PM1 can be set by a 1-bit or 8-bit memory manipulation instruction.

  • Page 319: Operation Of 8-Bit Timers H0 And H1

    CHAPTER 9 8-BIT TIMERS H0 AND H1 9.4 Operation of 8-Bit Timers H0 and H1 9.4.1 Operation as interval timer/square-wave output When 8-bit timer counter Hn and compare register 0n (CMP0n) match, an interrupt request signal (INTTMHn) is generated and 8-bit timer counter Hn is cleared to 00H. Compare register 1n (CMP1n) is not used in interval timer mode.
  • Page 320 CHAPTER 9 8-BIT TIMERS H0 AND H1 (2) Timing chart The timing of the interval timer/square-wave output operation is shown below. Figure 9-10. Timing of Interval Timer/Square-Wave Output Operation (1/2) (a) Basic operation Count clock Count start 01H 00H 8-bit timer counter Hn Clear Clear CMP0n...
  • Page 321 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-10. Timing of Interval Timer/Square-Wave Output Operation (2/2) (b) Operation when CMP0n = FFH Count clock Count start 8-bit timer counter Hn Clear Clear CMP0n TMHEn INTTMHn TOHn Interval time (c) Operation when CMP0n = 00H Count clock Count start 8-bit timer counter Hn...

  • Page 322: Operation As Pwm Output Mode

    CHAPTER 9 8-BIT TIMERS H0 AND H1 9.4.2 Operation as PWM output mode In PWM output mode, a pulse with an arbitrary duty and arbitrary cycle can be output. 8-bit timer compare register 0n (CMP0n) controls the cycle of timer output (TOHn). Rewriting the CMP0n register during timer operation is prohibited.
  • Page 323 CHAPTER 9 8-BIT TIMERS H0 AND H1 <2> The count operation starts when TMHEn = 1. <3> The CMP0n register is the compare register that is to be compared first after counter operation is enabled. When the values of 8-bit timer counter Hn and the CMP0n register match, 8-bit timer counter Hn is cleared, an interrupt request signal (INTTMHn) is generated, and TOHn output becomes active.
  • Page 324 CHAPTER 9 8-BIT TIMERS H0 AND H1 (2) Timing chart The operation timing in PWM output mode is shown below. Caution Make sure that the CMP1n register setting value (M) and CMP0n register setting value (N) are within the following range. 00H ≤...
  • Page 325 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-12. Operation Timing in PWM Output Mode (2/4) (b) Operation when CMP0n = FFH, CMP1n = 00H Count clock 8-bit timer counter Hn 00H 01H FFH 00H 01H 02H FFH 00H 01H 02H FFH 00H CMP0n CMP1n...
  • Page 326 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-12. Operation Timing in PWM Output Mode (3/4) (d) Operation when CMP0n = 01H, CMP1n = 00H Count clock 01H 00H 01H 00H 00H 01H 00H 01H 8-bit timer counter Hn CMP0n CMP1n TMHEn INTTMHn...
  • Page 327 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-12. Operation Timing in PWM Output Mode (4/4) (e) Operation by changing CMP1n (CMP1n = 01H → 03H, CMP0n = A5H) Count clock 8-bit timer counter Hn 00H 01H 02H A5H 00H 01H 02H 03H A5H 00H 01H 02H 03H A5H 00H CMP0n...

  • Page 328: Carrier Generator Mode Operation (8-Bit Timer H1 Only)

    CHAPTER 9 8-BIT TIMERS H0 AND H1 9.4.3 Carrier generator mode operation (8-bit timer H1 only) The carrier clock generated by 8-bit timer H1 is output in the cycle set by 8-bit timer/event counter 51. In carrier generator mode, the output of the 8-bit timer H1 carrier pulse is controlled by 8-bit timer/event counter 51, and the carrier pulse is output from the TOH1 output.
  • Page 329 CHAPTER 9 8-BIT TIMERS H0 AND H1 To control the carrier pulse output during a count operation, the NRZ1 and NRZB1 bits of the TMCYC1 register have a master and slave bit configuration. The NRZ1 bit is read-only but the NRZB1 bit can be read and written. The INTTM51 signal is synchronized with the 8-bit timer H1 count clock and output as the INTTM5H1 signal.
  • Page 330 CHAPTER 9 8-BIT TIMERS H0 AND H1 (3) Usage Outputs an arbitrary carrier clock from the TOH1 pin. <1> Set each register. Figure 9-14. Register Setting in Carrier Generator Mode Setting 8-bit timer H mode register 1 (TMHMD1) TMHE1 CKS12 CKS11 CKS10 TMMD11...
  • Page 331 CHAPTER 9 8-BIT TIMERS H0 AND H1 If the setting value of the CMP01 register is N, the setting value of the CMP11 register is M, and the count clock frequency is f , the carrier clock output cycle and duty are as follows. Carrier clock output cycle = (N + M + 2)/f Duty = High-level width : Carrier clock output width = ( M + 1) : (N + M + 2) Cautions 1.
  • Page 332 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-15. Carrier Generator Mode Operation Timing (1/3) (a) Operation when CMP01 = N, CMP11 = N 8-bit timer Hn count clock 8-bit timer counter N 00H N 00H N 00H N 00H N 00H Hn count value CMPn0...
  • Page 333 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-15. Carrier Generator Mode Operation Timing (2/3) (b) Operation when CMP01 = N, CMP11 = M 8-bit timer Hn count clock 8-bit timer counter N 00H 01H M 00H N 00H 01H M 00H Hn count value CMPn0...
  • Page 334 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-15. Carrier Generator Mode Operation Timing (3/3) (c) Operation when CMP11 is changed 8-bit timer H1 count clock 8-bit timer counter 00H 01H 00H 01H H1 count value CMP01 <3> <3>’ CMP11 M (L) TMHE1 INTTMH1...

  • Page 335: Chapter 10 Watch Timer

    CHAPTER 10 WATCH TIMER 10.1 Functions of Watch Timer Watch timer is mounted onto all 78K0/Fx2 microcontroller products. The watch timer has the following functions. • Watch timer • Interval timer The watch timer and the interval timer can be used simultaneously. Figure 10-1 shows the watch timer block diagram.

  • Page 336: Configuration Of Watch Timer

    CHAPTER 10 WATCH TIMER (1) Watch timer When the high-speed system clock or subsystem clock is used, interrupt requests (INTWT) are generated at preset intervals. Table 10-1. Watch Timer Interrupt Time Interrupt Time When Operated at When Operated at When Operated at When Operated at When Operated at = 32.768 kHz...

  • Page 337: Register Controlling Watch Timer

    CHAPTER 10 WATCH TIMER 10.3 Register Controlling Watch Timer The watch timer is controlled by the watch timer operation mode register (WTM). • Watch timer operation mode register (WTM) This register sets the watch timer count clock, enables/disables operation, prescaler interval time, and 5-bit counter operation control.
  • Page 338 CHAPTER 10 WATCH TIMER Figure 10-2. Format of Watch Timer Operation Mode Register (WTM) Address: FF8FH After reset: 00H Symbol <1> <0> WTM7 WTM6 WTM5 WTM4 WTM3 WTM2 WTM1 WTM0 Note WTM7 Watch timer count clock selection (f = 32.768 kHz = 4 MHz = 8 MHz = 10 MHz...

  • Page 339: Watch Timer Operations

    CHAPTER 10 WATCH TIMER 10.4 Watch Timer Operations 10.4.1 Watch timer operation The watch timer generates an interrupt request (INTWT) at a specific time interval by using the peripheral hardware clock or subsystem clock. When bit 0 (WTM0) and bit 1 (WTM1) of the watch timer operation mode register (WTM) are set to 1, the count operation starts.

  • Page 340: Interval Timer Operation

    CHAPTER 10 WATCH TIMER 10.4.2 Interval timer operation The watch timer operates as interval timer which generates interrupt requests (INTWTI) repeatedly at an interval of the preset count value. The interval time can be selected with bits 4 to 6 (WTM4 to WTM6) of the watch timer operation mode register (WTM).

  • Page 341: Cautions For Watch Timer

    CHAPTER 10 WATCH TIMER 10.5 Cautions for Watch Timer When operation of the watch timer and 5-bit counter is enabled by the watch timer mode control register (WTM) (by setting bits 0 (WTM0) and 1 (WTM1) of WTM to 1), the interval until the first interrupt request (INTWT) is generated after the register is set does not exactly match the specification made with bits 2 and 3 (WTM2, WTM3) of WTM.

  • Page 342: Chapter 11 Watchdog Timer

    CHAPTER 11 WATCHDOG TIMER 11.1 Functions of Watchdog Timer The watchdog timer is mounted onto all 78K0/Fx2 microcontroller products. The watchdog timer operates on the internal low-speed oscillation clock. The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset signal is generated.

  • Page 343: Configuration Of Watchdog Timer

    CHAPTER 11 WATCHDOG TIMER 11.2 Configuration of Watchdog Timer The watchdog timer includes the following hardware. Table 11-1. Configuration of Watchdog Timer Item Configuration Control register Watchdog timer enable register (WDTE) How the counter operation is controlled, overflow time, and window open period are set by the option byte. Table 11-2.

  • Page 344: Register Controlling Watchdog Timer

    CHAPTER 11 WATCHDOG TIMER 11.3 Register Controlling Watchdog Timer The watchdog timer is controlled by the watchdog timer enable register (WDTE). (1) Watchdog timer enable register (WDTE) Writing ACH to WDTE clears the watchdog timer counter and starts counting again. This register can be set by an 8-bit memory manipulation instruction.

  • Page 345: Operation Of Watchdog Timer

    CHAPTER 11 WATCHDOG TIMER 11.4 Operation of Watchdog Timer 11.4.1 Controlling operation of watchdog timer 1. When the watchdog timer is used, its operation is specified by the option byte (0080H). • Enable counting operation of the watchdog timer by setting bit 4 (WDTON) of the option byte (0080H) to 1 (the counter starts operating after a reset release) (for details, see CHAPTER 23).
  • Page 346 CHAPTER 11 WATCHDOG TIMER Cautions 4. The operation of the watchdog timer in the HALT and STOP modes differs as follows depending on the set value of bit 0 (LSROSC) of the option byte. LSROSC = 0 (Internal Low-Speed LSROSC = 1 (Internal Low-Speed Oscillator Can Be Stopped by Software) Oscillator Cannot Be Stopped) In HALT mode...

  • Page 347: Setting Overflow Time Of Watchdog Timer

    CHAPTER 11 WATCHDOG TIMER 11.4.2 Setting overflow time of watchdog timer Set the overflow time of the watchdog timer by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte (0080H). If an overflow occurs, an internal reset signal is generated. If “ACH” is written to WDTE during the window open period before the overflow time, the present count is cleared and the watchdog timer starts counting again.

  • Page 348: Setting Window Open Period Of Watchdog Timer

    CHAPTER 11 WATCHDOG TIMER 11.4.3 Setting window open period of watchdog timer Set the window open period of the watchdog timer by using bits 6 and 5 (WINDOW1, WINDOW0) of the option byte (0080H). The outline of the window is as follows. •...
  • Page 349 CHAPTER 11 WATCHDOG TIMER Remark If the overflow time is set to 2 , the window close time and open time are as follows. (when 2.7 V ≤ V ≤ 5.5 V) Setting of Window Open Period 100% Window close time 0 to 7.11 ms 0 to 4.74 ms 0 to 2.37 ms...

  • Page 350: Chapter 12 Clock Output/Buzzer Output Controller

    CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 12.1 Functions of Clock Output/Buzzer Output Controller The watchdog timer is mounted onto all 78K0/Fx2 microcontroller products. The clock output controller is intended for carrier output during remote controlled transmission and clock output for supply to peripheral LSIs.

  • Page 351: Configuration Of Clock Output/Buzzer Output Controller

    CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 12.2 Configuration of Clock Output/Buzzer Output Controller The clock output/buzzer output controller includes the following hardware. Table 12-1. Clock Output/Buzzer Output Controller Configuration Item Configuration Control registers Clock output selection register (CKS) Port mode register 7 (PM7) Port register 7 (P7) 12.3 Register Controlling Clock Output/Buzzer Output Controller The following two registers are used to control the clock output/buzzer output controller.
  • Page 352 CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER Figure 12-2. Format of Clock Output Selection Register (CKS) Address: FF40H After reset: 00H Symbol <7> <4> BZOE BCS1 BCS0 CLOE CCS3 CCS2 CCS1 CCS0 BZOE BUZ output enable/disable specification Clock division circuit operation stopped. BUZ fixed to low level. Clock division circuit operation enabled.
  • Page 353 CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER Notes 2. If the peripheral hardware clock operates on the internal high-speed oscillation clock when 1.8 V ≤ V < 2.7 V, setting CCS3 = CCS2 = CCS1 = CCS0 = 0 (output clock of PCL: f ) is prohibited.

  • Page 354: Clock Output/Buzzer Output Controller Operations

    CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 12.4 Clock Output/Buzzer Output Controller Operations 12.4.1 Clock output operation The clock pulse is output as the following procedure. <1> Select the clock pulse output frequency with bits 0 to 3 (CCS0 to CCS3) of the clock output selection register (CKS) (clock pulse output in disabled status).

  • Page 355: Chapter 13 A/D Converter

    CHAPTER 13 A/D CONVERTER 78K0/FC2 78K0/FE2 78K0/FF2 μ μ μ PD78F088yA, 78F089zA) PD78F088yA, 78F0890A) PD78F089yA) y = 1 to 3 y = 4 to 6, z = 4, 5 y = 7 to 9 y = 1 to 3 10-bit A/D converter 8 ch 9 ch 12 ch...

  • Page 356: Configuration Of A/D Converter

    CHAPTER 13 A/D CONVERTER 13.2 Configuration of A/D Converter The A/D converter includes the following hardware. (1) ANI0 to ANI15 pins These are the analog input pins of the 16-channel A/D converter. They input analog signals to be converted into digital signals.
  • Page 357 CHAPTER 13 A/D CONVERTER (7) 8-bit A/D conversion result register (ADCRH) The A/D conversion result is loaded from the successive approximation register to this register each time A/D conversion is completed, and the ADCRH register stores the higher 8 bits of the A/D conversion result. Caution When data is read from ADCR and ADCRH, a wait cycle is generated.

  • Page 358: Registers Used In A/D Converter

    CHAPTER 13 A/D CONVERTER 13.3 Registers Used in A/D Converter The A/D converter uses the following seven registers. • A/D converter mode register (ADM) • A/D port configuration register (ADPC) • Analog input channel specification register (ADS) • Port mode register 8 (PM8) •...
  • Page 359 CHAPTER 13 A/D CONVERTER Table 13-1. Settings of ADCS and ADCE ADCS ADCE A/D Conversion Operation Stop status (DC power consumption path does not exist) Conversion waiting mode (comparator operation, only comparator consumes power) Note Conversion mode (comparator operation stopped Conversion mode (comparator operation) Note Ignore data of the first conversion because it is not guaranteed range.
  • Page 360 CHAPTER 13 A/D CONVERTER Table 13-2. A/D Conversion Time Selection (1) 2.7 V ≤ AV ≤ 5.5 V (LV0 = 0) A/D Converter Mode Register (ADM) Conversion Time Selection Conversion Clock = 4 MHz = 10 MHz = 20 MHz μ...
  • Page 361 CHAPTER 13 A/D CONVERTER Figure 13-5. A/D Converter Sampling and A/D Conversion Timing ← ADCS 1 or ADS rewrite ADCS Sampling timing INTAD Wait Sampling time Successive Sampling time Transfer Note period clear conversion time to ADCR, clear INTAD generation Conversion time Conversion time Note For details of wait period, see CHAPTER 31 CAUTIONS FOR WAIT.
  • Page 362 CHAPTER 13 A/D CONVERTER (3) 8-bit A/D conversion result register (ADCRH) This register is an 8-bit register that stores the A/D conversion result. The higher 8 bits of 10-bit resolution are stored. ADCRH can be read by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
  • Page 363 CHAPTER 13 A/D CONVERTER (4) Analog input channel specification register (ADS) This register specifies the input port of the analog voltage to be A/D converted. ADS can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 13-8.
  • Page 364 CHAPTER 13 A/D CONVERTER (5) A/D port configuration register (ADPC) This register switches the P80/ANI0 to P87/ANI7, P90/ANI8 to P97/ANI15 pins to analog input of A/D converter or digital I/O of port. ADPC can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
  • Page 365 CHAPTER 13 A/D CONVERTER Figure 13-9. Format of A/D Port Configuration Register (ADPC) Address: FF22H After reset: 00H Symbol ADPC ADPC4 ADPC3 ADPC2 ADPC1 ADPC0 Analog input (A)/ digital input (D) switching P97/ P96/ P95/ P94/ P93/ P92/ P91/ P90/ P87/ P86/ P85/...
  • Page 366 CHAPTER 13 A/D CONVERTER (6) Port mode register 8 (PM8) When using the P80/ANI0 to P87/ANI7 pins for analog input port, set PM80 to PM87 to 1. The output latches of P80 to P87 at this time may be 0 or 1. If PM80 to PM87 are set to 0, they cannot be used as analog input port pins.
  • Page 367 CHAPTER 13 A/D CONVERTER P80/ANI0 to P87/ANI7, P90/ANI8 to P97/ANI15 pins are as shown below depending on the settings of ADPC, ADS, PM8 and PM9. Table 13-3. Setting Functions of P80/ANI0 to P87/ANI7, P90/ANI8 to P97/ANI15 Pins ADPC PM8, PM9 P80/ANI0 to P87/ANI7, P90/ANI8 to P97/ANI15 Pins Analog input selection...

  • Page 368: A/D Converter Operations

    CHAPTER 13 A/D CONVERTER 13.4 A/D Converter Operations 13.4.1 Basic operations of A/D converter <1> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1 to start the operation of the comparator. <2> Set channels for A/D conversion to analog input by using the A/D port configuration register (ADPC) and set to input mode by using port mode register 8, 9 (PM8, PM9).
  • Page 369 CHAPTER 13 A/D CONVERTER Figure 13-12. Basic Operation of A/D Converter Conversion time Sampling time A/D converter Sampling A/D conversion operation Conversion Undefined result Conversion ADCR result INTAD A/D conversion operations are performed continuously until bit 7 (ADCS) of the A/D converter mode register (ADM) is reset (0) by software.

  • Page 370: Input Voltage And Conversion Results

    CHAPTER 13 A/D CONVERTER 13.4.2 Input voltage and conversion results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI15) and the theoretical A/D conversion result (stored in the 10-bit A/D conversion result register (ADCR)) is shown by the following expression.
  • Page 371 CHAPTER 13 A/D CONVERTER Figure 13-13 shows the relationship between the analog input voltage and the A/D conversion result. Figure 13-13. Relationship Between Analog Input Voltage and A/D Conversion Result ADCR 1023 FFC0H 1022 FF80H 1021 FF40H A/D conversion result (ADCR) 00C0H 0080H...

  • Page 372: A/D Converter Operation Mode

    CHAPTER 13 A/D CONVERTER 13.4.3 A/D converter operation mode The operation mode of the A/D converter is the select mode. One channel of analog input is selected from ANI0 to ANI15 by the analog input channel specification register (ADS) and A/D conversion is executed. Remark ANI0 to ANI7 pins: 44-pin products of 78K0/FC2 ANI0 to ANI8 pins: 48-pin products of 78K0/FC2 ANI0 to ANI11 pins: 78K0/FE2...
  • Page 373 CHAPTER 13 A/D CONVERTER The setting methods are described below. <1> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1. <2> Set the channel to be used in the analog input mode by using bits 4 to 0 (ADPC4 to ADPC0) of the A/D port configuration register (ADPC) and bits 7 to 0 (PM87 to PM80) of port mode register 8 (PM8), bits 7 to 0 (PM97 to PM90) of port mode register 9 (PM9).

  • Page 374: How To Read A/D Converter Characteristics Table

    CHAPTER 13 A/D CONVERTER 13.5 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1LSB (Least Significant Bit).
  • Page 375 CHAPTER 13 A/D CONVERTER (5) Full-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (Full-scale − 3/2LSB) when the digital output changes from 1..110 to 1..111. (6) Integral linearity error This shows the degree to which the conversion characteristics deviate from the ideal linear relationship.

  • Page 376: Cautions For A/D Converter

    CHAPTER 13 A/D CONVERTER 13.6 Cautions for A/D Converter (1) Operating current in STOP mode The A/D converter stops operating in the STOP mode. At this time, the operating current can be reduced by clearing bit 7 (ADCS) and bit 0 (ADCE) of the A/D converter mode register (ADM) to 0. To restart from the standby status, clear bit 6 (ADIF) of interrupt request flag register 1L (IF1L) to 0 and start operation.
  • Page 377 CHAPTER 13 A/D CONVERTER Figure 13-21. Analog Input Pin Connection If there is a possibility that noise equal to or higher than AV equal to or lower than AV may enter, clamp with a diode with a small V value (0.3 V or lower). Reference voltage input...
  • Page 378 CHAPTER 13 A/D CONVERTER (8) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is changed. Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF for the pre-change analog input may be set just before the ADS rewrite.
  • Page 379 CHAPTER 13 A/D CONVERTER (11) Internal equivalent circuit The equivalent circuit of the analog input block is shown below. Figure 13-23. Internal Equivalent Circuit of ANIn Pin ANIn Table 13-4. Resistance and Capacitance Values of Equivalent Circuit (Reference Values) 4.0 V ≤ AV ≤...

  • Page 380: Chapter 14 Serial Interfaces Uart60 And Uart61

    CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 14.1 Functions of Serial Interfaces UART60 and UART61 The serial interfaces UART60 and UART61 is mounted onto all 78K0/Fx2 microcontroller products. Serial interfaces UART60 and UART61 have the following two modes. (1) Operation stop mode This mode is used when serial communication is not executed and can enable a reduction in the power consumption.
  • Page 381 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 Cautions 6. If data is continuously transmitted, the communication timing from the stop bit to the next start bit is extended two operating clocks of the macro. However, this does not affect the result of communication because the reception side initializes the timing when it has detected a start bit.
  • Page 382 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 Figure 14-2. LIN Reception Operation Wakeup Sync Sync Identifer Data field Data field Checksum signal frame break field field field field LIN bus 13-bit Data Data Data SBF reception reception reception reception reception reception <2>...
  • Page 383 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 Figure 14-3 to 14-5 show the port configuration for LIN reception operation. The wakeup signal transmitted from the LIN master is received by detecting the edge of the external interrupt (INTP0 and INTP1). The length of the sync field transmitted from the LIN master can be measured using the external event capture operation of 16-bit timer/event counter 00, 01, and the baud rate error can be calculated.
  • Page 384 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 Figure 13-4. Port Configuration for LIN Reception Operation: 78K0/FC2 (UART61) Selector P11/RxD61 RxD61 input Port mode (PM11) Output latch (P11) Selector Selector P30/INTP1 INTP1 input Port mode Port input (PM30) switch control Output latch4 (ISC4) (P30) <ISC4>...
  • Page 385 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 Figure 14-5. Port Configuration for LIN Reception Operation: 78K0/FE2, 78K0/FF2 (UART61) Selector P11/RxD61 RxD61 input Port mode (PM11) Output latch (P11) Selector Selector P05/TI001 TI001 input Port mode Port input (PM05) switch control Output latch (ISC2) (P05)

  • Page 386: Configurations Of Serial Interface Uart60 And Uart61

    CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 14.2 Configurations of Serial Interface UART60 and UART61 Serial interfaces UART60 and UART61 include the following hardware. Table 14-1. Configurations of Serial Interface UART60 and UART61 Item Configuration Registers Receive buffer register 6n (RXB6n) Receive shift register 6n (RXS6n) Transmit buffer register 6n (TXB6n) Transmit shift register 6n (TXS6n)
  • Page 387 Figure 14-6. Block Diagram of Serial Interface UART60 TI010, INTP0 Filter D60/P14 INTSR60 Reception control INTSRE60 Receive shift register 60 (RXS60) Asynchronous serial Asynchronous serial Baud rate Asynchronous serial interface Receive buffer register 60 interface operation mode interface reception error generator control register 60 (ASICL60) (RXB60)
  • Page 388 Figure 14-7. Block Diagram of Serial Interface UART61 Filter D61/P11/SI10 INTSR61 Reception control INTSRE61 Receive shift register 61 (RXS61) Asynchronous serial Asynchronous serial Asynchronous serial interface Baud rate Receive buffer register 61 interface operation mode interface reception error control register 61 (ASICL61) generator (RXB61) register 61 (ASIM61)
  • Page 389 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 (1) Receive buffer register 6n (RXB6n) This 8-bit register stores parallel data converted by receive shift register 6n (RXS6n). Each time 1 byte of data has been received, new receive data is transferred to this register from RXS6n. If the data length is set to 7 bits, data is transferred as follows.

  • Page 390: Registers Controlling Serial Interfaces Uart60 And Uart61

    CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 14.3 Registers Controlling Serial Interfaces UART60 and UART61 Serial interfaces UART60 and UART61 are controlled by the following nine registers. • Asynchronous serial interface operation mode register 6n (ASIM6n) • Asynchronous serial interface reception error status register 6n (ASIS6n) •...
  • Page 391 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 Figure 14-8. Format of Asynchronous Serial Interface Operation Mode Register 60 (ASIM60) (1/2) Address: FF2EH After reset: 01H R/W Symbol <7> <6> <5> ASIM60 POWER60 TXE60 RXE60 PS610 PS600 CL60 SL60 ISRM60 POWER60 Enables/disables operation of internal operation clock Note 1 Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously...
  • Page 392 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 Figure 14-8. Format of Asynchronous Serial Interface Operation Mode Register 60 (ASIM60) (2/2) PS610 PS600 Transmission operation Reception operation Does not output parity bit. Reception without parity Note Outputs 0 parity. Reception as 0 parity Outputs odd parity.
  • Page 393 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 Figure 14-9. Format of Asynchronous Serial Interface Operation Mode Register 61 (ASIM61) (1/2) Address: FF2FH After reset: 01H R/W Symbol <7> <6> <5> ASIM61 POWER61 TXE61 RXE61 PS611 PS601 CL61 SL61 ISRM61 POWER61 Enables/disables operation of internal operation clock Note 1 Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously...
  • Page 394 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 Figure 14-9. Format of Asynchronous Serial Interface Operation Mode Register 61 (ASIM61) (2/2) PS611 PS601 Transmission operation Reception operation Does not output parity bit. Reception without parity Note Outputs 0 parity. Reception as 0 parity Outputs odd parity.
  • Page 395 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 (2) Asynchronous serial interface reception error status register 6n (ASIS6n) This register indicates an error status on completion of reception by serial interfaces UART60 and UART61. It includes three error flag bits (PE6n, FE6n, OVE6n). This register is read-only by an 8-bit memory manipulation instruction.
  • Page 396 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 Figure 14-11. Format of Asynchronous Serial Interface Reception Error Status Register 61 (ASIS61) Address: FF2FH After reset: 00H R Symbol ASIS61 PE61 FE61 OVE61 PE61 Status flag indicating parity error If POWER61 = 0 and RXE61 = 0, or if ASIS61 register is read If the parity of transmit data does not match the parity bit on completion of reception FE61 Status flag indicating framing error...
  • Page 397 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 (3) Asynchronous serial interface transmission status register 6n (ASIF6n) This register indicates the status of transmission by serial interfaces UART60 and UART61. It includes two status flag bits (TXBF6n and TXSF6n). Transmission can be continued without disruption even during an interrupt period, by writing the next data to the TXB6n register after data has been transferred from the TXB6n register to the TXS6n register.
  • Page 398 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 Figure 14-13. Format of Asynchronous Serial Interface Transmission Status Register 61 (ASIF61) Address: FF38H After reset: 00H R Symbol ASIF61 TXBF61 TXSF61 TXBF61 Transmit buffer data flag If POWER61 = 0 or TXE61 = 0, or if data is transferred to transmit shift register 61 (TXS61) If data is written to transmit buffer register 61 (TXB61) (if data exists in TXB61) TXSF61 Transmit shift register data flag...
  • Page 399 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 (4) Clock selection register 6n (CKSR6n) This register selects the base clocks of serial interface UART60 and UART61. CKSR6n can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H. Remarks 1.
  • Page 400 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 Figure 14-14. Format of Clock Selection Register 60 (CKSR60) Address: FF56H After reset: 00H R/W Symbol CKSR60 TPS630 TPS620 TPS610 TPS600 Note 1 TPS630 TPS620 TPS610 TPS600 Base clock (f ) selection XCLK6 4 MHz 5 MHz 10 MHz...
  • Page 401 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 Figure 14-15. Format of Clock Selection Register 61 (CKSR61) Address: FF39H After reset: 00H R/W Symbol CKSR61 TPS631 TPS621 TPS611 TPS601 Note 1 TPS631 TPS621 TPS611 TPS601 Base clock (f ) selection XCLK6 4 MHz 5 MHz 10 MHz...
  • Page 402 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 (5) Baud rate generator control register 6n (BRGC6n) This register sets the division value of the 8-bit counters of serial interface UART60 and UART61. BRGC6n can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to FFH.
  • Page 403 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 Figure 14-17. Format of Baud Rate Generator Control Register 61 (BRGC61) Address: FF3EH After reset: FFH R/W Symbol BRGC61 MDL671 MDL661 MDL651 MDL641 MDL631 MDL621 MDL611 MDL601 MDL671 MDL661 MDL651 MDL641 MDL631 MDL621 MDL611 MDL601 Output clock selection of 8-bit counter ×...
  • Page 404 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 (6) Asynchronous serial interface control register 6n (ASICL6n) This register controls the serial communication operations of serial interface UART60 and UART61. ASICL6n can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 16H.
  • Page 405 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 Figure 14-18. Format of Asynchronous Serial Interface Control Register 60 (ASICL60) (2/2) SBL620 SBL610 SBL600 SBF transmission output width control SBF is output with 13-bit length. SBF is output with 14-bit length. SBF is output with 15-bit length. SBF is output with 16-bit length.
  • Page 406 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 Figure 14-19. Format of Asynchronous Serial Interface Control Register 61 (ASICL61) (1/2) Note Address: FF3FH After reset: 16H R/W Symbol <7> <6> ASICL61 SBRF61 SBRT61 SBTT61 SBL621 SBL611 SBL601 DIR61 TXDLV61 SBRF61 SBF reception status flag If POWER61 = 0 and RXE61 = 0 or if SBF reception has been completed correctly SBF reception in progress SBRT61...
  • Page 407 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 Figure 14-19. Format of Asynchronous Serial Interface Control Register 61 (ASICL61) (2/2) SBL621 SBL611 SBL601 SBF transmission output width control SBF is output with 13-bit length. SBF is output with 14-bit length. SBF is output with 15-bit length. SBF is output with 16-bit length.
  • Page 408 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 (7) Input switch control register (ISC) The input switch control register (ISC) is used to receive a status signal transmitted from the master during LIN (Local Interconnect Network) reception. The input source is switched by setting ISC. This register can be set by a 1-bit or 8-bit memory manipulation instruction.
  • Page 409 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 (8) Port mode register 1 (PM1) This register sets port 1 input/output in 1-bit units. When using the P13/TxD60 and P10/SCK10/TxD61 pins for serial interface data output, clear PM13 and PM10 to 0 and set the output latch of P13 and P10 to 1. When using the P14/RxD60 and P11/SI10/RxD61 in for serial interface data input, set PM14 and PM11 to 1.

  • Page 410: Operations Of Serial Interface Uart60 And Uart61

    CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 14.4 Operations of Serial Interface UART60 and UART61 Serial interfaces UART60 and UART61 have the following two modes. • Operation stop mode • Asynchronous serial interface (UART) mode 14.4.1 Operation stop mode In this mode, serial communication cannot be executed; therefore, the power consumption can be reduced. In addition, the pins can be used as ordinary port pins in this mode.

  • Page 411: Asynchronous Serial Interface (Uart) Mode

    CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 14.4.2 Asynchronous serial interface (UART) mode In this mode, data of 1 byte is transmitted/received following a start bit, and a full-duplex operation can be performed. A dedicated UART baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates.
  • Page 412 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 The relationship between the register settings and pins is shown below. Table 14-2. Relationship Between Register Settings and Pins (a) UART60 POWER6n TXE6n RXE6n PM13 PM14 UART60 Pin Function Operation TxD60/P13 RxD60/P14 Note Note Note Note...
  • Page 413 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 (2) Communication operation (a) Format and waveform example of normal transmit/receive data Figures 14-22 and 14-23 show the format and waveform example of the normal transmit/receive data. Figure 14-22. Format of Normal UART Transmit/Receive Data 1.
  • Page 414 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 Figure 14-23. Example of Normal UART Transmit/Receive Data Waveform 1. Data length: 8 bits, LSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H 1 data frame Start Parity Stop 2. Data length: 8 bits, MSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H 1 data frame Start Parity...
  • Page 415 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 (b) Parity types and operation The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used on both the transmission and reception sides. With even parity and odd parity, a 1-bit (odd number) error can be detected.
  • Page 416 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 (c) Normal transmission When bit 7 (POWER6n) of asynchronous serial interface operation mode register 6n (ASIM6n) is set to 1 and bit 6 (TXE6n) of ASIM6n is then set to 1, transmission is enabled. Transmission can be started by writing transmit data to transmit buffer register 6n (TXB6n).
  • Page 417 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 (d) Continuous transmission The next transmit data can be written to transmit buffer register 6n (TXB6n) as soon as transmit shift register 6 (TXS6n) has started its shift operation. Consequently, even while the INTST6n interrupt is being serviced after transmission of one data frame, data can be continuously transmitted and an efficient communication rate can be realized.
  • Page 418 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 Figure 14-25 shows an example of the continuous transmission processing flow. Figure 14-25. Example of Continuous Transmission Processing Flow Set registers. Write TXB6n. Transfer executed necessary number of times? Read ASIF6n TXBF6n = 0? Write TXB6n.
  • Page 419 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 Figure 14-26 shows the timing of starting continuous transmission, and Figure 14-26 shows the timing of ending continuous transmission. Figure 14-26. Timing of Starting Continuous Transmission Start Data (1) Parity Stop Start Data (2) Parity Stop Start...
  • Page 420 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 Figure 14-27. Timing of Ending Continuous Transmission Data (n − 1) Start Start Parity Data (n) Parity Stop Stop Stop INTST6n Data (n − 1) TXB6n Data (n) Data (n − 1) TXS6n Data (n) TXBF6n TXSF6n...
  • Page 421 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 (e) Normal reception Reception is enabled and the R D6n pins input is sampled when bit 7 (POWER6n) of asynchronous serial interface operation mode register 6n (ASIM6n) is set to 1 and then bit 5 (RXE6n) of ASIM6n is set to 1. The 8-bit counter of the baud rate generator starts counting when the falling edge of the R D6n pins input is detected.
  • Page 422 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 (f) Reception error Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error flag of asynchronous serial interface reception error status register 6n (ASIS6n) is set as a result of data reception, a reception error interrupt request (INTSR6n/INTSRE6n) is generated.
  • Page 423 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 (g) Noise filter of receive data The RXD6n signal’s is sampled with the base clock output by the prescaler block. If two sampled values are the same, the output of the match detector changes, and the data is sampled as input data.
  • Page 424 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 (h) SBF transmission When the device is used in LIN communication operation, the SBF (Synch Break Field) transmission control function is used for transmission. For the transmission operation of LIN, see Figure 14-1 LIN Transmission Operation.
  • Page 425 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 SBF reception When the device is used in LIN communication operation, the SBF (Synch Break Field) reception control function is used for reception. For the reception operation of LIN, see Figure 14-2 LIN Reception Operation.

  • Page 426: Dedicated Baud Rate Generator

    CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 14.4.3 Dedicated baud rate generator The dedicated baud rate generator consists of a source clock selector and an 8-bit programmable counter, and generates a serial clock for transmission/reception of UART60 and UART61. Separate 8-bit counters are provided for transmission and reception. (1) Configuration of baud rate generator •...
  • Page 427 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 Figure 14-33. Configuration of Baud Rate Generator POWER6n Baud rate generator POWER6n, TXE6n (or RXE6n) Selector 8-bit counter XCLK6 Match detector Baud rate 8-bit timer/ event counter 50 output CKSR6n: TPS63n to TPS60n BRGC6n: MDL67n to MDL60n Remark POWER6n: Bit 7 of asynchronous serial interface operation mode register 6n (ASIM6n) TXE6n:...
  • Page 428 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 Cautions 1. Keep the baud rate error during transmission to within the permissible error range at the reception destination. 2. Make sure that the baud rate error during reception satisfies the range shown in (4) Permissible baud rate range during reception.
  • Page 429 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 (4) Permissible baud rate range during reception The permissible error from the baud rate at the transmission destination during reception is shown below. Caution Make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below.
  • Page 430 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 k − 2 21k + 2 Minimum permissible data frame length: FLmin = 11 × FL − × FL = Therefore, the maximum receivable baud rate at the transmission destination is as follows. −...
  • Page 431 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 (5) Data frame length during continuous transmission When data is continuously transmitted, the data frame length from a stop bit to the next start bit is extended by two clocks of base clock from the normal value. However, the result of communication is not affected because the timing is initialized on the reception side when the start bit is detected.

  • Page 432: Chapter 15 Serial Interfaces Csi10 And Csi11

    CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 78K0/FC2 78K0/FE2 78K0/FF2 μ μ μ PD78F088yA, 78F089zA) PD78F088yA, 78F0890A) PD78F089yA) y = 1 to 6, z = 4, 5 y = 7 to 9 y = 1 to 3 Serial interface √ CSI10 −...

  • Page 433: Configuration Of Serial Interfaces Csi10 And Csi11

    CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 15.2 Configuration of Serial Interfaces CSI10 and CSI11 Serial interfaces CSI10 and CSI11 include the following hardware. Table 15-1. Configuration of Serial Interfaces CSI10 and CSI11 Item Configuration Controller Transmit controller Clock start/stop controller & clock phase controller Registers Transmit buffer register 1n (SOTB1n) Serial I/O shift register 1n (SIO1n)
  • Page 434 CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 Figure 15-2. Block Diagram of Serial Interface CSI11 Internal bus Serial I/O shift Transmit buffer Output SI11/P75 register 11 (SIO11) register 11 (SOTB11) SO11/P74 selector Output latch Transmit data Output latch (P74) controller SSI11 PM74 Transmit controller...

  • Page 435: Registers Controlling Serial Interfaces Csi10 And Csi11

    CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 15.3 Registers Controlling Serial Interfaces CSI10 and CSI11 Serial interfaces CSI10 and CSI11 are controlled by the following four registers. • Serial operation mode register 1n (CSIM1n) • Serial clock selection register 1n (CSIC1n) •...
  • Page 436 CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 Figure 15-4. Format of Serial Operation Mode Register 11 (CSIM11) Note 1 Address: FF88H After reset: 00H R/W Symbol <7> CSIM11 CSIE11 TRMD11 SSE11 DIR11 CSOT11 CSIE11 Operation control in 3-wire serial I/O mode Note 2 Note 3 Disables operation...
  • Page 437 CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 (2) Serial clock selection register 1n (CSIC1n) This register specifies the timing of the data transmission/reception and sets the serial clock. CSIC1n can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
  • Page 438 CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 Notes 1. The frequency that can be used for the peripheral hardware clock (f ) differs depending on the power supply voltage and product specifications. Supply Voltage Peripheral Hardware Clock Frequency 4.0 V ≤ V ≤...
  • Page 439 CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 Figure 15-6. Format of Serial Clock Selection Register 11 (CSIC11) Address: FF89H After reset: 00H R/W Symbol CSIC11 CKP11 DAP11 CKS112 CKS111 CKS110 CKP11 DAP11 Specification of data transmission/reception timing Type SCK11 SO11 D7 D6 D5 D4 D3 D2 D1 D0 SI11 input timing SCK11...
  • Page 440 CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 Notes 2. Set the serial clock to satisfy the following conditions. Supply Voltage (A) Grade Products (A2) Grade Products = 4.0 to 5.5 V Serial clock ≤ 5 MHz Serial clock ≤ 5 MHz = 2.7 to 4.0 V Serial clock ≤...
  • Page 441 CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 (3) Port mode registers 0, 1 and 7 (PM0, PM1, PM7) These registers set port 0, 1 and 7 input/output in 1-bit units. When using P10/SCK10 and P76/SCK11 as the clock output pins of the serial interface, clear PM10 and PM76, and the output latches of P10 and P76 to 1.
  • Page 442 CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 Figure 15-9. Format of Port Mode Register 7 (PM7) Address: FF2CH After reset: FFH R/W Symbol PM76 PM75 PM74 PM73 PM72 PM71 PM70 PM7n P7n pin I/O mode selection (n = 0 to 6) Output mode (Output buffer on) Input mode (Output buffer off) Remark The figure shown above presents the format of port mode register 0 of 78K0/FF2 products.

  • Page 443: Operation Of Serial Interfaces Csi10 And Csi11

    CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 15.4 Operation of Serial Interfaces CSI10 and CSI11 Serial interfaces CSI10 and CSI11 can be used in the following two modes. • Operation stop mode • 3-wire serial I/O mode 15.4.1 Operation stop mode Serial communication is not executed in this mode.

  • Page 444: 3-Wire Serial I/O Mode

    CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 15.4.2 3-wire serial I/O mode The 3-wire serial I/O mode is used for connecting peripheral ICs and display controllers with a clocked serial interface. In this mode, communication is executed by using three lines: the serial clock (SCK1n), serial output (SO1n), and serial input (SI1n) lines.
  • Page 445 CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 The relationship between the register settings and pins is shown below. Table 15-2. Relationship Between Register Settings and Pins (1/2) (a) Serial interface CSI10 CSIE10 TRMD10 PM11 PM12 PM10 CSI10 Pin Function Operation SI10/RxD61/ SO10/P12 SCK10/TxD61/ Note 1...
  • Page 446 CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 Table 15-2. Relationship Between Register Settings and Pins (2/2) (b) Serial interface CSI11 CSI11 CSIE11 TRMD11 SSE11 PM75 P75 PM74 P74 PM76 P76 PM05 P05 Pin Function Operation SI11/ SO11/ SCK11/ SSI11/ TI001/P05 Note 1 Note 1 Note 1...
  • Page 447 CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 (2) Communication operation In the 3-wire serial I/O mode, data is transmitted or received in 8-bit units. Each bit of the data is transmitted or received in synchronization with the serial clock. Data can be transmitted or received if bit 6 (TRMD1n) of serial operation mode register 1n (CSIM1n) is 1. Transmission/reception is started when a value is written to transmit buffer register 1n (SOTB1n).
  • Page 448 CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 Figure 15-10. Timing in 3-Wire Serial I/O Mode (1/2) Note (1) Transmission/reception timing (Type 1; TRMD1n = 1, DIR1n = 0, CKP1n = 0, DAP1n = 0, SSE11 = 1 Note SSI11 SCK1n Read/write trigger SOTB1n 55H (communication data)
  • Page 449 CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 Figure 15-10. Timing in 3-Wire Serial I/O Mode (2/2) Note (2) Transmission/reception timing (Type 2; TRMD1n = 1, DIR1n = 0, CKP1n = 0, DAP1n = 1, SSE11 = 1 Note SSI11 SCK1n Read/write trigger SOTB1n 55H (communication data)
  • Page 450 CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 Figure 15-11. Timing of Clock/Data Phase (a) Type 1; CKP1n = 0, DAP1n = 0, DIR1n = 0 SCK1n SI1n capture SO1n Writing to SOTB1n or reading from SIO1n CSIIF1n CSOT1n (b) Type 2; CKP1n = 0, DAP1n = 1, DIR1n = 0 SCK1n SI1n capture SO1n...
  • Page 451 CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 (3) Timing of output to SO1n pin (first bit) When communication is started, the value of transmit buffer register 1n (SOTB1n) is output from the SO1n pin. The output operation of the first bit at this time is described below. Figure 15-12.
  • Page 452 CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 Figure 15-12. Output Operation of First Bit (2/2) (c) Type 2: CKP1n = 0, DAP1n = 1 SCK1n Writing to SOTB1n or reading from SIO1n SOTB1n SIO1n Output latch SO1n First bit 2nd bit 3rd bit (d) Type 4: CKP1n = 1, DAP1n = 1 SCK1n...
  • Page 453 CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 (4) Output value of SO1n pin (last bit) After communication has been completed, the SO1n pin holds the output value of the last bit. Figure 15-13. Output Value of SO1n Pin (Last Bit) (1/2) (a) Type 1: CKP1n = 0, DAP1n = 0 SCK1n ( ←...
  • Page 454 CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 Figure 15-13. Output Value of SO1n Pin (Last Bit) (2/2) (c) Type 2: CKP1n = 0, DAP1n = 1 SCK1n Writing to SOTB1n or ( ← Next request is issued.) reading from SIO1n SOTB1n SIO1n Output latch...
  • Page 455 CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 (5) SO1n output (see (a) in Figures 15-1 and 15-2) The status of the SO1n output is as follows depending on the setting of CSIE1n, TRMD1n, DAP1n, and DIR1n. Table 16-3. SO1n Output Status Note 1 CSIE1n TRMD1n...

  • Page 456: Chapter 16 Can Controller

    CHAPTER 16 CAN CONTROLLER 16.1 Outline Description All 78K0/Fx2 microcontroller products features an on-chip 1-channel CAN (Controller Area Network) controller that complies with CAN protocol as standardized in ISO 11898. 16.1.1 Features - Compliant with ISO 11898 and tested according to ISO/DIS 16845 (CAN conformance test) - Standard frame and extended frame transmission/reception enabled - Transfer rate: 1 Mbps max.

  • Page 457: Overview Of Functions

    CHAPTER 16 CAN CONTROLLER 16.1.2 Overview of functions Table 16-1 presents an overview of the CAN controller functions. Table 16-1. Overview of Functions Function Details Protocol CAN protocol ISO 11898 (standard and extended frame transmission/reception) Maximum 1 Mbps (CAN clock input ≥ 8 MHz) Baud rate Data storage Storing messages in the CAN RAM...

  • Page 458: Configuration

    CHAPTER 16 CAN CONTROLLER 16.1.3 Configuration The CAN controller is composed of the following four blocks. (1) NPB interface This functional block provides an NPB (NEC peripheral I/O bus) interface and means of transmitting and receiving signals between the CAN module and the host CPU. (2) MCM (Message Control Module) This functional block controls access to the CAN protocol layer and to the CAN RAM within the CAN module.

  • Page 459: Can Protocol

    CHAPTER 16 CAN CONTROLLER 16.2 CAN Protocol CAN (Controller Area Network) is a high-speed multiplex communication protocol for real-time communication in automotive applications (class C). CAN is prescribed by ISO 11898. For details, refer to the ISO 11898 specifications. The CAN specification is generally divided into two layers: a physical layer and a data link layer. In turn, the data link layer includes logical link and medium access control.

  • Page 460: Frame Types

    CHAPTER 16 CAN CONTROLLER 16.2.2 Frame types The following four types of frames are used in the CAN protocol. Table 16-2. Frame Types Frame Type Description Data frame Frame used to transmit data Remote frame Frame used to request a data frame Error frame Frame used to report error detection Overload frame...
  • Page 461 CHAPTER 16 CAN CONTROLLER (2) Remote frame A remote frame is composed of six fields. Figure 16-4. Remote Frame Remote frame <1> <2> <3> <5> <6> <7> <8> Interframe space End of frame (EOF) ACK field CRC field Control field Arbitration field Start of frame (SOF) Remarks 1.
  • Page 462 CHAPTER 16 CAN CONTROLLER <2> Arbitration field The arbitration field is used to set the priority, data frame/remote frame, and frame format. Figure 16-6. Arbitration Field (in Standard Format Mode) Arbitration field (Control field) Identifier (r1) ID28 · · · · · · · · · · · · · · · · · · · · ID18 (11 bits) (1 bit) (1 bit)
  • Page 463 CHAPTER 16 CAN CONTROLLER <3> Control field The control field sets “N” as the number of data bytes in the data field (N = 0 to 8). Figure 16-8. Control Field (Arbitration field) Control field (Data field) DLC3 DLC2 DLC1 DLC0 (IDE) Remark...
  • Page 464 CHAPTER 16 CAN CONTROLLER <4> Data field The data field contains the amount of data (byte units) set by the control field. Up to 8 units of data can be set. Figure 16-9. Data Field (Control field) Data field (CRC field) Data0 Data7 (8 bits)
  • Page 465 CHAPTER 16 CAN CONTROLLER <6> ACK field The ACK field is used to acknowledge normal reception. Figure 16-11. ACK Field (CRC field) ACK field (End of frame) ACK slot ACK delimiter (1 bit) (1 bit) Remark D: Dominant = 0 R: Recessive = 1 - If no CRC error is detected, the receiving node sets the ACK slot to the dominant level.
  • Page 466 CHAPTER 16 CAN CONTROLLER <8> Interframe space The interframe space is inserted after a data frame, remote frame, error frame, or overload frame to separate one frame from the next. - The bus state differs depending on the error status. (a) Error active node The interframe space consists of a 3-bit intermission field and a bus idle field.
  • Page 467 CHAPTER 16 CAN CONTROLLER - Operation in error status Table 16-6. Operation in Error Status Error Status Operation Error active A node in this status can transmit immediately after a 3-bit intermission. Error passive A node in this status can transmit 8 bits after the intermission. User’s Manual U19180EJ1V0UD...

  • Page 468: Error Frame

    CHAPTER 16 CAN CONTROLLER 16.2.4 Error frame An error frame is output by a node that has detected an error. Figure 16-15. Error Frame Error frame (<4>) <1> <2> <3> (<5>) 6 bits 0 to 6 bits 8 bits Interframe space or overload frame Error delimiter Error flag2 Error flag1...

  • Page 469: Overload Frame

    CHAPTER 16 CAN CONTROLLER 16.2.5 Overload frame An overload frame is transmitted under the following conditions. Note - When the receiving node has not completed the reception operation - If a dominant level is detected at the first two bits during intermission - If a dominant level is detected at the last bit (7th bit) of the end of frame or at the last bit (8th bit) of the error delimiter/overload delimiter Note The CAN is internally fast enough to process all received frames not generating overload frames.

  • Page 470: Functions

    CHAPTER 16 CAN CONTROLLER 16.3 Functions 16.3.1 Determining bus priority (1) When a node starts transmission: - During bus idle, the node that output data first transmits the data. (2) When more than one node starts transmission: - The node that outputs the dominant level for the longest consecutively from the first bit of the arbitration field acquires the bus priority (if a dominant level and a recessive level are simultaneously transmitted, the dominant level is taken as the bus value).

  • Page 471: Error Control Function

    CHAPTER 16 CAN CONTROLLER 16.3.6 Error control function (1) Error types Table 16-11. Error Types Type Description of Error Detection State Detection Method Detection Transmission/ Field/Frame Condition Reception Bit error Comparison of output level and Mismatch of levels Transmitting/ Bit that outputting data on the level on the bus receiving node bus at the start of frame to end of...
  • Page 472 CHAPTER 16 CAN CONTROLLER (4) Error state (a) Types of error states The following three types of error states are defined by the CAN specification. - Error active - Error passive - Bus-off These types of error states are classified by the values of the TEC7 to TEC0 bits (transmission error counter bits) and the REC6 to REC0 bits (reception error counter bits) of the CAN error counter register (C0ERC) as shown in Table 16-13.
  • Page 473 CHAPTER 16 CAN CONTROLLER Table 16-13. Types of Error States Type Operation Value of Error Indication of Operation specific to Given Error State Counter C0INFO Register Error active Transmission 0-95 TECS1, TECS0 = 00 - Outputs an active error flag (6 consecutive dominant-level bits) on detection of the Reception 0-95...
  • Page 474 CHAPTER 16 CAN CONTROLLER (b) Error counter The error counter counts up when an error has occurred, and counts down upon successful transmission and reception. The error counter is updated immediately after error detection. Table 16-14. Error Counter State Transmission Error Counter Reception Error Counter (TEC7 to TEC0) (REC6 to REC0)
  • Page 475 CHAPTER 16 CAN CONTROLLER (5) Recovery from bus-off state When the CAN module is in the bus-off state, the CAN module permanently sets its output signals (CTxD) to recessive level. The CAN module recovers from the bus-off state in the following bus-off recovery sequence. <1>...
  • Page 476 CHAPTER 16 CAN CONTROLLER Figure 16-17. Recovery Operation from Bus-off State through Normal Recovery Sequence TEC > FFH »bus-off« »bus-off-recovery-sequence« »error-active« »error-passive« BOFF bit in C0INFO register <1> <2> OPMODE[2:0] in C0CTRL ≠ 00H ≠ 00H register (user writings) <3> OPMODE[2:0] in C0CTRL ≠...

  • Page 477: Baud Rate Control Function

    CHAPTER 16 CAN CONTROLLER 16.3.7 Baud rate control function (1) Prescaler The CAN controller has a prescaler that divides the clock (f ) supplied to CAN. This prescaler generates a CAN protocol layer basic clock (f ) derived from the CAN module system clock (f ), and divided by 1 to CANMOD 256 (refer to 16.6 (12) CAN Bit Rate Prescaler Register (C0BRP)).
  • Page 478 CHAPTER 16 CAN CONTROLLER Reference: The CAN standard ISO 11898 specification defines the segments constituting the data bit time as shown in Figure 16-19. Figure 16-19. Reference: Configuration of Data Bit Time Defined by CAN Specification Data bit time(DBT) Sync segment Prop segment Phase segment 1 Phase segment 2...
  • Page 479 CHAPTER 16 CAN CONTROLLER (3) Synchronizing data bit - The receiving node establishes synchronization by a level change on the bus because it does not have a sync signal. - The transmitting node transmits data in synchronization with the bit timing of the transmitting node. (a) Hard-synchronization This synchronization is established when the receiving node detects the start of frame in the interframe space.
  • Page 480 CHAPTER 16 CAN CONTROLLER (b) Resynchronization Synchronization is established again if a level change is detected on the bus during reception (only if a recessive level was sampled previously). - The phase error of the edge is given by the relative position of the detected edge and sync segment. <Sign of phase error>...

  • Page 481: Connection With Target System

    CHAPTER 16 CAN CONTROLLER 16.4 Connection with Target System The microcontroller incorporated a CAN has to be connected to the CAN bus using an external transceiver. Figure 16-22. Connection to CAN Bus CTxD CAN_L Microcontroller Transceiver incorporated CRxD CAN_H a CAN User’s Manual U19180EJ1V0UD...

  • Page 482: Internal Registers Of Can Controller

    CHAPTER 16 CAN CONTROLLER 16.5 Internal Registers of CAN Controller 16.5.1 CAN controller configuration Table 16-15. List of CAN Controller Registers Item Register Name CAN global registers CAN global control register (C0GMCTRL) CAN global clock selection register (C0GMCS) CAN global automatic block transmission control register (C0GMABT) CAN global automatic block transmission delay register (C0GMABTD) CAN module registers CAN module mask 1 register (C0MASK1L, C0MASK1H)

  • Page 483: Register Access Type

    CHAPTER 16 CAN CONTROLLER 16.5.2 Register access type Table 16-16. Register Access Types (1/9) Address Register Name Symbol Bit Manipulation Units Default Value √ FA00H CAN0 message data byte 01 register 00 C0MDATA0100 Undefined √ FA00H CAN0 message data byte 0 register 00 C0MDATA000 Undefined √...
  • Page 484 CHAPTER 16 CAN CONTROLLER Table 16-16. Register Access Types (2/9) Address Register Name Symbol Bit Manipulation Units Default Value √ FA20H CAN0 message data byte 01 register 02 C0MDATA0102 Undefined √ FA20H CAN0 message data byte 0 register 02 C0MDATA002 Undefined √...
  • Page 485 CHAPTER 16 CAN CONTROLLER Table 16-16. Register Access Types (3/9) Address Register Name Symbol Bit Manipulation Units Default Value √ FA40H CAN0 message data byte 01 register 04 C0MDATA0104 Undefined √ FA40H CAN0 message data byte 0 register 04 C0MDATA004 Undefined √...
  • Page 486 CHAPTER 16 CAN CONTROLLER Table 16-16. Register Access Types (4/9) Address Register Name Symbol Bit Manipulation Units Default Value √ FA60H CAN0 message data byte 01 register 06 C0MDATA0106 Undefined √ FA60H CAN0 message data byte 0 register 06 C0MDATA006 Undefined √...
  • Page 487 CHAPTER 16 CAN CONTROLLER Table 16-16. Register Access Types (5/9) Address Register Name Symbol Bit Manipulation Units Default Value √ FA80H CAN0 message data byte 01 register 08 C0MDATA0108 Undefined √ FA80H CAN0 message data byte 0 register 08 C0MDATA008 Undefined √...
  • Page 488 CHAPTER 16 CAN CONTROLLER Table 16-16. Register Access Types (6/9) Address Register Name Symbol Bit Manipulation Units Default Value √ FAA0H CAN0 message data byte 01 register 10 C0MDATA0110 Undefined √ FAA0H CAN0 message data byte 0 register 10 C0MDATA010 Undefined √...
  • Page 489 CHAPTER 16 CAN CONTROLLER Table 16-16. Register Access Types (7/9) Address Register Name Symbol Bit Manipulation Units Default Value √ FAC0H CAN0 message data byte 01 register 12 C0MDATA0112 Undefined √ FAC0H CAN0 message data byte 0 register 12 C0MDATA012 Undefined √...
  • Page 490 CHAPTER 16 CAN CONTROLLER Table 16-16. Register Access Types (8/9) Address Register Name Symbol Bit Manipulation Units Default Value √ FAE0H CAN0 message data byte 01 register 14 C0MDATA0114 Undefined √ FAE0H CAN0 message data byte 0 register 14 C0MDATA014 Undefined √...
  • Page 491 CHAPTER 16 CAN CONTROLLER Table 16-16. Register Access Types (9/9) Address Register Name Symbol Bit Manipulation Units Default Value √ FF60H CAN0 module receive history list register C0RGPT – – xx02H √ FF62H CAN0 module transmit history list register C0TGPT –...

  • Page 492: Register Bit Configuration

    CHAPTER 16 CAN CONTROLLER 16.5.3 Register bit configuration Table 16-17. Bit Configuration of CAN Global Registers Address Symbol Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9 Bit 0/8 FF64H C0GMCTRL(W) Clear FF65H Set EFSD Set GOM FF64H C0GMCTRL(R)
  • Page 493 CHAPTER 16 CAN CONTROLLER Table 16-18. Bit Configuration of CAN Module Registers (1/2) Address Symbol Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9 Bit 0/8 FF60H C0RGPT(W) Clear ROVF FF61H FF60H C0RGPT(R) RHPM ROVF FF61H RGPT [7:0] FF62H...
  • Page 494 CHAPTER 16 CAN CONTROLLER Table 16-18. Bit Configuration of CAN Module Registers (2/2) Address Symbol Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9 Bit 0/8 FF90H C0CTRL(W) Clear Clear Clear Clear Clear Clear Clear Clear CCERC VALID...
  • Page 495 CHAPTER 16 CAN CONTROLLER Table 16-19. Bit Configuration of Message Buffer Registers Address Symbol Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9 Bit 0/8 FAx0H C0MDATA01m Message data (byte 0) FAx1H Message data (byte 1) FAx0H C0MDATA0m Message data (byte 0)

  • Page 496: Bit Set/Clear Function

    CHAPTER 16 CAN CONTROLLER 16.6 Bit Set/Clear Function The CAN control registers include registers whose bits can be set or cleared via the CPU and via the CAN interface. An operation error occurs if the following registers are written directly. Do not write any values directly via bit manipulation, read/modify/write, or direct writing of target values.
  • Page 497 CHAPTER 16 CAN CONTROLLER Figure 16-24. 16-Bit Data during Write Operation set 7 set 6 set 5 set 4 set 3 set 2 set 1 set 0 clear 7 clear 6 clear 5 clear 4 clear 3 clear 2 clear 1 clear 0 set n clear n Status of bit n after bit set/clear operation...

  • Page 498: Control Registers

    CHAPTER 16 CAN CONTROLLER 16.7 Control Registers Remark m = 0 to 15 (1) CAN global control register (C0GMCTRL) The C0GMCTRL register is used to control the operation of the CAN module. After reset: 0000H Address: FF64H, FF65H (a) Read C0GMCTRL MBON EFSD...
  • Page 499 CHAPTER 16 CAN CONTROLLER EFSD Bit Enabling Forced Shut Down Forced shut down by GOM = 0 disabled. Forced shut down by GOM = 0 enabled. Caution To request forced shutdown, the GOM bit must be cleared to 0 in a subsequent, immediately following write access after the EFSD bit has been set to 1.
  • Page 500 CHAPTER 16 CAN CONTROLLER (2) CAN global clock selection register (C0GMCS) The C0GMCS register is used to select the CAN module system clock. After reset: 0FH Address: FF6EH C0GMCS CCP3 CCP2 CCP1 CCP0 CCP3 CCP2 CCP1 CCP1 CAN Module System Clock (f CANMOD /16 (Default value) Remark f...
  • Page 501 CHAPTER 16 CAN CONTROLLER (3) CAN global automatic block transmission control register (C0GMABT) The C0GMABT register is used to control the automatic block transmission (ABT) operation. After reset: 0000H Address: FF66H, FF67H (a) Read C0GMABT ABTCLR ABTTRG (b) Write C0GMABT ABTCLR ABTTRG Clear...
  • Page 502 CHAPTER 16 CAN CONTROLLER (b) Write Set ABTCLR Automatic Block Transmission Engine Clear Request Bit The automatic block transmission engine is in idle state or under operation. Request to clear the automatic block transmission engine. After the automatic block transmission engine has been cleared, automatic block transmission is started from message buffer 0 by setting the ABTTRG bit to 1.
  • Page 503 CHAPTER 16 CAN CONTROLLER (4) CAN global automatic block transmission delay setting register (C0GMABTD) The C0GMABTD register is used to set the interval at which the data of the message buffer assigned to ABT is to be transmitted in the normal operation mode with ABT. After reset: 00H Address: FF6FH C0GMABTD...
  • Page 504 CHAPTER 16 CAN CONTROLLER (5) CAN module mask control register (C0MASKaL, C0MASKaH) (a = 1, 2, 3, or 4) The C0MASKaL and C0MASKaH registers are used to extend the number of receivable messages into the same message buffer by masking part of the ID comparison of a message and invalidating the ID of the masked part.
  • Page 505 CHAPTER 16 CAN CONTROLLER CAN Module Mask 3 Register (C0MASK3L, C0MASK3H) After reset: Undefined Address: C0MASK3L FF78H, FF79H C0MASK3H FF7AH, FF7BH C0MASK3L CMID15 CMID14 CMID13 CMID12 CMID11 CMID10 CMID9 CMID8 CMID7 CMID6 CMID5 CMID4 CMID3 CMID2 CMID1 CMID0 C0MASK3H CMID28 CMID27 CMID26 CMID25 CMID24 CMID23 CMID22 CMID21 CMID20 CMID19 CMID18 CMID17 CMID16 CAN Module Mask 4 Register (C0MASK4L, C0MASK4H) After reset: Undefined...
  • Page 506 CHAPTER 16 CAN CONTROLLER (6) CAN module control register (C0CTRL) The C0CTRL register is used to control the operation mode of the CAN module. After reset: 0000H Address: FF90H, FF91H (a) Read C0CTRL RSTAT TSTAT CCERC VALID PSMODE1 PSMODE0 OPMODE2 OPMODE1 OPMODE0 (b) Write C0CTRL CCERC...
  • Page 507 CHAPTER 16 CAN CONTROLLER TSTAT Transmission Status Bit Transmission is stopped. Transmission is in progress. Remark - The TSTAT bit is set to 1 under the following conditions (timing). - The SOF bit of a transmit frame is detected - The TSTAT bit is cleared to 0 under the following conditions (timing). - During transition to bus-off state - On occurrence of arbitration loss in transmit frame - On detection of recessive level at the second bit of the interframe space...
  • Page 508 CHAPTER 16 CAN CONTROLLER PSMODE1 PSMODE0 Power Save Mode No power save mode is selected. CAN sleep mode Setting prohibited CAN stop mode Cautions 1. Transition to and from the CAN stop mode must be made via CAN sleep mode. A request for direct transition to and from the CAN stop mode is ignored.
  • Page 509 CHAPTER 16 CAN CONTROLLER Clear VALID Setting of VALID Bit VALID bit is not changed. VALID bit is cleared to 0. Clear Setting of PSMODE0 Bit PSMODE0 PSMODE0 PSMODE0 bit is cleared to 0. PSMODE bit is set to 1. Other than above PSMODE0 bit is not changed.
  • Page 510 CHAPTER 16 CAN CONTROLLER (7) CAN module last error code register (C0LEC) The C0LEC register provides the error information of the CAN protocol. After reset: 00H Address: FF92H C0LEC LEC2 LEC1 LEC0 Remarks 1. The contents of the C0LEC register are not cleared when the CAN module changes from an operation mode to the initialization mode.
  • Page 511 CHAPTER 16 CAN CONTROLLER (8) CAN module information register (C0INFO) The C0INFO register indicates the status of the CAN module. After reset: 00H Address: FF93H C0INFO BOFF TECS1 TECS0 RECS1 RECS0 BOFF Bus-off State Bit Not bus-off state (transmit error counter ≤ 255) (The value of the transmit counter is less than 256.) Bus-off state (transmit error counter >...
  • Page 512 CHAPTER 16 CAN CONTROLLER (9) CAN module error counter register (C0ERC) The C0ERC register indicates the count value of the transmission/reception error counter. After reset: 0000H Address: FF94H, FF95H C0ERC REPS REC6 REC5 REC4 REC3 REC2 REC1 REC0 TEC7 TEC6 TEC5 TEC4 TEC3...
  • Page 513 CHAPTER 16 CAN CONTROLLER (10) CAN module interrupt enable register (C0IE) The C0IE register is used to enable or disable the interrupts of the CAN module. After reset: 0000H Address: FF96H, FF97H (a) Read C0IE CIE5 CIE4 CIE3 CIE2 CIE1 CIE0 (b) Write C0IE...
  • Page 514 CHAPTER 16 CAN CONTROLLER Set CIE3 Clear CIE3 Setting of CIE Bit CIE3 bit is cleared to 0. CIE3 bit is set to 1. Other than above CIE3 bit is not changed. Set CIE2 Clear CIE2 Setting of CIE2 Bit CIE2 bit is cleared to 0.
  • Page 515 CHAPTER 16 CAN CONTROLLER (11) CAN module interrupt status register (C0INTS) The C0INTS register indicates the interrupt status of the CAN module. After reset: 0000H Address: FF98H, FF99H (a) Read C0INTS CINTS5 CINTS4 CINTS3 CINTS2 CINTS1 CINTS0 (b) Write C0INTS Clear Clear Clear...
  • Page 516 CHAPTER 16 CAN CONTROLLER (12) CAN module bit rate prescaler register (C0BRP) The C0BRP register is used to select the CAN protocol layer basic clock (f ). The communication baud rate is set to the C0BTR register. After reset: FFH Address: FF9EH C0BRP TQPRS7 TQPRS6 TQPRS5 TQPRS4 TQPRS3 TQPRS2 TQPRS1 TQPRS0...
  • Page 517 CHAPTER 16 CAN CONTROLLER (13) CAN module bit rate register (C0BTR) The C0BTR register is used to control the data bit time of the communication baud rate. After reset: 370FH Address: FF9CH, FF9DH C0BTR SJW1 SJW0 TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 Figure 16-26.
  • Page 518 CHAPTER 16 CAN CONTROLLER SJW1 SJW0 Length of Synchronization jump width 4TQ (default value) TSEG22 TSEG21 TSEG20 Length of time segment 2 8TQ (default value) TSEG13 TSEG12 TSEG11 TSEG10 Length of time segment 1 Setting prohibited Note Note 10TQ 11TQ 12TQ 13TQ 14TQ...
  • Page 519 CHAPTER 16 CAN CONTROLLER (14) CAN module last in-pointer register (C0LIPT) The C0LIPT register indicates the number of the message buffer in which a data frame or a remote frame was last stored. After reset: Undefined Address: FF9FH C0LIPT LIPT7 LIPT6 LIPT5 LIPT4...
  • Page 520 CHAPTER 16 CAN CONTROLLER (15) CAN module receive history list register (C0RGPT) The C0RGPT register is used to read the receive history list. After reset: xx02H Address: FF60H, FF61H (a) Read C0RGPT RGPT7 RGPT6 RGPT5 RGPT4 RGPT3 RGPT2 RGPT1 RGPT0 RHPM ROVF (b) Write...
  • Page 521 CHAPTER 16 CAN CONTROLLER (b) Write Clear ROVF Setting of ROVF Bit ROVF bit is not changed. ROVF bit is cleared to 0. (16) CAN module last out-pointer register (C0LOPT) The C0LOPT register indicates the number of the message buffer to which a data frame or a remote frame was transmitted last.
  • Page 522 CHAPTER 16 CAN CONTROLLER (17) CAN module transmit history list register (C0TGPT) The C0TGPT register is used to read the transmit history list. After reset: xx02H Address: FF62H, FF63H (a) Read C0TGPT TGPT7 TGPT6 TGPT5 TGPT4 TGPT3 TGPT2 TGPT1 TGPT0 THPM TOVF (b) Write...
  • Page 523 CHAPTER 16 CAN CONTROLLER (b) Write Clear TOVF Setting of TOVF Bit TOVF bit is not changed. TOVF bit is cleared to 0. (18) CAN module time stamp register (C0TS) The C0TS register is used to control the time stamp function. After reset: 0000H Address: FF8AH, FF8BH (a) Read...
  • Page 524 CHAPTER 16 CAN CONTROLLER TSEN TSOUT Signal Operation Setting Bit Disable TSOUT signal toggle operation. Enable TSOUT signal toggle operation. Remark The signal TSOUT is output from the CAN macro to a timer resource, depending on implementation. Refer to Figure 14-19. (b) Write Set TSLOCK Clear...
  • Page 525 CHAPTER 16 CAN CONTROLLER (19) CAN message data byte register (C0MDATAxm)(x = 0 to 7), (C0MDATAzm) (z = 01, 23, 45, 67) The C0MDATAxm, C0MDATAzm registers are used to store the data of a transmit/receive message. The C0MDATAxm registers can access in 8-bit units. The C0MDATAzm registers can access the C0MDATAxm registers in 16-bit units.
  • Page 526 CHAPTER 16 CAN CONTROLLER - C0MDATAzm Register C0MDATA01m MDATA011 MDATA011 MDATA011 MDATA011 MDATA011 MDATA011 MDATA019 MDATA018 MDATA017 MDATA016 MDATA015 MDATA014 MDATA013 MDATA012 MDATA011 MDATA010 C0MDATA23m MDATA231 MDATA231 MDATA231 MDATA231 MDATA231 MDATA231 MDATA239 MDATA238 MDATA237 MDATA236 MDATA235 MDATA234 MDATA233 MDATA232 MDATA231 MDATA230 C0MDATA45m MDATA451 MDATA451 MDATA451...
  • Page 527 CHAPTER 16 CAN CONTROLLER (20) CAN message data length register m (C0MDLCm) The C0MDLCm register is used to set the number of bytes of the data field of a message buffer. After reset: 0000xxxxB Address: See Table 16-16 C0MDLCm MDLC3 MDLC2 MDLC1 MDLC0...
  • Page 528 CHAPTER 16 CAN CONTROLLER (21) CAN message configuration register (C0MCONFm) The C0MCONFm register is used to specify the type of the message buffer and to set a mask. After reset: Undefined Address: See Table 16-16 C0MCONFm Overwrite Control Bit Note The message buffer that has already received a data frame is not overwritten by a newly received data frame.
  • Page 529 CHAPTER 16 CAN CONTROLLER Message Buffer Assignment Bit Message buffer not used. Message buffer used. Caution Be sure to write 0 to bits 2 and 1. (22) CAN message id register m (C0MIDLm, C0MIDHm) The C0MIDLm and C0MIDHm registers are used to set an identifier (ID). After reset: Undefined Address: See Table 16-16 C0MIDLm...
  • Page 530 CHAPTER 16 CAN CONTROLLER (23) CAN message control register m (C0MCTRLm) The C0MCTRLm register is used to control the operation of the message buffer. After reset: 00x000000 Address: See Table 16-16. 00000000B (a) Read C0MCTRLm (b) Write C0MCTRLm Clear Clear Clear Clear Clear...
  • Page 531 CHAPTER 16 CAN CONTROLLER Message Buffer Data Updating Bit A data frame or remote frame is not stored in the message buffer. A data frame or remote frame is stored in the message buffer. Message Buffer Transmission Request Bit No message frame transmitting request that is pending or being transmitted is in the message buffer. The message buffer is holding transmission of a message frame pending or is transmitting a message frame.
  • Page 532 CHAPTER 16 CAN CONTROLLER Set TRQ Clear TRQ Setting of TRQ Bit TRQ bit is cleared to 0. TRQ bit is set to 1. Other than above TRQ bit is not changed. Caution While receiving a message from another node or transmitting the messages, there is a possibility of not to begin immediately the transmission even if the TRQ bit is set to 1.

  • Page 533: Can Controller Initialization

    CHAPTER 16 CAN CONTROLLER 16.8 CAN Controller Initialization 16.8.1 Initialization of CAN module Before the CAN module operation is enabled, the CAN module system clock needs to be determined by setting the CCP[3:0] bits of the C0GMCS register by software. Do not change the setting of the CAN module system clock after CAN module operation is enabled.

  • Page 534: Transition From Initialization Mode To Operation Mode

    CHAPTER 16 CAN CONTROLLER Figure 16-27. Setting Transmission Request (TRQ) to Transmit Message Buffer After Redefining Redefinition completed Execute transmission? Wait for 1 bit of CAN data. Set TRQ bit Set TRQ = 1 Clear TRQ = 0 Cautions 1. When a message is received, reception filtering is performed in accordance with the ID and mask set to each receive message buffer.

  • Page 535: Resetting Error Counter C0Erc Of Can Module

    CHAPTER 16 CAN CONTROLLER Figure 16-28. Transition to Operation Modes OPMODE[2:0] = 00H and CAN bus is busy. [Receive-only mode] OPMODE[2:0]=03H OPMODE[2:0] = 00H OPMODE[2:0] = 00H and CAN bus is busy. and CAN bus is busy. [Normal operation OPMODE[2:0] = 03H mode with ABT] [Single-shot mode] OPMODE[2:0]=02H...

  • Page 536: Message Reception

    CHAPTER 16 CAN CONTROLLER 16.9 Message Reception 16.9.1 Message reception In all the operation modes, the complete message buffer area is analyzed to find a suitable buffer to store a newly received message. All message buffers satisfying the following conditions are included in that evaluation (RX-search process).

  • Page 537: Receive Data Read

    CHAPTER 16 CAN CONTROLLER 16.9.2 Receive Data Read To keep data consistency when reading CAN message buffers, perform the data reading according to Figure 16-51 to 16-53. During message reception, the CAN module sets DN of the C0MCTRLm register two times: at the beginning of the storage process of data to the message buffer, and again at the end of this storage process.

  • Page 538: Receive History List Function

    CHAPTER 16 CAN CONTROLLER 16.9.3 Receive history list function The receive history list (RHL) function records in the receive history list the number of the receive message buffer in which each data frame or remote frame was received and stored. The RHL consists of storage elements equivalent to up to 23 messages, the last in-message pointer (LIPT) with the corresponding C0LIPT register and the receive history list get pointer (RGPT) with the corresponding C0RGPT register.
  • Page 539 CHAPTER 16 CAN CONTROLLER As long as the RHL contains 23 or less entries the sequence of occurrence is maintained. If more receptions occur without reading the RHL by the host processor, complete sequence of receptions can not be recovered. Figure 16-30.

  • Page 540: Mask Function

    CHAPTER 16 CAN CONTROLLER 16.9.4 Mask function For any message buffer, which is used for reception, the assignment to one of four global reception masks (or no mask) can be selected. By using the mask function, the message ID comparison can be reduced by masked bits, herewith allowing the reception of several different IDs into one buffer.
  • Page 541 CHAPTER 16 CAN CONTROLLER <3> Mask setting for CAN module 1 (mask 1) (Example) (Using CAN1 address mask 1 registers L and H (C1MASK1L and C1MASK1H)) CMID28 CMID27 CMID26 CMID25 CMID24 CMID23 CMID22 CMID21 CMID20 CMID19 CMID18 CMID17 CMID16 CMID15 CMID14 CMID13 CMID12...

  • Page 542: Multi Buffer Receive Block Function

    CHAPTER 16 CAN CONTROLLER 16.9.5 Multi buffer receive block function The multi buffer receive block (MBRB) function is used to store a block of data in two or more message buffers sequentially with no CPU interaction, by setting the same ID to two or more message buffers with the same message buffer type.

  • Page 543: Remote Frame Reception

    CHAPTER 16 CAN CONTROLLER 16.9.6 Remote frame reception In all the operation modes, when a remote frame is received, the message buffer that is to store the remote frame is searched from all the message buffers satisfying the following conditions. - Used as a message buffer (MA0 bit of C0MCONFm register set to 1B.) - Set as a transmit message buffer...

  • Page 544: Message Transmission

    CHAPTER 16 CAN CONTROLLER 16.10 Message Transmission 16.10.1 Message transmission In all the operation modes, if the TRQ bit is set to 1 in a message buffer that satisfies the following conditions, the message buffer that is to transmit a message is searched. - Used as a message buffer (MA0 bit of C0MCONFm register set to 1B.) - Set as a transmit message buffer...
  • Page 545 CHAPTER 16 CAN CONTROLLER Priority Conditions Description 1(high) Value of first 11 bits of ID The message frame with the lowest value represented by the first 11 bits of the ID is transmitted first. If the value of an 11-bit [ID28 to ID18]: standard ID is equal to or smaller than the first 11 bits of a 29-bit extended ID, the 11-bit standard ID has a higher priority than...

  • Page 546: Transmit History List Function

    CHAPTER 16 CAN CONTROLLER 16.10.2 Transmit history list function The transmit history list (THL) function records in the transmit history list the number of the transmit message buffer from which data or remote frames have been were sent. The THL consists of storage elements equivalent to up to seven messages, the last out-message pointer (LOPT) with the corresponding C0LOPT register, and the transmit history list get pointer (TGPT) with the corresponding C0TGPT register.
  • Page 547 CHAPTER 16 CAN CONTROLLER Figure 16-32. Transmit History List Transmit history list (THL) Transmit history list (THL) Event: Message buffer 4 - CPU confirms Tx completion Message buffer 3 of message buffer 6, 9, and 2. Last out- Last out- Message buffer 7 Message buffer 7 - Tx completion of message...

  • Page 548: Automatic Block Transmission (Abt)

    CHAPTER 16 CAN CONTROLLER 16.10.3 Automatic block transmission (ABT) The automatic block transmission (ABT) function is used to transmit two or more data frames successively with no CPU interaction. The maximum number of transmit message buffers assigned to the ABT function is eight (message buffer numbers 0 to 7).

  • Page 549: Transmission Abort Process

    CHAPTER 16 CAN CONTROLLER Cautions 1. Set the ABTCLR bit to 1 while the ABTTRG bit is cleared to 0 in order to resume ABT operation at buffer No.0. If the ABTCLR bit is set to 1 while the ABTTRG bit is set to 1, the subsequent operation is not guaranteed.

  • Page 550: Remote Frame Transmission

    CHAPTER 16 CAN CONTROLLER (3) Transmission abort process for ABT transmission in normal operation mode with automatic block transmission (ABT) To abort ABT that is already started, clear the ABTTRG bit of the C0GMABT register to 0. In this case, the ABTTRG bit remains 1 if an ABT message is currently being transmitted and until the transmission is completed (successfully or not), and is cleared to 0 as soon as transmission is finished.

  • Page 551: Power Save Modes

    CHAPTER 16 CAN CONTROLLER 16.11 Power Save Modes 16.11.1 CAN sleep mode The CAN sleep mode can be used to set the CAN controller to standby mode in order to reduce power consumption. The CAN module can enter the CAN sleep mode from all operation modes. Release of the CAN sleep mode returns the CAN module to exactly the same operation mode from which the CAN sleep mode was entered.
  • Page 552 CHAPTER 16 CAN CONTROLLER - Even when initialization mode and sleep mode are not requested simultaneously (i.e the first request has not been granted while the second request is made), the request for initialization has priority over the sleep mode request. The sleep mode request is cancelled when the initialization mode is requested. When a pending request for initialization mode is present, a subsequent request for Sleep mode request is cancelled right at the point in time where it was submitted.

  • Page 553: Can Stop Mode

    CHAPTER 16 CAN CONTROLLER 16.11.2 CAN stop mode The CAN stop mode can be used to set the CAN controller to standby mode to reduce power consumption. The CAN module can enter the CAN stop mode only from the CAN sleep mode. Release of the CAN stop mode puts the CAN module in the CAN sleep mode.

  • Page 554: Example Of Using Power Saving Modes

    CHAPTER 16 CAN CONTROLLER 16.11.3 Example of using power saving modes In some application systems, it may be necessary to place the CPU in a power saving mode to reduce the power consumption. By using the power saving mode specific to the CAN module and the power saving mode specific to the CPU in combination, the CPU can be woken up from the power saving status by the CAN bus.

  • Page 555: Interrupt Function

    CHAPTER 16 CAN CONTROLLER 16.12 Interrupt Function The CAN module provides 6 different interrupt sources. The occurrence of these interrupt sources is stored in interrupt status registers. Four separate interrupt request signals are generated from the six interrupt sources. When an interrupt request signal that corresponds to two or more interrupt sources is generated, the interrupt sources can be identified by using an interrupt status register.

  • Page 556: Diagnosis Functions And Special Operational Modes

    CHAPTER 16 CAN CONTROLLER 16.13 Diagnosis Functions and Special Operational Modes The CAN module provides a receive-only mode, single-shot mode, and self-test mode to support CAN bus diagnosis functions or the operation of specific CAN communication methods. 16.13.1 Receive-only mode The receive-only mode is used to monitor receive messages without causing any interference on the CAN bus and can be used for CAN bus analysis nodes.

  • Page 557: Single-Shot Mode

    CHAPTER 16 CAN CONTROLLER Furthermore, ACK is not returned to the CAN bus in this mode upon the valid reception of a message frame. Internally, the local node recognizes that it has transmitted ACK. An overload frame cannot be transmitted to the CAN bus.

  • Page 558: Self-Test Mode

    CHAPTER 16 CAN CONTROLLER 16.13.3 Self-test mode In the self-test mode, message frame transmission and message frame reception can be tested without connecting the CAN node to the CAN bus or without affecting the CAN bus. In the self-test mode, the CAN module is completely disconnected from the CAN bus, but transmission and reception are internally looped back.

  • Page 559: Receive/Transmit Operation In Each Operation Mode

    CHAPTER 16 CAN CONTROLLER 16.13.4 Receive/Transmit Operation in Each Operation Mode Table 16-21 shows outline of the receive/transmit operation in each operation mode. Table 16-21. Outline of the Receive/Transmit in Each Operation Mode Operation Transmission Transmission Transmission Transmission Automatic Set of Store Data Mode of data/...

  • Page 560: Time Stamp Function

    CHAPTER 16 CAN CONTROLLER 16.14 Time Stamp Function CAN is an asynchronous, serial protocol. All nodes connected to the CAN bus have a local, autonomous clock. As a consequence, the clocks of the nodes have no relation (i.e., the clocks are asynchronous and may have different frequencies).
  • Page 561 CHAPTER 16 CAN CONTROLLER Caution The time stamp function using TSLOCK bit is to stop toggle of TSOUT bit by receiving a data frame in message buffer 0. Therefore, message buffer 0 must be set as a receive message buffer. Since a receive message buffer cannot receive a remote frame, toggle of TSOUT bit cannot be stopped by reception of a remote frame.

  • Page 562: Baud Rate Settings

    CHAPTER 16 CAN CONTROLLER 16.15 Baud Rate Settings 16.15.1 Baud rate settings Make sure that the settings are within the range of limit values for ensuring correct operation of the CAN controller, as follows. (a) 5TQ ≤ SPT (sampling point) ≤ 17TQ SPT = TSEG1 + 1TQ (b) 8TQ ≤...
  • Page 563 CHAPTER 16 CAN CONTROLLER Table 16-22. Settable Bit Rate Combinations (1/3) Valid Bit Rate Setting C0BTR Register Setting Sampling Point Value (Unit %) DBT Length SYNC PROP PHASE PHASE TSEG1[3:0] TSEG2[2:0] SEGMENT SEGMENT SEGMENT1 SEGMENT2 1111 68.0 1110 66.7 1111 70.8 1101 65.2...
  • Page 564 CHAPTER 16 CAN CONTROLLER Table 16-22. Settable Bit Rate Combinations (2/3) Valid Bit Rate Setting C0BTR Register Setting Sampling Point Value (Unit %) DBT Length SYNC PROP PHASE PHASE TSEG1[3:0] TSEG2[2:0] SEGMENT SEGMENT SEGMENT1 SEGMENT2 1000 58.8 1001 64.7 1010 70.6 1011 76.5...
  • Page 565 CHAPTER 16 CAN CONTROLLER Table 16-22. Settable Bit Rate Combinations (3/3) Valid Bit Rate Setting C0BTR Register Setting Sampling Point Value (Unit %) DBT Length SYNC PROP PHASE PHASE TSEG1[3:0] TSEG2[2:0] SEGMENT SEGMENT SEGMENT1 SEGMENT2 0101 63.6 0110 72.7 0111 81.8 1000 90.9...

  • Page 566: Representative Examples Of Baud Rate Settings

    CHAPTER 16 CAN CONTROLLER 16.15.2 Representative examples of baud rate settings Tables 16-23 and 16-24 show representative examples of baud rate setting. Table 16-23. Representative Examples of Baud Rate Settings (f = 8 MHz) (1/2) CANMOD Set Baud Division C0BRP Valid Bit Rate Setting (Unit: kbps) C0BTR Register Sampling...
  • Page 567 CHAPTER 16 CAN CONTROLLER Table 16-23. Representative Examples of Baud Rate Settings (f = 8 MHz) (2/2) CANMOD Set Baud Division C0BRP Valid Bit Rate Setting (Unit: kbps) C0BTR Register Sampling Rate Value Ratio of Register Setting Value point (Unit: kbps) C0BRP Set Value (Unit: %)
  • Page 568 CHAPTER 16 CAN CONTROLLER Table 16-24. Representative Examples of Baud Rate Settings (f = 16 MHz) (1/2) CANMOD Set Baud Division C0BRP Valid Bit Rate Setting (Unit: kbps) C0BTR Register Sampling Rate Value Ratio of Register Setting Value point (Unit: kbps) C0BRP Set Value (Unit: %)
  • Page 569 CHAPTER 16 CAN CONTROLLER Table 16-24. Representative Examples of Baud Rate Settings (f = 16 MHz) (2/2) CANMOD Set Baud Division C0BRP Valid Bit Rate Setting (Unit: kbps) C0BTR Register Sampling Rate Value Ratio of Register Setting Value point (Unit: kbps) C0BRP Set Value (Unit: %)

  • Page 570: Operation Of Can Controller

    CHAPTER 16 CAN CONTROLLER 16.16 Operation of CAN Controller Remark m = 0 to 15 Figure 16-37. Initialization START CnGMCS register CnGMCTRL register (Set GOM = 1) CnBRP register, CnBTR register CnIE register CnMASK register Initialize message buffers CnCTRL register (set OPMODE) Remark OPMODE: Normal operation mode, normal operation mode with ABT, receive-only mode, single- shot mode, self-test mode...
  • Page 571 CHAPTER 16 CAN CONTROLLER Figure 16-38. Re-initialization START Clear OPMODE INIT mode? C0BRP register, C0BTR register C0IE register C0MASK register Initialize message buffers C0ERC and C0INFO register clear? Set CCERC bit Set C0CTRL register (Set OPMODE) Caution After setting the CAN module to the initialization mode, avoid setting the module to another operation mode immediately after.
  • Page 572 CHAPTER 16 CAN CONTROLLER Figure 16-39. Message Buffer Initialization START START RDY = 1? Clear RDY bit RDY = 0? C0MCONFm register C0MIDHm register, C0MIDLm register Transmit message buffer? C0MDLCm register Clear C0MDATAm register C0MCTRLm register Set RDY bit Cautions 1. Before a message buffer is initialized, the RDY bit must be cleared. 2.
  • Page 573 CHAPTER 16 CAN CONTROLLER Figure 16-40 shows the processing for a receive message buffer (MT [2:0] bits of C0MCONFm register = 001B to 101B). Figure 16-40. Message Buffer Redefinition START Clear VALID bit RDY = 1? Clear RDY bit RDY = 0? RSTAT = 0 or Note 1 VALID = 1?
  • Page 574 CHAPTER 16 CAN CONTROLLER Figure 16-41 shows the processing for a transmit message buffer during transmission (MT [2:0] bits of C0MCONFm register = 000B). Figure 16-41. Message Buffer Redefinition during Transmission START Transmit abort process Clear RDY bit RDY = 0? Data frame Remote frame Data frame or remote frame?
  • Page 575 CHAPTER 16 CAN CONTROLLER Figure 16-42 shows the processing for a transmit message buffer (MT [2:0] bits of C0MCONFm register = 000B). Figure 16-42. Message Transmit Processing START TRQ = 0? Clear RDY bit RDY = 0? Data frame Remote frame Data frame or remote frame? Set C0MDATAxm register Set C0MDLCm register...
  • Page 576 CHAPTER 16 CAN CONTROLLER Figure 16-43 shows the processing for a transmit message buffer (MT [2:0] bits of C0MCONFm register = 000B). Figure 16-43. ABT Message Transmit Processing START ABTTRG = 0? Clear RDY bit RDY = 0? Set C0MDATAxm register Set C0MDLCm register Clear RTR bit of C0MCONFm register...
  • Page 577 CHAPTER 16 CAN CONTROLLER Figure 16-44. Transmission via Interrupt (Using C0LOPT register) START Transmit completion interrupt processing Read C0LOPT register Clear RDY bit RDY = 0? Data frame Remote frame Data frame or remote frame? Set C0MDATAxm register Set C0MDLCm register Set C0MDLCm register, Set RTR bit of C0MCONFm Clear RTR bit of C0MCONFm...
  • Page 578 CHAPTER 16 CAN CONTROLLER Figure 16-45. Transmit via Interrupt (Using C0TGPT register) START Transmit completion interrupt processing Read C0TGPT register TOVF = 1? Clear TOVF bit Clear RDY bit RDY = 0? Data frame Remote frame Data frame or remote frame? Set C0MDATAxm register Set C0MDLCm register Set C0MDLCm register...
  • Page 579 CHAPTER 16 CAN CONTROLLER Figure 16-46. Transmission via Software Polling START CINTS0 = 1? Clear CINTS0 bit Read C0TGPT register TOVF = 1? Clear TOVF bit Clear RDY bit RDY = 0? Data frame Remote frame Data frame or remote frame? Set C0MDATAxm register Set C0MDLCm register Set C0MDLCm register...
  • Page 580 CHAPTER 16 CAN CONTROLLER Figure 16-47. Transmission Abort Processing (Except Normal Operation Mode with ABT) START Clear TRQ bit Note Wait for 11 CAN data bits TSTAT = 0? Read C0LOPT register Message buffer to be aborted matches C0LOPT register? Transmit abort request was successful Transmission successful...
  • Page 581 CHAPTER 16 CAN CONTROLLER Figure 16-48. Transmission Abort Processing Except for ABT Transmission (Normal Operation Mode with ABT) START Clear ABTTRG bit ABTTRG = 0? Clear TRQ bit Note Wait for 11 CAN data bits TSTAT = 0? Read C0LOPT register Message buffer to be aborted matches C0LOPT register?
  • Page 582 CHAPTER 16 CAN CONTROLLER Cautions 5 There is a possibility that contradiction is caused in the judgment whether the transmission abort request was successful when the transmission from the same message buffer is consecutive or only one message buffer is used. In that case, judge it by using the history information etc.
  • Page 583 CHAPTER 16 CAN CONTROLLER Figure 16-49 shows the processing not to skip resumption of transmitting a message that was stopped when transmission of an ABT message buffer was aborted. Figure 16-49. ABT Transmission Abort Processing (Normal Operation Mode with ABT) START TSTAT = 0? Clear ABTTRG bit...
  • Page 584 CHAPTER 16 CAN CONTROLLER Figure 16-50 shows the processing to skip resumption of transmitting a message that was stopped when transmission of an ABT message buffer was aborted. Figure 16-50. ABT Transmission Request Abort Processing (Normal Operation Mode with ABT) START Clear TRQ bit of message buffer undergoing transmission...
  • Page 585 CHAPTER 16 CAN CONTROLLER Figure 16-51. Reception via Interrupt (Using C0LIPT Register) START Generation of receive completion interrupt Read C0LIPT register Clear DN bit Read C0MDATAxm , C0MDLCm, C0MIDLm, and C0MIDHm registers DN = 0 Note MUC = 0 Note Check the MUC and DN bits using one read access. Remark Also check the MBON flag at the beginning and at the end of the interrupt routine, in order to check the access to the message buffers as well as reception history list registers, in case a pending sleep mode had been executed.
  • Page 586 CHAPTER 16 CAN CONTROLLER Figure 16-52. Reception via Interrupt (Using C0RGPT Register) START Generation of receive completion interrupt Read C0RGPT register ROVF = 1? Clear ROVF bit RHPM = 1? Clear DN bit Read C0MDATAxm , C0MDLCm, C0MIDLm, C0MIDHm registers DN = 0 Note MUC = 0...
  • Page 587 CHAPTER 16 CAN CONTROLLER Figure 16-53. Reception via Software Polling START CINTS1 = 1? Clear CINTS1 bit Read C0RGPT register ROVF = 1? Clear ROVF bit RHPM = 1? Clear DN bit Read C0MDATAxm , C0MDLCm, C0MIDLm, C0MIDHm registers DN = 0 Note MUC = 0 Correct data is read...
  • Page 588 CHAPTER 16 CAN CONTROLLER Figure 16-54. Setting CAN Sleep Mode/Stop Mode START (when PSMODE[1:0] = 00B) Set PSMODE0 bit PSMODE0 = 1? CAN sleep mode CAN sleep mode Set PSMODE1 bit PSMODE1 = 1? Request CAN sleep mode again? CAN stop mode CAN stop mode Clear OPMODE INIT mode?
  • Page 589 CHAPTER 16 CAN CONTROLLER Figure 16-55. Clear CAN Sleep/Stop Mode START CAN stop mode Clear PSMODE1 bit (In case CAN clock is disabled) (In case CAN clock is active) CAN sleep mode Releasing CAN sleep mode Releasing CAN sleep mode by CAN bus active by CAN bus active After dominant edge...
  • Page 590 CHAPTER 16 CAN CONTROLLER Figure 16-56. Bus-Off Recovery (Expect Normal Operation Mode with ABT) START BOFF = 1? Note Clear all TRQ bits Set C0CTRL register (Clear OPMODE) Access to registers other than C0CTRL and C0GMCTRL registers Forced recovery from bus off? Set C0CTRL register Set CCERC bit (Set OPMODE)
  • Page 591 CHAPTER 16 CAN CONTROLLER Figure 16-57. Bus-Off Recovery (Normal Operation Mode with ABT) START BOFF = 1? Clear ABTTRG bit Note Clear all TRQ bits Set C0CTRL register (Clear OPMODE) Access to registers other than C0CTRL and C0GMCTRL registers Forced recovery from bus off? Set C0CTRL register Set CCERC bit (Set OPMODE)
  • Page 592 CHAPTER 16 CAN CONTROLLER Figure 16-58. Normal Shutdown Process START INIT mode Clear GOM bit Shutdown successful GOM = 0, EFSD = 0 User’s Manual U19180EJ1V0UD...
  • Page 593 CHAPTER 16 CAN CONTROLLER Figure 16-59. Forced Shutdown Process START Set EFSD bit Must be a subseguent write Clear GOM bit GOM = 0? Shutdown successful GOM = 0, EFSD = 0 Caution Do not read- or write-access any registers by software between setting the EFSD bit and clearing the GOM bit.
  • Page 594 CHAPTER 16 CAN CONTROLLER Figure 16-60. Error Handling START Error interrupt CINTS2 = 1? Check CAN module state (read C0INFO register) Clear CINTS2 bit CINTS3 = 1? Check CAN protocol error state (read C0LEC register) Clear CINTS3 bit CINTS4 = 1? Clear CINTS4 bit User’s Manual U19180EJ1V0UD...
  • Page 595 CHAPTER 16 CAN CONTROLLER Figure 16-61. Setting CPU Standby (from CAN Sleep Mode) START Set PSMODE0 bit PSMODE0 = 1? CAN sleep mode MBON bit = 0? CINTS5 bit = 1? Set CPU standby mode Clear PSMODE0 bit Clear CINTS5 bit Caution Before the CPU is set in the CPU standby mode, please check the CAN sleep mode or not.
  • Page 596 CHAPTER 16 CAN CONTROLLER Figure 16-62. Setting CPU Standby (from CAN Stop Mode) START Set PSMODE0 bit PSMODE0 = 1? CAN sleep mode Set PSMODE1 bit PSMODE1 = 1? Clear PSMODE0 bit CAN stop mode Note Clear CINTS5 bit MBON bit = 0? Set CPU standby mode Note During wakeup interrupts Caution The CAN stop mode can only be released by writing 01B to the PSMODE[1:0] bit of the C0CTRL...

  • Page 597: Chapter 17 Interrupt Functions

    CHAPTER 17 INTERRUPT FUNCTIONS 78K0/FC2 78K0/FE2 78K0/FF2 μ μ μ PD78F088yA, 78F089zA) PD78F088yA, 78F0890A) PD78F089yA) y = 1 to 6, z = 4, 5 y = 7 to 9 y = 1 to 3 Maskable External interrupts internal 17.1 Interrupt Function Types The following two types of interrupt functions are used.
  • Page 598 CHAPTER 17 INTERRUPT FUNCTIONS Table 17-1. Interrupt Source List (1/2) Interrupt Internal/ Basic Default Interrupt Source Vector Table Note 1 Type External Configuration Priority Address Note 2 Name Trigger Type Note 3 √ √ √ Maskable Internal INTLVI Low-voltage detection 0004H √...
  • Page 599 CHAPTER 17 INTERRUPT FUNCTIONS Table 17-1. Interrupt Source List (2/2) Interrupt Internal/ Basic Default Interrupt Source Vector Table Note 1 Type External Configuration Priority Address Note 2 Type Name Trigger Maskable Internal INTTMH1 Match between TMH1 and CMP01 0026H √ √...
  • Page 600 CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-1. Basic Configuration of Interrupt Function (A) Internal maskable interrupt Internal bus Vector table Priority controller Interrupt address generator request Standby release signal (B) External maskable interrupt (INTP0 to INTP7) Internal bus External interrupt edge enable register (EGP, EGN) Vector table...

  • Page 601: Registers Controlling Interrupt Functions

    CHAPTER 17 INTERRUPT FUNCTIONS 17.3 Registers Controlling Interrupt Functions The following 6 types of registers are used to control the interrupt functions. • Interrupt request flag register (IF0L, IF0H, IF1L, IF1H) • Interrupt mask flag register (MK0L, MK0H, MK1L, MK1H) •...
  • Page 602 CHAPTER 17 INTERRUPT FUNCTIONS Table 17-2. Flags Corresponding to Interrupt Request Sources Interrupt Interrupt Request Flag Interrupt Mask Flag Priority Specification Flag Request Register Register Register √ √ √ INTLVI LVIIF IF0L LVIMK MK0L LVIPR PR0L √ √ √ INTP0 PIF0 PMK0 PPR0...
  • Page 603 CHAPTER 17 INTERRUPT FUNCTIONS (1) Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H) The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon reset signal generation.
  • Page 604 CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-2. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H) (78K0/FC2) Address: FFE0H After reset: 00H R/W Symbol <7> <6> <5> <4> <3> <2> <1> <0> IF0L C0ERRIF PIF5 PIF4 PIF3 PIF2 PIF1 PIF0 LVIIF Address: FFE1H After reset: 00H...
  • Page 605 CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-3. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H) (78K0/FE2, 78K0/FF2) Address: FFE0H After reset: 00H R/W Symbol <7> <6> <5> <4> <3> <2> <1> <0> DUALIF6 DUALIF5 DUALIF4 DUALIF3 IF0L C0ERRIF PIF1 PIF0 LVIIF PIF5...
  • Page 606 CHAPTER 17 INTERRUPT FUNCTIONS (2) Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H) The interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing. MK0L, MK0H, MK1L, and MK1H are set by a 1-bit or 8-bit memory manipulation instruction. When MK0L and MK0H, and MK1L and MK1H are combined to form 16-bit registers MK0 and MK1, they are set with a 16-bit memory manipulation instruction.
  • Page 607 CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-5. Format of Interrupt Mask Flag Registers (MK0L, MK0H, MK1L, MK1H) (78K0/FE2, 78K0/FF2) Address: FFE4H After reset: FFH Symbol <7> <6> <5> <4> <3> <2> <1> <0> DUALMK6 DUALMK5 DUALMK4 DUALMK3 MK0L C0ERRMK PMK1 PMK0 LVIMK PMK5 PMK4...
  • Page 608 CHAPTER 17 INTERRUPT FUNCTIONS (3) Priority specification flag registers (PR0L, PR0H, PR1L, PR1H) The priority specification flag registers are used to set the corresponding maskable interrupt priority order. PR0L, PR0H, PR1L, and PR1H are set by a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H, and PR1L and PR1H are combined to form 16-bit registers PR0 and PR1, they are set with a 16-bit memory manipulation instruction.
  • Page 609 CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-7. Format of Priority Specification Flag Registers (PR0L, PR0H, PR1L, PR1H) (78K0/FE2, 78K0/FF2) Address: FFE8H After reset: FFH Symbol <7> <6> <5> <4> <3> <2> <1> <0> DUALPR6 DUALPR5 DUALPR4 DUALPR3 PR0L C0ERRPR PPR1 PPR0 LVIPR PPR5 PPR4...
  • Page 610 CHAPTER 17 INTERRUPT FUNCTIONS (4) External interrupt rising edge enable register (EGP), external interrupt falling edge enable register (EGN) These registers specify the valid edge for INTP0 to INTP7. EGP and EGN are set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H.
  • Page 611 CHAPTER 17 INTERRUPT FUNCTIONS (5) Program status word (PSW) The program status word is a register used to hold the instruction execution result and the current status for an interrupt request. The IE flag that sets maskable interrupt enable/disable and the ISP flag that controls multiple interrupt servicing are mapped to the PSW.

  • Page 612: Interrupt Servicing Operations

    CHAPTER 17 INTERRUPT FUNCTIONS 17.4 Interrupt Servicing Operations 17.4.1 Maskable interrupt acknowledgement A maskable interrupt becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (MK) flag corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if interrupts are in the interrupt enabled state (when the IE flag is set to 1).
  • Page 613 CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-10. Interrupt Request Acknowledgement Processing Algorithm Start ××IF = 1? Yes (interrupt request generation) ××MK = 0? Interrupt request held pending Yes (High priority) ××PR = 0? No (Low priority) Any high-priority Any high-priority interrupt request among those interrupt request among simultaneously generated with ××PR = 0?

  • Page 614: Software Interrupt Request Acknowledgement

    CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-11. Interrupt Request Acknowledgement Timing (Minimum Time) 6 clocks PSW and PC saved, Interrupt servicing CPU processing Instruction Instruction jump to interrupt program servicing ××IF (××PR = 1) 8 clocks ××IF (××PR = 0) 7 clocks Remark 1 clock: 1/f : CPU clock) Figure 17-12.

  • Page 615: Multiple Interrupt Servicing

    CHAPTER 17 INTERRUPT FUNCTIONS 17.4.3 Multiple interrupt servicing Multiple interrupt servicing occurs when another interrupt request is acknowledged during execution of an interrupt. Multiple interrupt servicing does not occur unless the interrupt request acknowledgement enabled state is selected (IE = 1). When an interrupt request is acknowledged, interrupt request acknowledgement becomes disabled (IE = 0). Therefore, to enable multiple interrupt servicing, it is necessary to set (1) the IE flag with the EI instruction during interrupt servicing to enable interrupt acknowledgement.
  • Page 616 CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-13. Examples of Multiple Interrupt Servicing (1/2) Example 1. Multiple interrupt servicing occurs twice Main processing INTxx servicing INTyy servicing INTzz servicing IE = 0 IE = 0 IE = 0 INTxx INTyy INTzz (PR = 1) (PR = 0) (PR = 0) RETI...
  • Page 617 CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-13. Examples of Multiple Interrupt Servicing (2/2) Example 3. Multiple interrupt servicing does not occur because interrupts are not enabled Main processing INTxx servicing INTyy servicing IE = 0 INTyy (PR = 0) INTxx (PR = 0) RETI IE = 1 IE = 0...

  • Page 618: Interrupt Request Hold

    CHAPTER 17 INTERRUPT FUNCTIONS 17.4.4 Interrupt request hold There are instructions where, even if an interrupt request is issued for them while another instruction is being executed, request acknowledgement is held pending until the end of execution of the next instruction. These instructions (interrupt request hold instructions) are listed below.

  • Page 619: Chapter 18 Standby Function

    CHAPTER 18 STANDBY FUNCTION 18.1 Standby Function and Configuration 18.1.1 Standby function The standby function is mounted onto all 78K0/Fx2 microcontroller products. The standby function is designed to reduce the operating current of the system. The following two modes are available.
  • Page 620 CHAPTER 18 STANDBY FUNCTION (1) Oscillation stabilization time counter status register (OSTC) This is the register that indicates the count status of the X1 clock oscillation stabilization time counter. When X1 clock oscillation starts with the internal high-speed oscillation clock or subsystem clock used as the CPU clock, the X1 clock oscillation stabilization time can be checked.
  • Page 621 CHAPTER 18 STANDBY FUNCTION (2) Oscillation stabilization time select register (OSTS) This register is used to select the X1 clock oscillation stabilization time when the STOP mode is released. When the X1 clock is selected as the CPU clock, the operation waits for the time set using OSTS after the STOP mode is released.

  • Page 622: Standby Function Operation

    CHAPTER 18 STANDBY FUNCTION 18.2 Standby Function Operation 18.2.1 HALT mode (1) HALT mode The HALT mode is set by executing the HALT instruction. HALT mode can be set regardless of whether the CPU clock before the setting was the high-speed system clock, internal high-speed oscillation Clock, or subsystem clock.
  • Page 623 CHAPTER 18 STANDBY FUNCTION Table 18-1. Operating Statuses in HALT Mode (1/2) HALT Mode Setting When HALT Instruction Is Executed While CPU Is Operating on Main System Clock When CPU Is Operating on When CPU Is Operating on When CPU Is Operating on Internal High-Speed X1 Clock (f External Main System Clock...
  • Page 624 CHAPTER 18 STANDBY FUNCTION Table 18-1. Operating Statuses in HALT Mode (2/2) HALT Mode Setting When HALT Instruction Is Executed While CPU Is Operating on Subsystem Clock When CPU Is Operating on XT1 Clock (f When CPU Is Operating on External Subsystem Clock (f Item EXCLKS...
  • Page 625 CHAPTER 18 STANDBY FUNCTION (2) HALT mode release The HALT mode can be released by the following two sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgement is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgement is disabled, the next address instruction is executed.
  • Page 626 CHAPTER 18 STANDBY FUNCTION (b) Release by reset signal generation When the reset signal is generated, HALT mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address. Figure 18-4.

  • Page 627: Stop Mode

    CHAPTER 18 STANDBY FUNCTION Table 18-2. Operation in Response to Interrupt Request in HALT Mode Release Source MK×× PR×× Operation Maskable interrupt × Next address request instruction execution × Interrupt servicing execution Next address instruction execution × Interrupt servicing execution ×...
  • Page 628 CHAPTER 18 STANDBY FUNCTION Table 18-3. Operating Statuses in STOP Mode STOP Mode Setting When STOP Instruction Is Executed While CPU Is Operating on Main System Clock When CPU Is Operating on When CPU Is Operating on When CPU Is Operating on Internal High-Speed X1 Clock (f External Main System Clock...
  • Page 629 CHAPTER 18 STANDBY FUNCTION Cautions 1. To use the peripheral hardware that stops operation in the STOP mode, and the peripheral hardware for which the clock that stops oscillating in the STOP mode after the STOP mode is released, restart the peripheral hardware. 2.
  • Page 630 CHAPTER 18 STANDBY FUNCTION (2) STOP mode release Figure 18-5. Operation Timing When STOP Mode Is Released (When Unmasked Interrupt Request Is Generated) STOP mode release STOP mode High-speed system clock (X1 oscillation) High-speed system clock (external clock input) Internal high-speed oscillation clock Wait for oscillation accuracy μ...
  • Page 631 CHAPTER 18 STANDBY FUNCTION (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the STOP mode is released. After the oscillation stabilization time has elapsed, if interrupt acknowledgment is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgment is disabled, the next address instruction is executed. Figure 18-6.
  • Page 632 CHAPTER 18 STANDBY FUNCTION Figure 18-6. STOP Mode Release by Interrupt Request Generation (2/2) (2) When high-speed system clock (external clock input) is used as CPU clock (2/2) • When AMPH = 0 Interrupt request STOP instruction Standby release signal Normal operation Normal operation (high-speed...
  • Page 633 CHAPTER 18 STANDBY FUNCTION (b) Release by reset signal generation When the reset signal is generated, STOP mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address. Figure 18-7.

  • Page 634: Chapter 19 Reset Function

    CHAPTER 19 RESET FUNCTION The reset function is mounted onto all 78K0/Fx2 microcontroller products. The following four operations are available to generate a reset signal. (1) External reset input via RESET pin (2) Internal reset by watchdog timer program loop detection (3) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit (4) Internal reset by comparison of supply voltage and detection voltage of low-power-supply detector (LVI) External and internal resets have no functional differences.
  • Page 635 Figure 19-1. Block Diagram of Reset Function Internal bus Reset control flag register (RESF) WDTRF LVIRF Watchdog timer reset signal Clear Clear RESF register read signal Reset signal to LVIM/LVIS register RESET Power-on-clear circuit reset signal Reset signal Low-voltage detector reset signal Caution An LVI circuit internal reset does not reset the LVI circuit.
  • Page 636 CHAPTER 19 RESET FUNCTION Figure 19-2. Timing of Reset by RESET Input Wait for oscillation accuracy stabilization μ (86 to 361 s) Internal high-speed oscillation clock Starting X1 oscillation is specified by software. High-speed system clock (when X1 oscillation is selected) Reset processing Normal operation...
  • Page 637 CHAPTER 19 RESET FUNCTION Figure 19-4. Timing of Reset in STOP Mode by RESET Input Wait for oscillation accuracy stabilization STOP instruction execution μ (86 to 361 s) Internal high-speed oscillation clock Starting X1 oscillation is specified by software. High-speed system clock (when X1 oscillation is selected) Reset processing...
  • Page 638 CHAPTER 19 RESET FUNCTION Table 19-1. Operation Statuses During Reset Period Item During Reset Period System clock Clock supply to the CPU is stopped. Main system clock Operation stopped Operation stopped (pin is I/O port mode) Clock input invalid (pin is I/O port mode) EXCLK Subsystem clock Operation stopped (pin is I/O port mode)
  • Page 639 CHAPTER 19 RESET FUNCTION Table 19-2. Hardware Statuses After Reset Acknowledgment (1/3) Hardware After Reset Note 1 Acknowledgment Program counter (PC) The contents of the reset vector table (0000H, 0001H) are set. Stack pointer (SP) Undefined Program status word (PSW) Note 2 Data memory Undefined...
  • Page 640 CHAPTER 19 RESET FUNCTION Table 19-2. Hardware Statuses After Reset Acknowledgment (2/3) Hardware Status After Reset Note 1 Acknowledgment 16-bit timer/event Timer counters 00-03 (TM00-TM03) 0000H counters 00-03 Capture/compare registers 000-003, 010-013(CR000-CR003, CR010-CR013) 0000H Mode control registers 00-03 (TMC00-TMC03) Prescaler mode registers 00-03 (PRM00-PRM03) Capture/compare control registers 00-03 (CRC00-CRC03) Timer output control registers 00-03 (TOC00- TOC03) 8-bit timer/event...
  • Page 641 CHAPTER 19 RESET FUNCTION Table 19-2. Hardware Statuses After Reset Acknowledgment (3/3) Hardware Status After Reset Note 1 Acknowledgment Serial interfaces CSI10, Transmit buffer registers 10, 11 (SOTB10, SOTB11) CSI11 Serial I/O shift registers 10, 11 (SIO10, SIO11) Serial operation mode registers 10, 11 (CSIM10, CSIM11) Serial clock selection registers 10, 11 (CSIC10, CSIC11) Multiplier/divider Remainder data register 0 (SDR0)

  • Page 642: Register For Confirming Reset Source

    CHAPTER 19 RESET FUNCTION 19.1 Register for Confirming Reset Source Many internal reset generation sources exist in the 78K0/Fx2 microcontrollers. The reset control flag register (RESF) is used to store which source has generated the reset request. RESF can be read by an 8-bit memory manipulation instruction. RESET input, reset input by power-on-clear (POC) circuit, and reading RESF clear RESF to 00H.

  • Page 643: Chapter 20 Multiplier/Divider

    CHAPTER 20 MULTIPLIER/DIVIDER 20.1 Functions of Multiplier/Divider The multiplier/divider is mounted onto all 78K0/Fx2 microcontroller products. The multiplier/divider has the following functions. • 16 bits × 16 bits = 32 bits (multiplication) • 32 bits ÷ 16 bits = 32 bits, 16-bit remainder (division) 20.2 Configuration of Multiplier/Divider The multiplier/divider includes the following hardware.
  • Page 644 Figure 20-1. Block Diagram of Multiplier/Divider Internal bus Multiplier/divider control register 0 (DMUC0) Multiplication/division data register B0 Remainder data register 0 Multiplication/division data register A0 DMUSEL0 DMUE (MDB0 (MDB0H + MDB0L) (SDR0 (SDR0H + SDR0L) (MDA0H (MDA0HH + MDA0HL) + MDA0L (MDA0LH + MDA0LL) ) Start MDA000 INTDMU...
  • Page 645 CHAPTER 20 MULTIPLIER/DIVIDER (1) Remainder data register 0 (SDR0) SDR0 is a 16-bit register that stores a remainder. This register stores 0 in the multiplication mode and the remainder of an operation result in the division mode. SDR0 can be read by an 8-bit or 16-bit memory manipulation instruction. Reset signal generation clears SDR0 to 0000H.
  • Page 646 CHAPTER 20 MULTIPLIER/DIVIDER The functions of MDA0 when an operation is executed are shown in the table below. Table 20-2. Functions of MDA0 During Operation Execution DMUSEL0 Operation Mode Setting Operation Result Division mode Dividend Division result (quotient) Multiplication mode Higher 16 bits: 0, Lower 16 Multiplication result bits: Multiplier A...

  • Page 647: Register Controlling Multiplier/Divider

    CHAPTER 20 MULTIPLIER/DIVIDER 20.3 Register Controlling Multiplier/Divider The multiplier/divider is controlled by multiplier/divider control register 0 (DMUC0). (1) Multiplier/divider control register 0 (DMUC0) DMUC0 is an 8-bit register that controls the operation of the multiplier/divider. DMUC0 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears DMUC0 to 00H.

  • Page 648: Operations Of Multiplier/Divider

    CHAPTER 20 MULTIPLIER/DIVIDER 20.4 Operations of Multiplier/Divider 20.4.1 Multiplication operation • Initial setting 1. Set operation data to multiplication/division data register A0L (MDA0L) and multiplication/division data register B0 (MDB0). 2. Set bits 0 (DMUSEL0) and 7 (DMUE) of multiplier/divider control register 0 (DMUC0) to 1. Operation will start. •...
  • Page 649 Figure 20-6. Timing Chart of Multiplication Operation (00DAH × 0093H) Operation clock DMUE DMUSEL0 Internal clock Counter XXXX 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 SDR0 0000 0049 0024 005B 0077 003B 0067...

  • Page 650: Division Operation

    CHAPTER 20 MULTIPLIER/DIVIDER 20.4.2 Division operation • Initial setting 1. Set operation data to multiplication/division data register A0 (MDA0L and MDA0H) and multiplication/division data register B0 (MDB0). 2. Set bits 0 (DMUSEL0) and 7 (DMUE) of multiplier/divider control register 0 (DMUC0) to 0 and 1, respectively. Operation will start.
  • Page 651 Figure 20-7. Timing Chart of Division Operation (DCBA2586H ÷ 0018H) Operation clock DMUE DMUSEL0 “0” Internal clock 1B 1C 1D 1E Counter XXXX 0000 0001 0003 0006 000D 0003 0007 000E 0004 000B 0016 0014 0010 0008 0011 000B 0016 SDR0 B974 72E8...

  • Page 652: Chapter 21 Power-On-Clear Circuit

    CHAPTER 21 POWER-ON-CLEAR CIRCUIT 21.1 Functions of Power-on-Clear Circuit The power-on-clear circuit (POC) is mounted onto all 78K0/Fx2 microcontroller products. The power-on-clear circuit has the following functions. • Generates internal reset signal at power on. In the 1.59 V POC mode (option byte: LVISTART = 0), the reset signal is released when the supply voltage ) exceeds 1.59 V ±0.15 V.

  • Page 653: Configuration Of Power-On-Clear Circuit

    CHAPTER 21 POWER-ON-CLEAR CIRCUIT 21.2 Configuration of Power-on-Clear Circuit The block diagram of the power-on-clear circuit is shown in Figure 21-1. Figure 21-1. Block Diagram of Power-on-Clear Circuit Internal reset signal − Reference voltage source 21.3 Operation of Power-on-Clear Circuit (1) In 1.59 V POC mode (option byte: LVISTART = 0) •...
  • Page 654 CHAPTER 21 POWER-ON-CLEAR CIRCUIT Figure 21-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit and Low-Voltage Detector (1/2) (1) In 1.59 V POC mode (option byte: LVISTART = 0) Set LVI to be Set LVI to be Set LVI to be used for reset used for interrupt used for reset...
  • Page 655 CHAPTER 21 POWER-ON-CLEAR CIRCUIT Figure 21-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit and Low-Voltage Detector (2/2) (2) In 2.7 V / 1.59V POC mode (option byte: LVISTART = 1) Set LVI to be Set LVI to be Set LVI to be used for reset used for interrupt...

  • Page 656: Cautions For Power-On-Clear Circuit

    CHAPTER 21 POWER-ON-CLEAR CIRCUIT 21.4 Cautions for Power-on-Clear Circuit In a system where the supply voltage (V ) fluctuates for a certain period in the vicinity of the POC detection voltage (V ), the system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action.
  • Page 657 CHAPTER 21 POWER-ON-CLEAR CIRCUIT Figure 21-3. Example of Software Processing After Release of Reset (2/2) • Checking reset cause Check reset cause WDTRF of RESF register = 1? Reset processing by watchdog timer LVIRF of RESF register = 1? Reset processing by low-voltage detector Power-on-clear/external reset generated...

  • Page 658: Chapter 22 Low-Voltage Detector

    CHAPTER 22 LOW-VOLTAGE DETECTOR 22.1 Functions of Low-Voltage Detector The low-voltage detector (LVI) is mounted onto all 78K0/Fx2 microcontroller products. The low-voltage detector has the following functions. • The LVI circuit compares the supply voltage (V ) with the detection voltage (V ) or the input voltage from an external input pin (EXLVI) with the detection voltsage (V = 1.21 V (TYP.): fixed), and generates an internal...

  • Page 659: Configuration Of Low-Voltage Detector

    CHAPTER 22 LOW-VOLTAGE DETECTOR 22.2 Configuration of Low-Voltage Detector The block diagram of the low-voltage detector is shown in Figure 22-1. Figure 22-1. Block Diagram of Low-Voltage Detector N-ch Internal reset signal EXLVI/P120/ INTP0 − INTLVI Reference voltage source Low-voltage detection level Low-voltage detection register selection register (LVIS) (LVIM)
  • Page 660 CHAPTER 22 LOW-VOLTAGE DETECTOR (1) Low-voltage detection register (LVIM) This register sets low-voltage detection and the operation mode. This register can be set by a 1-bit or 8-bit memory manipulation instruction. The generation of a reset signal other than an LVI reset clears this register to 00H. Figure 22-2.
  • Page 661 CHAPTER 22 LOW-VOLTAGE DETECTOR Cautions 1. To stop LVI, follow either of the procedures below. • When using 8-bit memory manipulation instruction: Write 00H to LVIM. • When using 1-bit memory manipulation instruction: Clear LVION to 0. 2. Input voltage from external input pin (EXLVI) must be EXLVI < V 3.

  • Page 662: Operation Of Low-Voltage Detector

    CHAPTER 22 LOW-VOLTAGE DETECTOR (3) Port mode register 12 (PM12) When using the P120/EXLVI/INTP0 pin for external low-voltage detection potential input, set PM120 to 1. At this time, the output latch of P120 may be 0 or 1. PM12 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets PM12 to FFH.

  • Page 663: When Used As Reset

    CHAPTER 22 LOW-VOLTAGE DETECTOR 22.4.1 When used as reset (1) When detecting level of supply voltage (V • When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Clear bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 0 (detects level of supply voltage )) (default value).
  • Page 664 CHAPTER 22 LOW-VOLTAGE DETECTOR Figure 22-5. Timing of Low-Voltage Detector Internal Reset Signal Generation (Detects Level of Supply Voltage (V )) (1/2) (1) In 1.59 V POC mode setup (option byte: LVISTART = 0) Supply voltage (V = 1.59 V (TYP.) Time LVIMK flag Note1...
  • Page 665 CHAPTER 22 LOW-VOLTAGE DETECTOR Figure 22-5. Timing of Low-Voltage Detector Internal Reset Signal Generation (Detects Level of Supply Voltage (V )) (2/2) (2) In 2.7/1.59 V POC mode setup (option byte: LVISTART = 1) Supply voltage (V 2.7 V (TYP.) = 1.59 V (TYP.) Time LVIMK flag...
  • Page 666 CHAPTER 22 LOW-VOLTAGE DETECTOR (2) When detecting level of input voltage from external input pin (EXLVI) • When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Set bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 1 (detects level of input voltage from external input pin (EXLVI)).
  • Page 667 CHAPTER 22 LOW-VOLTAGE DETECTOR Figure 22-6. Timing of Low-Voltage Detector Internal Reset Signal Generation (Detects Level of Input Voltage from External Input Pin (EXLVI)) Input voltage from external input pin (EXLVI) LVI detection voltage EXLVI Time LVIMK flag Note 1 (set by software) <1>...

  • Page 668: When Used As Interrupt

    CHAPTER 22 LOW-VOLTAGE DETECTOR 22.4.2 When used as interrupt (1) When detecting level of supply voltage (V • When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Clear bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 0 (detects level of supply voltage )) (default value).
  • Page 669 CHAPTER 22 LOW-VOLTAGE DETECTOR Figure 22-7. Timing of Low-Voltage Detector Interrupt Signal Generation (Detects Level of Supply Voltage (V )) (1/2) (1) In 1.59 V POC mode setup (option byte: LVISTART = 0) Supply voltage (V = 1.59 V (TYP.) Note 3 Note 3 Time...
  • Page 670 CHAPTER 22 LOW-VOLTAGE DETECTOR Figure 22-7. Timing of Low-Voltage Detector Interrupt Signal Generation (Detects Level of Supply Voltage (V )) (2/2) (2) In 2.7/1.59 V POC mode setup (option byte: LVISTART = 1) Supply voltage (V 2.7 V(TYP.) = 1.59 V (TYP.) Note 3 Note 3 Time...
  • Page 671 CHAPTER 22 LOW-VOLTAGE DETECTOR (2) When detecting level of input voltage from external input pin (EXLVI) • When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Set bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 1 (detects level of input voltage from external input pin (EXLVI)).
  • Page 672 CHAPTER 22 LOW-VOLTAGE DETECTOR Figure 22-8. Timing of Low-Voltage Detector Interrupt Signal Generation (Detects Level of Input Voltage from External Input Pin (EXLVI)) Input voltage from external input pin (EXLVI) EXLVI Note 3 Note 3 Time LVIMK flag (set by software) <1>...

  • Page 673: Cautions For Low-Voltage Detector

    CHAPTER 22 LOW-VOLTAGE DETECTOR 22.5 Cautions for Low-Voltage Detector In a system where the supply voltage (V ) fluctuates for a certain period in the vicinity of the LVI detection voltage ), the operation is as follows depending on how the low-voltage detector is used. (1) When used as reset The system may be repeatedly reset and released from the reset status.
  • Page 674 CHAPTER 22 LOW-VOLTAGE DETECTOR Figure 22-9. Example of Software Processing After Reset Release (1/2) • If supply voltage fluctuation is 50 ms or less in vicinity of LVI detection voltage Reset Note Check the reset source Initialization Initialize the port. processing <1>...
  • Page 675 CHAPTER 22 LOW-VOLTAGE DETECTOR Figure 22-9. Example of Software Processing After Reset Release (2/2) • Checking reset cause Check reset source Yes: Reset generation by LVI LVION of LVIM register = 1? No: Reset generation other than by LVI Set LVI (Set LVIM and LVIS registers) User’s Manual U19180EJ1V0UD...

  • Page 676: Chapter 23 Option Byte

    CHAPTER 23 OPTION BYTE 23.1 Functions of Option Bytes The flash memory at 0080H to 0084H of the 78K0/Fx2 microcontrollers are an option byte area. When power is turned on or when the device is restarted from the reset status, the device automatically references the option bytes and sets specified functions.
  • Page 677 CHAPTER 23 OPTION BYTE (3) 0084H/1084H On-chip debug operation control • Disabling on-chip debug operation • Enabling on-chip debug operation and erasing data of the flash memory in case authentication of the on- chip debug security ID fails • Enabling on-chip debug operation and not erasing data of the flash memory even in case authentication of the on-chip debug security ID fails Caution To use the on-chip debug function, set 02H or 03H to 0084H.

  • Page 678: Format Of Option Byte

    CHAPTER 23 OPTION BYTE 23.2 Format of Option Byte The format of the option byte is shown below. Figure 23-1. Format of Option Byte (1/2) Note Address: 0080H/1080H WINDOW1 WINDOW0 WDTON WDCS2 WDCS1 WDCS0 LSROSC WINDOW1 WINDOW0 Watchdog timer window open period 100% WDTON Operation control of watchdog timer counter/illegal access detection...
  • Page 679 CHAPTER 23 OPTION BYTE Figure 23-1. Format of Option Byte (2/2) Notes 1, 2 Address: 0081H/1081H LVISTART LVISTART POC mode selection 1.59 V POC mode (default) 2.7 V/1.59 V POC mode Notes 1. LVISTART can only be written by using a dedicated flash memory programmer. It cannot be set during self-programming or boot swap operation during self-programming (at this time, 1.59 V POC mode (default) is set).
  • Page 680 CHAPTER 23 OPTION BYTE Here is an example of description of the software for setting the option bytes. CSEG AT 0080H OPTION: DB ; Enables watchdog timer operation (illegal access detection operation), ; Window open period of watchdog timer: 50%, ;...

  • Page 681: Chapter 24 Flash Memory

    CHAPTER 24 FLASH MEMORY The 78K0/Fx2 microcontrollers incorporates the flash memory to which a program can be written, erased, and overwritten while mounted on the board. 24.1 Internal Memory Size Switching Register The internal memory capacity can be selected using the internal memory size switching register (IMS). IMS is set by an 8-bit memory manipulation instruction.

  • Page 682: Internal Expansion Ram Size Switching Register

    CHAPTER 24 FLASH MEMORY 24.2 Internal Expansion RAM Size Switching Register The internal expansion RAM capacity can be selected using the internal expansion RAM size switching register (IXS). IXS is set by an 8-bit memory manipulation instruction. Reset signal generation sets IXS to 0CH. Caution Be sure to set each product to the values shown in Table 24-2 after a reset release.

  • Page 683: Writing With Flash Memory Programmer

    CHAPTER 24 FLASH MEMORY 24.3 Writing with Flash Memory Programmer Data can be written to the flash memory on-board or off-board, by using a dedicated flash memory programmer. (1) On-board programming The contents of the flash memory can be rewritten after the 78K0/Fx2 microcontrollers have been mounted on the target system.
  • Page 684 CHAPTER 24 FLASH MEMORY Examples of the recommended connection when using the adapter for flash memory writing are shown below. Figure 24-3. Example of Wiring Adapter for Flash Memory Writing in 3-Wire Serial I/O (CSI10) Mode μ PD78F0881A, 78F0882A, 78F0883A of 78K0/FC2) (2.7 to 5.5 V) 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22...
  • Page 685 CHAPTER 24 FLASH MEMORY Figure 23-4. Example of Wiring Adapter for Flash Memory Writing in UART (UART60) Mode μ PD78F0881A, 78F0882A, 78F0883A of 78K0/FC2) (2.7 to 5.5 V) 44 43 42 41 40 39 38 37 36 35 34 Note 12 13 14 15 16 17 18 19 20 21 22 Note /RESET...
  • Page 686 CHAPTER 24 FLASH MEMORY Table 23-4. Wiring Between 78K0/FC2 and Dedicated Flash Memory Programmer μ PD78F0884A, 78F0885A, 78F0886A, 78F0894A, 78F0895A) Pin Configuration of Dedicated Flash Memory Programmer With CSI10 With UART60 Signal Name Pin Function Pin Name Pin No. Pin Name Pin No.
  • Page 687 CHAPTER 24 FLASH MEMORY Examples of the recommended connection when using the adapter for flash memory writing are shown below. Figure 24-5. Example of Wiring Adapter for Flash Memory Writing in 3-Wire Serial I/O (CSI10) Mode μ PD78F0884A, 78F0885A, 78F0886A, 78F0894A, 78F0895A of 78K0/FC2) (2.7 to 5.5 V) 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24...
  • Page 688 CHAPTER 24 FLASH MEMORY Figure 24-6. Example of Wiring Adapter for Flash Memory Writing in UART (UART60) Mode μ PD78F0884A, 78F0885A, 78F0886A, 78F0894A, 78F0895A of 78K0/FC2) (2.7 to 5.5 V) 48 47 46 45 44 43 42 41 40 39 38 37 Note 13 14 15 16 17 18 19 20 21 22 23 24 Note...
  • Page 689 CHAPTER 24 FLASH MEMORY Table 24-5. Wiring Between 78K0/FE2 and Dedicated Flash Memory Programmer Pin Configuration of Dedicated Flash Memory Programmer With CSI10 With UART60 Signal Name Pin Function Pin Name Pin No. Pin Name Pin No. SI/RxD Input Receive signal SO10/P12 TxD60/P13 SO/TxD...
  • Page 690 CHAPTER 24 FLASH MEMORY Examples of the recommended connection when using the adapter for flash memory writing are shown below. Figure 24-7. Example of Wiring Adapter for Flash Memory Writing in 3-Wire Serial I/O (CSI10) Mode (78K0/FE2) (2.3 to 5.5 V) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 /RESET FLMD0...
  • Page 691 CHAPTER 24 FLASH MEMORY Figure 24-8. Example of Wiring Adapter for Flash Memory Writing in UART (UART60) Mode (78K0/FE2) (2.3 to 5.5 V) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Note 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Note /RESET FLMD0...
  • Page 692 CHAPTER 24 FLASH MEMORY Table 24-6. Wiring Between 78K0/FF2 and Dedicated Flash Memory Programmer Pin Configuration of Dedicated Flash Memory Programmer With CSI10 With UART60 Signal Name Pin Function Pin Name Pin No. Pin Name Pin No. SI/RxD Input Receive signal SO10/P12 TxD60/P13 SO/TxD...
  • Page 693 CHAPTER 24 FLASH MEMORY Examples of the recommended connection when using the adapter for flash memory writing are shown below. Figure 24-9. Example of Wiring Adapter for Flash Memory Writing in 3-Wire Serial I/O (CSI10) Mode (78K0/FF2) (2.7 to 5.5 V) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 VDD2...
  • Page 694 CHAPTER 24 FLASH MEMORY Figure 24-10. Example of Wiring Adapter for Flash Memory Writing in UART (UART60) Mode (78K0/FF2) (2.7 to 5.5 V) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 Note 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 VDD2...

  • Page 695: Programming Environment

    CHAPTER 24 FLASH MEMORY 24.4 Programming Environment The environment required for writing a program to the flash memory of the 78K0/Fx2 microcontrollers are illustrated below. Figure 24-11. Environment for Writing Program to Flash Memory POWER FLMD0 RS-232C PASS BUSY START RESET PG-FP5 78K0/Fx2...
  • Page 696 CHAPTER 24 FLASH MEMORY (2) UART60 Transfer rate: 115200 bps Figure 24-13. Communication with Dedicated Flash Memory Programmer (UART60) FLMD0 FLMD0 POWER PASS BUSY /RESET RESET START PG-FP5 SI/RxD TxD60 78K0/Fx2 SO/TxD RxD60 Dedicated flash microcontrollers Note Note EXCLK memory programmer Note The above figure illustrates an example of wiring when using the clock output from the PG-FP5, FL-PR5, PG-FP4 or FL-PR4.

  • Page 697: Connection Of Pins On Board

    CHAPTER 24 FLASH MEMORY 24.6 Connection of Pins on Board To write the flash memory on-board, connectors that connect the dedicated flash memory programmer must be provided on the target system. First provide a function that selects the normal operation mode or flash memory programming mode on the board.
  • Page 698 CHAPTER 24 FLASH MEMORY (1) Signal collision If the dedicated flash memory programmer (output) is connected to a pin (input) of a serial interface connected to another device (output), signal collision takes place. To avoid this collision, either isolate the connection with the other device, or make the other device go into an output high-impedance state.

  • Page 699: Reset Pin

    CHAPTER 24 FLASH MEMORY 24.6.3 RESET pin If the reset signal of the dedicated flash memory programmer is connected to the RESET pin that is connected to the reset signal generator on the board, signal collision takes place. To prevent this collision, isolate the connection with the reset signal generator.

  • Page 700: Power Supply

    CHAPTER 24 FLASH MEMORY 24.6.7 Power supply To use the supply voltage output of the flash memory programmer, connect the V pin to V of the flash memory programmer, and the V pin to GND of the flash memory programmer. To use the on-board supply voltage, connect in compliance with the normal operation mode.

  • Page 701: Programming Method

    CHAPTER 24 FLASH MEMORY 24.7 Programming Method 24.7.1 Controlling flash memory The following figure illustrates the procedure to manipulate the flash memory. Figure 24-18. Flash Memory Manipulation Procedure Start Flash memory programming mode is set FLMD0 pulse supply Selecting communication mode Manipulate flash memory End? 24.7.2 Flash memory programming mode...

  • Page 702: Selecting Communication Mode

    CHAPTER 24 FLASH MEMORY Table 24-9. Relationship Between FLMD0 Pin and Operation Mode After Reset Release FLMD0 Operation Mode Normal operation mode Flash memory programming mode 24.7.3 Selecting communication mode In the 78K0/Fx2 microcontrollers, a communication mode is selected by inputting pulses (up to 8 pulses) to the FLMD0 pin after the dedicated flash memory programming mode is entered.

  • Page 703: Communication Commands

    CHAPTER 24 FLASH MEMORY 24.7.4 Communication commands The 78K0/Fx2 microcontrollers communicate with the dedicated flash memory programmer by using commands. The signals sent from the flash memory programmer to the 78K0/Fx2 microcontrollers are called commands, and the signals sent from the 78K0/Fx2 microcontrollers to the dedicated flash memory programmer are called response. Figure 24-20.

  • Page 704: Security Settings

    CHAPTER 24 FLASH MEMORY 24.8 Security Settings The 78K0/Fx2 microcontrollers support a security function that prohibits rewriting the user program written to the internal flash memory, so that the program cannot be changed by an unauthorized person. The operations shown below can be performed using the security set command. The security setting is valid when the programming mode is set next.
  • Page 705 CHAPTER 24 FLASH MEMORY Table 24-13. Relationship Between Enabling Security Function and Command (1) During on-board/off-board programming Valid Security Executed Command Batch Erase (Chip Erase) Block Erase Write Note Prohibition of batch erase (chip erase) Cannot be erased in batch Blocks cannot be Can be performed erased.

  • Page 706: Processing Time For Each Command When Pg-Fp4 Or Pg-Fp5 Is Used (Reference)

    CHAPTER 24 FLASH MEMORY 24.9 Processing Time for Each Command When PG-FP4 or PG-FP5 Is Used (Reference) The following table shows the processing time for each command (reference) when the PG-FP4 or PG-FP5 is used as a dedicated flash memory programmer. Table 24-15.
  • Page 707 CHAPTER 24 FLASH MEMORY Table 24-15. Processing Time for Each Command When PG-FP4 or PG-FP5 Is Used (Reference) (2/2) μ PD78F0890A, 78F0893A, 78F0895A (internal ROM capacity: 128 KB) Command of Port: CSI-Internal-OSC Port: UART-Ext-FP4CK (External main system clock (f EXCLK PG-FP4 or (Internal high-speed Speed: 115,200 bps...

  • Page 708: Flash Memory Programming By Self-Programming

    CHAPTER 24 FLASH MEMORY 24.10 Flash Memory Programming by Self-Programming The 78K0/Fx2 microcontrollers support a self-programming function that can be used to rewrite the flash memory via a user program. Because this function allows a user application to rewrite the flash memory by using the 78K0/Fx2 self-programming library, it can be used to upgrade the program in the field.
  • Page 709 CHAPTER 24 FLASH MEMORY Cautions 6. Allocate the entry program for self-programming in the common area of 0000H to 7FFFH. Figure 24-21. Operation Mode and Memory Map for Self-Programming μ PD78F0883A, 78F0886A F F F F H F F F F H F F 0 0 H F F 0 0 H F E F F H...
  • Page 710 CHAPTER 24 FLASH MEMORY Table 24-16. Correspondence Among Bank Numbers, CPU Addresses, and Flash Real Addresses μ PD78F0889A, 78F0892A, 78F0894A Bank No. CPU Address Real Address of Flash Memory − 0000H to 7FFFH (common area) 00000H to 07FFFH 8000H to BFFFH 08000H to 0BFFFH 0C000H to 0FFFFH 10000H to 13FFFH...
  • Page 711 CHAPTER 24 FLASH MEMORY The following figure illustrates a flow of rewriting the flash memory by using a self programming library. Figure 24-22. Flow of Self-Programming (Rewriting Flash Memory) Start of self programming FLMD0 pin Low level → High level FlashStart Setting operating environment FlashEnv...
  • Page 712 CHAPTER 24 FLASH MEMORY The following table shows the processing time and interrupt response time for the self programming sample library. Table 24-17. Processing Time for Self Programming Library (1/3) (1) When internal high-speed oscillation clock is used and entry RAM is located outside short direct addressing range μ...
  • Page 713 CHAPTER 24 FLASH MEMORY Table 24-17. Processing Time for Self Programming Library (2/3) (3) When high-speed system clock (X1 oscillation or external clock input) is used and entry RAM is located outside short direct addressing range μ Library Name Processing Time ( Normal Model of C Compiler Static Model of C Compiler/Assembler Min.
  • Page 714 CHAPTER 24 FLASH MEMORY Table 24-17. Processing Time for Self Programming Library (3/3) (4) When high-speed system clock (X1 oscillation or external clock input) is used and entry RAM is located in short direct addressing range μ Library Name Processing Time ( Normal Model of C Compiler Static Model of C Compiler/Assembler Min.
  • Page 715 CHAPTER 24 FLASH MEMORY Table 24-18. Interrupt Response Time for Self Programming Library (1/2) (1) When internal high-speed oscillation clock is used μ Library Name Interrupt Response Time ( s (Max.)) Normal Model of C Compiler Static Model of C Compiler/Assembler Entry RAM location Entry RAM location Entry RAM location...
  • Page 716 CHAPTER 24 FLASH MEMORY Table 24-18. Interrupt Response Time for Self Programming Library (2/2) (3) When high-speed system clock is used (static model of C compiler/assembler) μ Library Name Interrupt Response Time ( s (Max.)) RSTOP = 0, RSTS = 1 RSTOP = 1 Entry RAM location Entry RAM location...

  • Page 717: Registers Used For Self-Programming Function

    CHAPTER 24 FLASH MEMORY 24.10.1 Registers used for self-programming function The following three registers are used for the self-programming function. • Flash-programming mode control register (FLPMC) • Flash protect command register (PFCMD) • Flash status register (PFS) (1) Flash-programming mode control register (FLPMC) This register is used to enable or disable writing or erasing of the flash memory and to set the operation mode during self-programming.
  • Page 718 CHAPTER 24 FLASH MEMORY Figure 24-23. Format of Flash-Programming Mode Control Register (FLPMC) Note 1 Note 2 Address: FFC4H After reset: 0×H Symbol FLPMC FWEDIS FWEPR FLSPM1 FLSPM0 FWEDIS Control of flash memory writing/erasing Note 3 Writing/erasing enabled Writing/erasing disabled FWEPR Status of FLMD0 pin Low level...
  • Page 719 CHAPTER 24 FLASH MEMORY (2) Flash protect command register (PFCMD) If the application system stops inadvertently due to malfunction caused by noise or program hang-up, an operation to write the flash programming mode control register (FLPMC) may have a serious effect on the system. PFCMD is used to protect FLPMC from being written, so that the application system does not stop inadvertently.
  • Page 720 CHAPTER 24 FLASH MEMORY The operating conditions of the FPRERR flag are as follows. <Setting conditions> • If PFCMD is written when the store instruction operation recently performed on a peripheral register is not to write a specific value (A5H) to PFCMD •...

  • Page 721: Boot Swap Function

    CHAPTER 24 FLASH MEMORY 24.11 Boot Swap Function If rewriting the boot area has failed during self-programming due to a power failure or some other cause, the data in the boot area may be lost and the program may not be restarted by resetting. The boot swap function is used to avoid this problem.
  • Page 722 CHAPTER 24 FLASH MEMORY Figure 24-27. Example of Executing Boot Swapping Block number Erasing block 4 Erasing block 5 Erasing block 6 Erasing block 7 Program Program Program Program Boot Program Program Program cluster 1 Program Program Program 1 0 0 0 H Boot program Boot program Boot program...

  • Page 723: Chapter 25 On-Chip Debug Function

    CHAPTER 25 ON-CHIP DEBUG FUNCTION 25.1 Outline of Functions On-chip debug function is mounted onto all 78K0/Fx2 microcontroller products. The 78K0/Fx2 microcontrollers uses the V , FLMD0, RESET, X1 (or P31), X2 (or P32), and V pins to communicate with the host machine via an on-chip debug emulator (QB-78K0MINI or QB-MINI2). Whether X1 and P31, or X2 and P32 are used can be selected.

  • Page 724: Connection With Minicube Or Qb-Mini2

    CHAPTER 25 ON-CHIP DEBUG FUNCTION 25.2 Connection with MINICUBE or QB-MINI2 In order to connect QB-78K0MINI or QB-MINI2, it is necessary to mount the connector for emulator connection, and the circuit for connection on a target system. The connector for OCD (a two-row 2.54 pitch type connector, with reverse-insertion blocker) is described below. •...

  • Page 725: Connection Circuit Examples

    CHAPTER 25 ON-CHIP DEBUG FUNCTION 25.3 Connection Circuit Examples The following are examples of circuits required when connecting the QB-78K0MINI to the target system. Figure 25-2. Connection Example of QB-78K0MINI or QB-MINI2 and 78K0/Fx2 microcontrollers (When X1 and X2 Are Used) Reset circuit Target connector (10-pin)
  • Page 726 CHAPTER 25 ON-CHIP DEBUG FUNCTION Figure 25-3. Connection Example of QB-78K0MINI or QB-MINI2 and 78K0/Fx2 microcontrollers (When P31 and P32 Are Used) Reset circuit Target connector (10-pin) 3 to 10 kΩ 1 kΩ Reset signal Note 2 (Recommended) (Recommended) Note 1 RESET_IN 10 kΩ...

  • Page 727: Reserved Area Used By Qb-78K0Mini And Qb-Mini2

    CHAPTER 25 ON-CHIP DEBUG FUNCTION 25.4 Reserved Area Used by QB-78K0MINI and QB-MINI2 QB-78K0MINI and QB-MINI2 use the reserved areas shown in Figure 25-5 below to implement communication with the 78K0/Fx2 microcontrollers, or each debug function. The shaded reserved areas are used for the respective debug functions to be used, and the other areas are always used for debugging.

  • Page 728: On-Chip Debug Security Id

    CHAPTER 25 ON-CHIP DEBUG FUNCTION 25.5 On-Chip Debug Security ID The 78K0/Fx2 microcontrollers have an on-chip debug operation control flag in the flash memory at 0084H (see CHAPTER 23 OPTION BYTE) and an on-chip debug security ID setting area at 0085H to 008EH. When the boot swap function is used, also set a value that is the same as that of 1084H and 1085H to 108EH in advance, because 0084H, 0085H to 008EH and 1084H, and 1085H to 108EH are switched.

  • Page 729: Chapter 26 Instruction Set

    CHAPTER 26 INSTRUCTION SET This chapter lists each instruction set of 78K0/Fx2 microcontrollers in table form. For details of each operation and operation code, refer to the separate document 78K/0 Series Instructions User’s Manual (U12326E). 26.1 Conventions Used in Operation List 26.1.1 Operand identifiers and specification methods Operands are written in the “Operand”...

  • Page 730: Description Of Operation Column

    CHAPTER 26 INSTRUCTION SET 26.1.2 Description of operation column A register; 8-bit accumulator X register B register C register D register E register H register L register AX register pair; 16-bit accumulator BC register pair DE register pair HL register pair Program counter Stack pointer PSW:...

  • Page 731: Operation List

    CHAPTER 26 INSTRUCTION SET 26.2 Operation List Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 − r ← byte 8-bit data r, #byte transfer saddr, #byte (saddr) ← byte − sfr ← byte sfr, #byte Note 3 A ←...
  • Page 732 CHAPTER 26 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 16-bit data MOVW rp, #word − rp ← word transfer (saddrp) ← word saddrp, #word sfrp, #word − sfrp ← word AX ←...
  • Page 733 CHAPTER 26 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 8-bit A, #byte − A, CY ← A − byte × × × operation (saddr), CY ← (saddr) − byte × ×...
  • Page 734 CHAPTER 26 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 8-bit A, #byte − A ← A ∨ byte × operation (saddr) ← (saddr) ∨ byte × saddr, #byte Note 3 A, r −...
  • Page 735 CHAPTER 26 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 16-bit ADDW AX, #word − AX, CY ← AX + word × × × operation − AX, CY ← AX − word ×...
  • Page 736 CHAPTER 26 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 AND1 CY, saddr.bit CY ← CY ∧ saddr.bit) × manipulate − CY ← CY ∧ sfr.bit × CY, sfr.bit CY, A.bit −...
  • Page 737 CHAPTER 26 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 Call/return CALL !addr16 − (SP − 1) ← (PC + 3) , (SP − 2) ← (PC + 3) PC ← addr16, SP ← SP − 2 CALLF !addr11 −...
  • Page 738 CHAPTER 26 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 Conditional saddr.bit, $addr16 PC ← PC + 3 + jdisp8 if(saddr.bit) = 1 branch − PC ← PC + 4 + jdisp8 if sfr.bit = 1 sfr.bit, $addr16 A.bit, $addr16 −...

  • Page 739: Instructions Listed By Addressing Type

    CHAPTER 26 INSTRUCTION SET 26.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ Note Second Operand #byte saddr !addr16 [DE]...
  • Page 740 CHAPTER 26 INSTRUCTION SET (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Note Second Operand #word sfrp saddrp !addr16 None First Operand ADDW MOVW MOVW MOVW MOVW MOVW SUBW XCHW CMPW Note MOVW MOVW INCW DECW PUSH Sfrp MOVW...
  • Page 741 CHAPTER 26 INSTRUCTION SET (4) Call instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ Second Operand !addr16 !addr11 [addr5] $addr16 First Operand Basic instruction CALL CALLF CALLT Compound instruction BTCLR DBNZ (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP User’s Manual U19180EJ1V0UD...

  • Page 742: Chapter 27 Electrical Specifications ((A) Grade Products)

    CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) μ Target products: 78K0/FC2: PD78F0881A (A), 78F0882A (A), 78F0883A (A), 78F0884A (A), 78F885A (A), 78F0886A (A), 78F0894A (A), 78F895A (A) μ 78K0/FE2: PD78F0887A (A), 78F0888A (A), 78F0889A (A), 78F0890A (A) μ 78K0/FF2: PD78F0891A (A), 78F0892A (A), 78F0893A (A) Cautions 1.
  • Page 743 CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) grade products (2) Non-port functions Port 78K0/FC2 78K0/FE2 78K0/FF2 44 Pins 48 Pins 64 Pins 80 Pins Power supply, , EV , EV , AV , AV ground Regulator REGC Reset RESET Clock X1, X2, XT1, XT2, EXCLK, EXCLKS oscillation...

  • Page 744: Absolute Maximum Ratings

    CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) grade products Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. 27.1 Absolute Maximum Ratings Absolute Maximum Ratings (T = 25°C) (1/2) Parameter Symbol Conditions Ratings...
  • Page 745 CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) grade products Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. Absolute Maximum Ratings (T = 25°C) (2/2) Parameter Symbol Conditions Ratings Unit −10 Output current, high Per pin...

  • Page 746: Oscillator Characteristics

    CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) grade products Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. 27.2 Oscillator Characteristics (1) Main System Clock (Crystal/Ceramic) Oscillator Characteristics = −40 to +85°C, 1.8 V ≤ V ≤...
  • Page 747 CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) grade products Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. (2) On-chip Internal Oscillator Characteristics = −40 to +85°C, 1.8 V ≤ V ≤...

  • Page 748: Dc Characteristics

    CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) grade products Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. 27.3 DC Characteristics DC Characteristics (1/6) = −40 to +85°C, 1.8 V ≤ V ≤...
  • Page 749 CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) grade products Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. DC Characteristics (2/6) = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, V = EV = EV = AV...
  • Page 750 CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) grade products Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. DC Characteristics (3/6) = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, V = EV = EV = AV...
  • Page 751 CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) grade products Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. DC Characteristics (4/6) = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, V = EV = EV = AV...
  • Page 752 CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) grade products Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. DC Characteristics (5/6) = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, 2.3 V ≤ AV ≤...
  • Page 753 CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) grade products Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. DC Characteristics (6/6) = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, 2.3 V ≤ AV ≤...

  • Page 754: Ac Characteristics

    CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) grade products Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. 27.4 AC Characteristics (1) Basic operation = −40 to +85°C, 1.8 V ≤ V ≤...
  • Page 755 CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) grade products vs. V (Main System Clock Operation) 20.0 10.0 Guaranteed operation range (The gray portion is applicable only if AMPH = 1 is set.) Supply voltage V User’s Manual U19180EJ1V0UD...
  • Page 756 CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) grade products Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. AC Timing Test Points (Excluding X1, XT1) Test points External clock input timing EXTL EXTH 0.8V...
  • Page 757 CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) grade products Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. RESET Input Timing RESET (2) Serial interface = −40 to +85°C, 1.8 V ≤ V ≤...
  • Page 758 CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) grade products Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. Serial Transfer Timing 3-wire serial I/O mode: KCYm SCK1n SIKm KSIm SI1n Input data KSOm SO1n...
  • Page 759 CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) grade products Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. (3) CAN controller = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, V = EV = EV = AV...
  • Page 760 CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) grade products Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. (4) A/D Converter Characteristics = −40 to +85°C, 2.3 V ≤ V ≤...
  • Page 761 CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) grade products Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. (5) POC Circuit Characteristics = −40 to +85°C, V = 0 V) Parameter Symbol Conditions...
  • Page 762 CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) grade products Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. (6) LVI Circuit Characteristics = −40 to +85°C, V ≤ V ≤ 5.5 V, AV ≤...
  • Page 763 CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) grade products Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. (7) Power Supply Starting Time = −40 to +85°C, V = 0 V) Parameter Symbol Conditions...

  • Page 764: Data Retention Characteristics

    CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) grade products Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. 27.5 Data Retention Characteristics Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (T = −40 to +85°C) Parameter Symbol...

  • Page 765: Flash Eeprom Programming Characteristics

    CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) grade products Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. 27.6 Flash EEPROM Programming Characteristics (1) Basic characteristics = −40 to +85°C, 2.7 V ≤ V ≤...

  • Page 766: Chapter 28 Electrical Specifications ((A2) Grade Products)

    CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) μ Target products: 78K0/FC2: PD78F0881A (A2), 78F0882A (A2), 78F0883A (A2), 78F0884A (A2), 78F885A (A2), 78F0886A (A2), 78F0894A (A2), 78F895A (A2) μ 78K0/FE2: PD78F0887A (A2), 78F0888A (A2), 78F0889A (A2), 78F0890A (A2) μ 78K0/FF2: PD78F0891A (A2), 78F0892A (A2), 78F0893A (A2) Cautions 1.
  • Page 767 CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (A2) grade products (2) Non-port functions Port 78K0/FC2 78K0/FE2 78K0/FF2 44 Pins 48 Pins 64 Pins 80 Pins Power supply, , EV , EV , AV , AV ground Regulator REGC Reset RESET Clock X1, X2, XT1, XT2, EXCLK, EXCLKS oscillation...

  • Page 768: Absolute Maximum Ratings

    CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (A2) grade products Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. 28.1 Absolute Maximum Ratings Absolute Maximum Ratings (T = 25°C) (1/2) Parameter Symbol Conditions Ratings...
  • Page 769 CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (A2) grade products Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. Absolute Maximum Ratings (T = 25°C) (2/2) Parameter Symbol Conditions Ratings Unit Output current, low Per pin P00, P01, P05, P06,...

  • Page 770: Oscillator Characteristics

    CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (A2) grade products Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. 28.2 Oscillator Characteristics (1) Main System Clock (Crystal/Ceramic) Oscillator Characteristics = −40 to +125°C, 2.7 V ≤ V ≤...
  • Page 771 CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (A2) grade products Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. (2) On-chip Internal Oscillator Characteristics = −40 to +125°C, 2.7 V ≤ V ≤...

  • Page 772: Dc Characteristics

    CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (A2) grade products Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. 28.3 DC Characteristics DC Characteristics (1/6) = −40 to +125°C, 2.7 V ≤ V ≤...
  • Page 773 CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (A2) grade products Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. DC Characteristics (2/6) = −40 to +125°C, 2.7 V ≤ V ≤ 5.5 V, V = EV = EV = AV...
  • Page 774 CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (A2) grade products Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. DC Characteristics (3/6) = −40 to +125°C, 2.7 V ≤ V ≤ 5.5 V, V = EV = EV = AV...
  • Page 775 CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (A2) grade products Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. DC Characteristics (4/6) = −40 to +125°C, 2.7 V ≤ V ≤ 5.5 V, V = EV = EV = AV...
  • Page 776 CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (A2) grade products Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. DC Characteristics (5/6) = −40 to +125°C, 2.7 V ≤ V ≤ 5.5 V, 2.7 V ≤ AV ≤...
  • Page 777 CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (A2) grade products Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. DC Characteristics (6/6) = −40 to +125°C, 2.7 V ≤ V ≤ 5.5 V, AV ≤...

  • Page 778: Ac Characteristics

    CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (A2) grade products Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. 28.4 AC Characteristics (1) Basic operation = −40 to +125°C, 2.7 V ≤ V ≤...
  • Page 779 CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (A2) grade products vs. V (Main System Clock Operation) 20.0 10.0 Guaranteed operation range (The gray portion is applicable only if AMPH = 1 is set.) Supply voltage V User’s Manual U19180EJ1V0UD...
  • Page 780 CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (A2) grade products Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. AC Timing Test Points (Excluding X1, XT1) Test points External clock input timing EXTL EXTH 0.8V...
  • Page 781 CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (A2) grade products Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. RESET Input Timing RESET (2) Serial interface = −40 to +125°C, 2.7V ≤ V ≤...
  • Page 782 CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (A2) grade products Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. Serial Transfer Timing 3-wire serial I/O mode: KCYm SCK1n SIKm KSIm SI1n Input data KSOm SO1n...
  • Page 783 CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (A2) grade products Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. (3) CAN controller = −40 to +125°C, 2.7 V ≤ V ≤ 5.5 V, V = EV = EV = AV...
  • Page 784 CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (A2) grade products Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. (4) A/D Converter Characteristics = −40 to +125°C, 2.7 V ≤ V ≤...
  • Page 785 CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (A2) grade products Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. (5) POC Circuit Characteristics = −40 to +125°C, V = 0 V) Parameter Symbol Conditions...
  • Page 786 CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (A2) grade products Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. (6) LVI Circuit Characteristics = −40 to +125°C, V ≤ V ≤ 5.5 V, AV ≤...
  • Page 787 CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (A2) grade products Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. (7) Power Supply Starting Time = −40 to +125°C, V = 0 V) Parameter Symbol Conditions...

  • Page 788: Data Retention Characteristics

    CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (A2) grade products Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. 28.5 Data Retention Characteristics = −40 to +125°C) Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (T Parameter Symbol Conditions...

  • Page 789: Flash Eeprom Programming Characteristics

    CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (A2) grade products Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. 28.6 Flash EEPROM Programming Characteristics (1) Basic characteristics = −40 to +125°C, 2.7 V ≤ V ≤...

  • Page 790: Chapter 29 Package Drawings

    CHAPTER 29 PACKAGE DRAWINGS 29.1 78K0/FC2 μ • PD78F0881AGBA-GAF-G, 78F0881AGBA2-GAF-G, 78F0882AGBA-GAF-G, 78F0882AGBA2-GAF-G, 78F0883AGBA-GAF-G, 78F0883AGBA2-GAF-G 44-PIN PLASTIC LQFP (10x10) detail of lead end θ (UNIT:mm) ITEM DIMENSIONS 10.00±0.20 10.00±0.20 12.00±0.20 12.00±0.20 1.60 MAX. 0.10±0.05 1.40±0.05 0.25 0.35 +0.08 −0.04 0.125 +0.075 −0.025 0.50 0.60±0.15...
  • Page 791 CHAPTER 29 PACKAGE DRAWINGS μ • PD78F0884AGAA-GAM-G, 78F0884AGAA2-GAM-G, 78F0885AGAA-GAM-G, 78F0885AGAA2-GAM-G, 78F0886AGAA-GAM-G, 78F0886AGAA2-GAM-G, 78F0894AGAA-GAM-G, 78F0894AGAA2-GAM-G, 78F0895AGAA-GAM-G, 78F0895AGAA2-GAM-G 48-PIN PLASTIC LQFP (FINE PITCH) (7x7) detail of lead end θ (UNIT:mm) ITEM DIMENSIONS 7.00±0.20 7.00±0.20 9.00±0.20 9.00±0.20 1.60 MAX. 0.10±0.05 1.40±0.05 0.25 +0.07 0.20 −0.03 0.125 +0.075...

  • Page 792: 78K0/Fe2

    CHAPTER 29 PACKAGE DRAWINGS 29.2 78K0/FE2 μ • PD78F0887AGBA-GAH-G, 78F0887AGBA2-GAH-G, 78F0888AGBA-GAH-G, 78F0888AGBA2-GAH-G, 78F0889AGBA-GAH-G, 78F0889AGBA2-GAH-G, 78F0890AGBA-GAH-G, 78F0890AGBA2-GAH-G 64-PIN PLASTIC LQFP(FINE PITCH)(10x10) detail of lead end θ (UNIT:mm) ITEM DIMENSIONS 10.00±0.20 10.00±0.20 12.00±0.20 12.00±0.20 1.60 MAX. 0.10±0.05 1.40±0.05 0.25 +0.07 0.20 −0.03 0.125 +0.075 −0.025 0.50...
  • Page 793 CHAPTER 29 PACKAGE DRAWINGS μ • PD78F0887AGKA-GAJ-G, 78F0887AGKA2-GAJ-G, 78F0888AGKA-GAJ-G, 78F0888AGKA2-GAJ-G, 78F0889AGKA-GAJ-G, 78F0889AGKA2-GAJ-G, 78F0890AGKA-GAJ-G, 78F0890AGKA2-GAJ-G 64-PIN PLASTIC LQFP (12x12) detail of lead end θ (UNIT:mm) ITEM DIMENSIONS 12.00±0.20 12.00±0.20 14.00±0.20 14.00±0.20 1.60 MAX. 0.10±0.05 1.40±0.05 0.25 0.30 +0.08 −0.04 0.125 +0.75 −0.25 0.50 0.60±0.15...

  • Page 794: 78K0/Ff2

    CHAPTER 29 PACKAGE DRAWINGS 29.3 78K0/FF2 • μ PD78F0891AGCA-GAD-G, 78F0891AGCA2-GAD-G, 78F0892AGCA-GAD-G, 78F0892AGCA2-GAD-G, 78F0893AGCA-GAD-G, 78F0893AGCA2-GAD-G 80-PIN PLASTIC LQFP (14x14) detail of lead end θ (UNIT:mm) ITEM DIMENSIONS 14.00±0.20 14.00±0.20 17.20±0.20 17.20±0.20 1.70 MAX. 0.125±0.075 1.40±0.05 0.25 +0.08 0.30 −0.04 0.125 +0.075 −0.025 0.80 0.886±0.15...
  • Page 795 CHAPTER 29 PACKAGE DRAWINGS μ • PD78F0891AGKA-GAK-G, 78F0891AGKA2-GAK-G, 78F0892AGKA-GAK-G, 78F0892AGKA2-GAK-G, 78F0893AGKA-GAK-G, 78F0893AGKA2-GAK-G 80-PIN PLASTIC LQFP (FINE PITCH) (12x12) detail of lead end θ (UNIT:mm) ITEM DIMENSIONS 12.00±0.20 12.00±0.20 14.00±0.20 14.00±0.20 1.60 MAX. 0.10±0.05 1.40±0.05 0.25 +0.07 0.20 −0.03 0.125 +0.075 −0.025 0.50 0.60±0.15...

  • Page 796: Chapter 30 Recommended Soldering Conditions

    CHAPTER 30 RECOMMENDED SOLDERING CONDITIONS These products should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, please contact an NEC Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) Table 30-1.

  • Page 797: Chapter 31 Cautions For Wait

    CHAPTER 31 CAUTIONS FOR WAIT 31.1 Cautions for Wait This product has two internal system buses. One is a CPU bus and the other is a peripheral bus that interfaces with the low-speed peripheral hardware. Because the clock of the CPU bus and the clock of the peripheral bus are asynchronous, unexpected illegal data may be passed if an access to the CPU conflicts with an access to the peripheral hardware.

  • Page 798: Peripheral Hardware That Generates Wait

    CHAPTER 31 CAUTIONS FOR WAIT 31.2 Peripheral Hardware That Generates Wait Table 31-1 lists the registers that issue a wait request when accessed by the CPU, and the number of CPU wait clocks. Table 31-1. Registers That Generate Wait and Number of CPU Wait Clocks Peripheral Register Access...
  • Page 799 CHAPTER 31 CAUTIONS FOR WAIT Table 31-2 RAM Access That Generate Wait and Number of CPU Wait Clocks Peripheral Register Access number of wait clocks Cause Hardware MIN. MAX. Global Reg. Read/Write synchronizaition of NPB signals with VPCLK CANmodule <Calculating number of wait clocks> MIN.

  • Page 800: Example Of Wait Occurrence

    CHAPTER 31 CAUTIONS FOR WAIT 31.3 Example of Wait Occurrence • Serial interface UART61 <On execution of MOV A, ASIS61> Number of execution clocks: 6 (5 clocks when data is read from a register that does not issue a wait (MOV A, sfr).) User’s Manual U19180EJ1V0UD...

  • Page 801: Appendix A Development Tools

    APPENDIX A DEVELOPMENT TOOLS The following development tools are available for the development of systems that employ the 78K0/Fx2 microcontrollers. Figure A-1 shows the development tool configuration. User’s Manual U19180EJ1V0UD...
  • Page 802 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tool Configuration (1/3) (1) When using the in-circuit emulator QB-78K0FX2 Software package · Software package Language processing software Debugging software · Assembler package Note 1 · Integrated debugger · C compiler package Note 2 ·...
  • Page 803 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tool Configuration (2/3) (2) When using the on-chip debug emulator QB-78K0MINI Software package • Software package Language processing software Debugging software • Assembler package • Integrated debugger Note 4 • C compiler package •...
  • Page 804 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tool Configuration (3/3) (2) When using the on-chip debug emulator with programming function QB-MINI2 Software package • Software package Language processing software Debugging software • Assembler package • Integrated debugger Note 1 • C compiler package •...

  • Page 805: Software Package

    APPENDIX A DEVELOPMENT TOOLS A.1 Software Package SP78K0 Development tools (software) common to the 78K0 microcontrollers are combined in this 78K0 microcontroller software package. package A.2 Language Processing Software Note 1 RA78K0 This assembler converts programs written in mnemonics into object codes executable Assembler package with a microcontroller.

  • Page 806: Flash Memory Programming Tools

    APPENDIX A DEVELOPMENT TOOLS A.3 Flash Memory Programming Tools A.3.1 When using flash memory programmer PG-FP5, FL-PR5, FG-FP4, and FL-PR4 PG-FP5, FL-PR5, Flash memory programmer dedicated to microcontrollers with on-chip flash memory. Note 1 PG-FP4 , FL-PR4 Flash memory programmer Note 2 FA-xxxx Flash memory programming adapter used connected to the flash memory programmer...

  • Page 807: Debugging Tools (Hardware)

    APPENDIX A DEVELOPMENT TOOLS A.4 Debugging Tools (Hardware) A.4.1 When using in-circuit emulator QB-78K0FX2 QB-78K0FX2 The in-circuit emulator serves to debug hardware and software when developing application In-circuit emulator systems using the 78K0/Fx2 microcontrollers. It supports the integrated debugger (ID78K0- QB).

  • Page 808: When Using On-Chip Debug Emulator Qb-78K0Mini

    APPENDIX A DEVELOPMENT TOOLS Remarks 1. The QB-78K0FX2 is supplied with the integrated debugger ID78K0-QB, a USB interface cable, a power supply unit, the on-chip debug emulator QB-MINI2, connection cables (10-pin and 16-pin cables), and the 78K0-OCD board. Download the software for operating the QB-MINI2 from the download site for development tools (http://www.necel.com/micro/en/ods/index.html) when using the QB-MINI2.

  • Page 809: Debugging Tools (Software)

    APPENDIX A DEVELOPMENT TOOLS A.5 Debugging Tools (Software) Note ID78K0-QB This debugger supports the in-circuit emulators for the 78K0 microcontrollers. The Integrated debugger ID78K0-QB is Windows-based software. It has improved C-compatible debugging functions and can display the results of tracing with the source program using an integrating window function that associates the source program, disassemble display, and memory display with the trace result.

  • Page 810: Appendix B Notes On Target System Design

    APPENDIX B NOTES ON TARGET SYSTEM DESIGN This chapter shows areas on the target system where component mounting is prohibited and areas where there are component mounting height restrictions when the QB-78K0FX2 is used. (a) Case of 44-pin GB package Figure B-1.
  • Page 811 APPENDIX B NOTES ON TARGET SYSTEM DESIGN (b) Case of 48-pin GA package Figure B-2. The Restriction Domain on a Target System (Case of 48-pin GA Package) 13.375 17.375 Note : Exchange adapter area: Components up to 17.45 mm in height can be mounted Note : Emulation probe tip area: Components up to 24.45 mm in height can be mounted...
  • Page 812 APPENDIX B NOTES ON TARGET SYSTEM DESIGN (c) Case of 64-pin GB package Figure B-3. The Restriction Domain on a Target System (Case of 64-pin GB Package) 13.375 17.375 Note : Exchange adapter area: Components up to 17.45 mm in height can be mounted Note : Emulation probe tip area: Components up to 24.45 mm in height can be mounted...
  • Page 813 APPENDIX B NOTES ON TARGET SYSTEM DESIGN (d) Case of 64-pin GK package Figure B-4. The Restriction Domain on a Target System (Case of 64-pin GK Package) 13.375 17.375 Note : Exchange adapter area: Components up to 17.45 mm in height can be mounted Note : Emulation probe tip area: Components up to 24.45 mm in height can be mounted...
  • Page 814 APPENDIX B NOTES ON TARGET SYSTEM DESIGN (e) Case of 80-pin GC package Figure B-5. The Restriction Domain on a Target System (Case of 80-pin GC Package) 13.375 17.375 Note : Exchange adapter area: Components up to 17.45 mm in height can be mounted Note : Emulation probe tip area: Components up to 24.45 mm in height can be mounted...
  • Page 815 APPENDIX B NOTES ON TARGET SYSTEM DESIGN (f) Case of 80-pin GK package Figure B-6. The Restriction Domain on a Target System (Case of 80-pin GK Package) 13.375 17.375 Note : Exchange adapter area: Components up to 17.45 mm in height can be mounted Note : Emulation probe tip area: Components up to 24.45 mm in height can be mounted...

  • Page 816: Appendix C Register Index

    APPENDIX C REGISTER INDEX C.1 Register Index (In Alphabetical Order with Respect to Register Names) 10-bit A/D conversion result register (ADCR)......................359 16-bit timer capture/compare register 000 (CR000) ....................226 16-bit timer capture/compare register 001 (CR001) ....................226 16-bit timer capture/compare register 002 (CR002) ....................226 16-bit timer capture/compare register 003 (CR003) ....................226 16-bit timer capture/compare register 010 (CR010) ....................228 16-bit timer capture/compare register 011 (CR011) ....................228...
  • Page 817 APPENDIX C REGISTER INDEX A/D port configuration register (ADPC) ........................362 Analog input channel specification register (ADS) ......................361 Asynchronous serial interface control register 60 (ASICL60)..................402 Asynchronous serial interface control register 61 (ASICL61)..................402 Asynchronous serial interface operation mode register 60 (ASIM60) .................388 Asynchronous serial interface operation mode register 61 (ASIM61) .................388 Asynchronous serial interface reception error status register 60 (ASIS60)..............393 Asynchronous serial interface reception error status register 61 (ASIS61)..............393...
  • Page 818 APPENDIX C REGISTER INDEX CAN module receive history list register (C0RGPT)....................518 CAN module time stamp register (C0TS) ........................521 CAN module transmit history list register (C0TGPT)....................520 Capture/compare control register 00 (CRC00)......................237 Capture/compare control register 01 (CRC01)......................237 Capture/compare control register 02 (CRC02)......................237 Capture/compare control register 03 (CRC03)......................237 Clock operation mode select register (OSCCTL) ......................190 Clock output selection register (CKS) .........................349...
  • Page 819 APPENDIX C REGISTER INDEX Oscillation stabilization time counter status register (OSTC) ..................192 Oscillation stabilization time select register (OSTS)....................193 Port mode register 0 (PM0)............................167 Port mode register 1 (PM1)............................167 Port mode register 12 (PM12).............................167 Port mode register 13 (PM13).............................167 Port mode register 3 (PM3)............................167 Port mode register 4 (PM4)............................167 Port mode register 5 (PM5)............................167 Port mode register 6 (PM6)............................167...
  • Page 820 APPENDIX C REGISTER INDEX Pull-up resistor option register 7 (PU7) ........................173 Receive buffer register 60 (RXB60) ..........................387 Receive buffer register 61 (RXB61) ..........................387 Receive shift register 60 (RXS60) ..........................387 Receive shift register 61 (RXS61) ..........................387 Remainder data register 0 (SDR0)..........................643 Reset control flag register (RESF) ..........................640 Serial clock selection register 10 (CSIC10) .........................435 Serial clock selection register 11 (CSIC11) .........................435...

  • Page 821: Register Index (In Alphabetical Order With Respect To Register Symbol)

    APPENDIX C REGISTER INDEX C.2 Register Index (In Alphabetical Order with Respect to Register Symbol) ADCR: 10-bit A/D conversion result register ....................359 ADCRH: 8-bit A/D conversion result register .....................360 ADM: A/D converter mode register .......................356 ADPC: A/D port configureation register ......................362 ADS: Analog input channel specification register..................361 ASICL60:...
  • Page 822 APPENDIX C REGISTER INDEX C0MASK3H: CAN module mask control register 3H....................502 C0MASK3L: CAN module mask control register 3L ....................502 C0MASK4H: CAN module mask control register 4H....................502 C0MASK4L: CAN module mask control register 4L ....................502 C0MIDHm: CAN message id register Hm ........................527 C0MIDLm: CAN message id register Lm .........................527 C0RGPT:...
  • Page 823 APPENDIX C REGISTER INDEX IF0L: Interrupt request flag register 0L ......................601 IF1H: Interrupt request flag register 1H ......................601 IF1L: Interrupt request flag register 1L ......................601 IMS: Internal memory size switching register....................679 ISC: Input switch control register ........................406 IXS: Internal expansion RAM size switching register ..................680 LVIM: Low-voltage detection register ........................658 LVIS:...
  • Page 824 APPENDIX C REGISTER INDEX PM4: Port mode register 4 ..........................167 PM5: Port mode register 5 ..........................167 PM6: Port mode register 6 ..........................167 PM7: Port mode register 7 ..........................167 PM8: Port mode register 8 ..........................167 PM9: Port mode register 9 ..........................167 PR0H: Priority specification flag register 0H .......................606 PR0L:...
  • Page 825 APPENDIX C REGISTER INDEX TM50: 8-bit timer counter 50 ..........................290 TM51: 8-bit timer counter 51 ..........................290 TMC00: 16-bit timer mode control register 00.......................232 TMC01: 16-bit timer mode control register 01.......................232 TMC02: 16-bit timer mode control register 02.......................232 TMC03: 16-bit timer mode control register 03.......................232 TMC50: 8-bit timer mode control register 50......................295 TMC51:...

  • Page 826: Appendix D List Of Cautions

    APPENDIX D LIST OF CAUTIONS This appendix lists cautions described in this document. “Classification (hard/soft)” in table is as follows. Hard: Cautions for microcontroller internal/external hardware Soft: Cautions for software such as register settings or programs (1/32) Function Details of Cautions Page Function...
  • Page 827 APPENDIX D LIST OF CAUTIONS (2/32) Function Details of Cautions Page Function Memory Memory bank Instructions cannot be fetched between different memory banks. p. 82 space Branch and access cannot be directly executed between different memory p. 82 banks. Execute branch or access between different memory banks via the common area.
  • Page 828 APPENDIX D LIST OF CAUTIONS (3/32) Function Details of Cautions Page Function Port P121/X1, When using the P121 to P124 pins to connect a resonator for the main system p. 159 function P122/X2/EXCLK, clock (X1, X2) or subsystem clock (XT1, XT2), or to input an external clock for P123/XT1, the main system clock (EXCLK) or subsystem clock (EXCLKS), the X1 oscillation P124/XT2/EXCLKS...
  • Page 829 APPENDIX D LIST OF CAUTIONS (4/32) Function Details of Cautions Page Function Clock MOC: Main OSC When setting MSTOP to 1, be sure to confirm that the CPU operates with a clock p. 189 generator control register other than the high-speed system clock. Specifically, set MSTOP to 1 under either of the following conditions.
  • Page 830 APPENDIX D LIST OF CAUTIONS (5/32) Function Details of Cautions Page Function Clock OSTS: Oscillation To set the STOP mode when the X1 clock is used as the CPU clock, set OSTS p. 193 generator stabilization time before executing the STOP instruction. select register Do not change the value of the OSTS register during the X1 clock oscillation p.
  • Page 831 APPENDIX D LIST OF CAUTIONS (6/32) Function Details of Cautions Page Function Controlling X1/P121 and The X1/P121 and X2/EXCLK/P122 pins are in the I/O port mode after a reset p. 203 high-speed X2/EXCLK/P122 release. system X1 clock Do not change the value of EXCLK and OSCSEL while the X1 clock is operating. p. 204 clock Set the X1 clock after the supply voltage has reached the operable voltage of the p.
  • Page 832 APPENDIX D LIST OF CAUTIONS (7/32) Function Details of Cautions Page Function − 16-bit Be careful to the following restrictions for function of 16-bit timer/event p. 219 μ timer/event counter 01 for PD78F0881A, 78F0882A, and 78F0883A. counters 00, • Selecting TI001 and TI011 for count clock is prohibited. When Using TI001 for baud rate error calculation, it is not applicable.
  • Page 833 APPENDIX D LIST OF CAUTIONS (8/32) Function Details of Cautions Page Function − 16-bit To capture the count value of the TM0n register to the CR00n register by using p. 231 timer/event the phase reverse to that input to the TI00n pin, the interrupt request signal counters 00, (INTTM00n) is not generated after the value has been captured.
  • Page 834 APPENDIX D LIST OF CAUTIONS (9/32) Function Details of Cautions Page Function 16-bit External event Only 16-bit timer/event counter 00 can use the external event counter of pp. 270 timer/event counter 78K0/FC2. to 272 counters When reading the external event counter count value, TM0n should be read. p.
  • Page 835 APPENDIX D LIST OF CAUTIONS (10/32) Function Details of Cautions Page Function 16-bit One-shot pulse One-shot pulse output operates correctly in the free-running timer mode or the p. 285 timer/event output clear & start mode entered by the TI00n pin valid edge. The one-shot pulse counters cannot be output in the clear &...
  • Page 836 APPENDIX D LIST OF CAUTIONS (11/32) Function Details of Cautions Page Function 8-bit TMC5n: 8-bit The settings of LVS5n and LVR5n are valid in other than PWM mode. p. 296 timer/event timer mode Perform <1> to <4> below in the following order, not at the same time. p.
  • Page 837 APPENDIX D LIST OF CAUTIONS (12/32) Function Details of Cautions Page Function 8-bit timers Carrier Do not rewrite the NRZB1 bit again until at least the second clock after it has p. 327 H0, H1 generator (8-bit been rewritten, or else the transfer from the NRZB1 bit to the NRZ1 bit is not timer H1 only) guaranteed.
  • Page 838 APPENDIX D LIST OF CAUTIONS (13/32) Function Details of Cautions Page Function Watchdog Setting overflow The combination of WDCS2 = WDCS1 = WDCS0 = 0 and WINDOW1 = pp. 345, timer time of WINDOW0 = 0 is prohibited. watchdog timer, The watchdog timer continues its operation during self-programming and pp.
  • Page 839 APPENDIX D LIST OF CAUTIONS (14/32) Function Details of Cautions Page Function ADS: Analog Be sure to clear bits 4 to 7 to “0”. p. 361 converter input channel Because ADS and ADPC do not control input and output, set the channel used for p.
  • Page 840 APPENDIX D LIST OF CAUTIONS (15/32) Function Details of Cautions Page Function P80/ANI0 to The analog input pins (ANI0 to ANI15) are also used as I/O port pins (P80 to P87, p. 375 converter P87/ANI7, P90 to P97). P90/ANI8 to When A/D conversion is performed with any of ANI0 to ANI15 selected, do not P97/ANI15 access P80 to P87, P90 to P97 while conversion is in progress;...
  • Page 841 APPENDIX D LIST OF CAUTIONS (16/32) Function Details of Cautions Page Function Serial UART mode Set POWER6n = 1 and then set TXE6n = 1 (transmission) or RXE6n = 1 p. 378 interface (reception) to start communication. UART60, TXE6n and RXE6n are synchronized by the base clock (f ) set by CKSR6n.
  • Page 842 APPENDIX D LIST OF CAUTIONS (17/32) Function Details of Function Cautions Page Serial ASIF6n: To transmit data continuously, write the first transmit data (first byte) to the TXB6n pp. 395, interface Asynchronous register. Be sure to check that the TXBF6n flag is “0”. If so, write the next transmit UART60, serial interface data (second byte) to the TXB6n register.
  • Page 843 APPENDIX D LIST OF CAUTIONS (18/32) Function Details of Function Cautions Page Serial Continuous The TXBF6n and TXSF6n flags of the ASIF6n register change from “10” to “11”, p. 415 interface transmission and to “01” during continuous transmission. To check the status, therefore, do not UART60, use a combination of the TXBF6n and TXSF6n flags for judgment.
  • Page 844 APPENDIX D LIST OF CAUTIONS (19/32) Function Details of Function Cautions Page Serial 3-wire serial I/O mode Take relationship with the other party of communication when setting the port p. 442 interface mode register and port register. CSI10, Communication Do not access the control register and data register when CSOT1n = 1 (during p.
  • Page 845 APPENDIX D LIST OF CAUTIONS (20/32) Function Details of Function Cautions Page Register bit The actual register address is calculated as follows: pp. 490 controller configuration Register Address = Global Register Area Offset (CH dependent) + Offset to 493 Address as listed in table above C0GMCTRL: CAN While the MBON bit is cleared (to 0), software access to the message buffers p.
  • Page 846 APPENDIX D LIST OF CAUTIONS (21/32) Function Details of Function Cautions Page C0INTS: CAN module Please clear the status bit of this register with software when the confirmation of p. 513 controller interrupt status each status is necessary in the interrupt processing, because these bits are not register cleared automatically.
  • Page 847 APPENDIX D LIST OF CAUTIONS (22/32) Function Details of Function Cautions Page Receive history list If the history list is in the overflow condition (ROVF is set), reading the history p. 536 controller function list contents is still possible, until the history list is empty (indicated by RHPM flag set).
  • Page 848 APPENDIX D LIST OF CAUTIONS (23/32) Function Details of Function Cautions Page Automatic block The C0GMABTD register is used to set the delay time that is inserted in the p. 547 controller transmission (ABT) period from completion of the preceding ABT message to setting of the TRQ bit for the next ABT message when the transmission requests are set in the order of message numbers for each message for ABT that is successively transmitted in the ABT mode.
  • Page 849 APPENDIX D LIST OF CAUTIONS (24/32) Function Details of Function Cautions Page Time stamp function The time stamp function using TSLOCK bit is to stop toggle of TSOUT bit by p. 559 controller receiving a data frame in message buffer 0. Therefore, message buffer 0 must be set as a receive message buffer.
  • Page 850 APPENDIX D LIST OF CAUTIONS (25/32) Function Details of Function Cautions Page ABT Transmission Do not set any transmission requests while ABT transmission abort processing is pp. 581, controller Abort Processing in progress. Make a CAN sleep mode/CAN stop mode transition request after ABTTRG bit is pp.
  • Page 851 APPENDIX D LIST OF CAUTIONS (26/32) Function Details of Cautions Page Function Interrupt BRK instruction The BRK instruction is not one of the above-listed interrupt request hold p. 616 function instructions. However, the software interrupt activated by executing the BRK instruction causes the IE flag to be cleared.
  • Page 852 APPENDIX D LIST OF CAUTIONS (27/32) Function Details of Cautions Page Function Standby STOP mode Even if “internal low-speed oscillator can be stopped by software” is selected by the p. 627 function option byte, the internal low-speed oscillator continues in the STOP mode in the status before the STOP mode is set.
  • Page 853 APPENDIX D LIST OF CAUTIONS (28/32) Function Details of Cautions Page Function Multiplier/ DMUC0: If DMUE is cleared to 0 during operation processing (while DMUE is 1), the p. 645 divider Multiplier/divider operation processing is stopped. To execute the operation again, set control register 0 multiplication/division data register A0 (MDA0), multiplication/division data register B0 (MDB0), and multiplier/divider control register 0 (DMUC0), and start the...
  • Page 854 APPENDIX D LIST OF CAUTIONS (29/32) Function Details of Cautions Page Function Option 0082H, 0083H/ Be sure to set 00H to 0082H and 0083H (0082H/1082H and 0083H/1083H when the p. 674 byte 1082H, 1083H boot swap function is used). 0080H/1080H Set a value that is the same as that of 0080H to 1080H because 0080H and 1080H p.
  • Page 855 APPENDIX D LIST OF CAUTIONS (30/32) Function Details of Cautions Page Function Flash Flash memory The self-programming function cannot be used when the CPU operates with the p. 706 memory programming subsystem clock. by self- Input a high level to the FLMD0 pin during self-programming. p.
  • Page 856 APPENDIX D LIST OF CAUTIONS (31/32) Function Details of Cautions Page Function On-chip Restrictions When setting to on-chip debugging mode via the normal port, without using pins p. 726 debug and Cautions X1 and X2, two of the user ports will be unavailable for use. function on On-Chip In order to realize on-chip debug function, use the following user resource.
  • Page 857 APPENDIX D LIST OF CAUTIONS (32/32) Function Details of Cautions Page Function Electrical X1 oscillator When using the X1 oscillator, wire as follows in the area enclosed by the pp. 744, specifications characteristics broken lines in the above figures to avoid an adverse effect from wiring capacitance.
  • Page 858 For further information, please contact: NEC Electronics Corporation 1753, Shimonumabe, Nakahara-ku, Kawasaki, Kanagawa 211-8668, Japan Tel: 044-435-5111 http://www.necel.com/ [Asia & Oceania] [America] [Europe] NEC Electronics (China) Co., Ltd NEC Electronics America, Inc. NEC Electronics (Europe) GmbH 7th Floor, Quantum Plaza, No. 27 ZhiChunLu Haidian 2880 Scott Blvd.

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