Starting Pll Clock Oscillation - Renesas M16C/64A Series User Manual

M16C/64A Group
8.9.6

Starting PLL Clock Oscillation

(Technical update number:
Adhere to the following restrictions when using the following products:
R5F364AENFA, R5F364AENFB, R5F364AEDFA, R5F364AEDFB,
R5F364A6NFA, R5F364A6NFB, R5F364A6DFA, R5F364A6DFB
8.9.6.1 When Using Voltage Detector 0, 1, or 2
Do not change the PLC07 bit in the PLC0 register from 0 to 1 when any bit from VC25 to VC27 in the
VCR2 register is 1.
To change the PLC07 bit from 0 to 1 while using a voltage detector or power-on reset, use the
following procedure:
(1) Set bits VC25 to VC27 to 0 (voltage detector off).
(2) Change the PLC07 bit from 0 to 1.
(3) Wait for 1 ms.
(4) Change the bit from VC25 to VC27 that was originally 1, back to 1 (voltage detector on).
8.9.6.2 When Using 125 kHz On-chip Oscillator Mode or 125 kHz On-chip Oscil-
lator Low Power Mode
Change the PLC07 bit in the PLC0 register from 0 to 1 while dividing the clock by 8 or 16 (selectable
by setting the CM06 bit in the CM0 register and bits CM17 to CM16 in the CM1 register).
8.9.6.3 Count Source for Timer A and Timer B
When using PLL clock, do not use fOCO-S as the count source for timer A and timer B.
8.9.6.4 When Using fOCO-S as the Count Source for the Watchdog Timer
Change the PLC07 bit in the PLC0 register from 0 to 1 using the following procedure:
(1) Write 00h to the WDTR register, then write FFh (watchdog timer refresh).
(2) Change the PLC07 bit from 0 to 1.
(3) Wait for 1 ms.
(4) Write 00h to the WDTR register, then write FFh (watchdog timer refresh).
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
TN-
16C-A177A/E)
8. Clock Generator
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