Renesas M16C/64A Series User Manual page 121

M16C/64A Group
CM02 (Wait mode peripheral function clock stop bit) (b2)
This bit is used to stop the f1 peripheral function clock in wait mode. fC, fC32, and fOCO-S are not
affected by the CM02 bit.
When the PM21 bit in the PM2 register is 1 (clock change disabled), the CM02 bit remains unchanged
even when written to.
CM03 (XCIN-XCOUT drive capacity select Bit) (b3)
Setting the driving capacity to low while sub clock oscillation is stable reduces power consumption.
The CM03 bit becomes 1 (high) while the CM04 bit is 0 (P8_6 and P8_7 are I/O ports), or when
entering stop mode.
CM04 (Port XC select bit) (b4)
The CM03 bit becomes 1 (high) while the CM04 bit is 0 (P8_6 and P8_7 are I/O ports).
CM05 (Main clock stop bit) (b5)
This bit is used to stop the main clock. The main clock is allowed to stop in the following cases.
•
Entering low power mode
•
Entering 125 kHz on-chip oscillator low power mode
This bit cannot be used to detect if the main clock is stopped or not. Refer to 8.7 "Oscillator Stop/Restart
Detect Function" for details on main clock stop detection.
When the PM21 bit in the PM2 register is 1 (clock change disabled), this bit remains unchanged even
when written to.
CM06 (Main clock division select bit) (b6)
The CM06 bit becomes 1 (divide-by-8 mode) under the following conditions:
•
When entering stop mode
•
When the CM21 bit in the CM2 register is 0 (main clock or PLL clock) and the CM05 bit is 1 (main
clock off)
CM07 (System clock select bit) (b7)
The CPU clock source and the peripheral function clock f1 depend on combinations of the bit status of
the CM07 bit, the CM11 bit in the CM1 register, and the CM21 bit in the CM2 register. When the CM07
bit is 0 (main clock or on-chip oscillator clock used as CPU clock), the CPU clock source and the
peripheral function clock f1 can be selected by combinations of the bit status of the CM11 bit and the
CM21 bit. When the CM07 bit is 1 (sub clock used as CPU clock), the CPU clock source is fC, and the
peripheral function clock f1 can be selected by combinations of the bit status of bits CM11 and CM21.
When setting the PM21 bit in the PM2 register to 1 (clock change disabled), set the CM07 bit to 0 (main
clock) before setting the PM21 bit to 1. When the PM21 bit is set to 1, this bit remains unchanged even
when written to.
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
8. Clock Generator
Page 88 of 800