Hitachi SH7751 Manuals

Manuals and User Guides for Hitachi SH7751. We have 1 Hitachi SH7751 manual available for free PDF download: Hardware Manual

Hitachi SH7751 Hardware Manual (1104 pages)

SuperH RISC engine

Brand: Hitachi | Category: Engine | Size: 5.43 MB

Table Of Contents6................................................................................................................................................................

Section 1 Overview40................................................................................................................................................................

Table 1.1 Sh7751 Series Features41................................................................................................................................................................

Block Diagram49................................................................................................................................................................

Pin Arrangement50................................................................................................................................................................

Figure 1.3 Pin Arrangement (256-pin Bga)51................................................................................................................................................................

Pin Functions52................................................................................................................................................................

Pin Functions (256-pin Bga)63................................................................................................................................................................

Section 2 Programming Model74................................................................................................................................................................

Register Configuration75................................................................................................................................................................

Table 2.1 Initial Register Values76................................................................................................................................................................

Figure 2.2 Cpu Register Configuration In Each Processor Mode77................................................................................................................................................................

General Registers78................................................................................................................................................................

Figure 2.3 General Registers79................................................................................................................................................................

Floating-point Registers80................................................................................................................................................................

Figure 2.4 Floating-point Registers81................................................................................................................................................................

Control Registers82................................................................................................................................................................

System Registers83................................................................................................................................................................

Memory-mapped Registers85................................................................................................................................................................

Data Format In Registers86................................................................................................................................................................

Processor States87................................................................................................................................................................

Processor Modes88................................................................................................................................................................

Section 3 Memory Management Unit (mmu)90................................................................................................................................................................

Figure 3.1 Role Of The Mmu92................................................................................................................................................................

Register Descriptions94................................................................................................................................................................

Address Space97................................................................................................................................................................

Figure 3.3 Physical Address Space (mmucr.at = 0)98................................................................................................................................................................

Figure 3.4 P4 Area99................................................................................................................................................................

External Memory Space100................................................................................................................................................................

Virtual Address Space101................................................................................................................................................................

On-chip Ram Space102................................................................................................................................................................

Single Virtual Memory Mode And Multiple Virtual Memory Mode103................................................................................................................................................................

Tlb Functions104................................................................................................................................................................

Figure 3.8 Relationship Between Page Size And Address Format105................................................................................................................................................................

Instruction Tlb (itlb) Configuration108................................................................................................................................................................

Figure 3.10 Flowchart Of Memory Access Using Utlb109................................................................................................................................................................

Figure 3.11 Flowchart Of Memory Access Using Itlb110................................................................................................................................................................

Mmu Functions111................................................................................................................................................................

Hardware Itlb Miss Handling112................................................................................................................................................................

Avoiding Synonym Problems113................................................................................................................................................................

Mmu Exceptions114................................................................................................................................................................

Instruction Tlb Protection Violation Exception115................................................................................................................................................................

Data Tlb Multiple Hit Exception116................................................................................................................................................................

Data Tlb Miss Exception117................................................................................................................................................................

Data Tlb Protection Violation Exception118................................................................................................................................................................

Memory-mapped Tlb Configuration119................................................................................................................................................................

Itlb Address Array120................................................................................................................................................................

Itlb Data Array 1121................................................................................................................................................................

Itlb Data Array 2122................................................................................................................................................................

Figure 3.16 Memory-mapped Utlb Address Array123................................................................................................................................................................

Utlb Data Array 1124................................................................................................................................................................

Utlb Data Array 2125................................................................................................................................................................

Section 4 Caches126................................................................................................................................................................

Operand Cache (oc)130................................................................................................................................................................

Figure 4.2 Configuration Of Operand Cache (sh7751)131................................................................................................................................................................

Figure 4.3 Configuration Of Operand Cache (sh7751r)132................................................................................................................................................................

Read Operation133................................................................................................................................................................

Write Operation134................................................................................................................................................................

Write-back Buffer136................................................................................................................................................................

Oc Index Mode138................................................................................................................................................................

Figure 4.6 Configuration Of Instruction Cache (sh7751)139................................................................................................................................................................

Figure 4.7 Configuration Of Instruction Cache (sh7751r)140................................................................................................................................................................

Memory-mapped Cache Configuration (sh7751)142................................................................................................................................................................

Ic Data Array143................................................................................................................................................................

Oc Address Array144................................................................................................................................................................

Oc Data Array145................................................................................................................................................................

Memory-mapped Cache Configuration (sh7751r)146................................................................................................................................................................

Ic Address Array147................................................................................................................................................................

Summary Of Memory-mapped Oc Addresses151................................................................................................................................................................

Store Queues152................................................................................................................................................................

Determination Of Sq Access Exception154................................................................................................................................................................

Sq Usage Notes155................................................................................................................................................................

Section 5 Exceptions158................................................................................................................................................................

Exception Handling Functions160................................................................................................................................................................

Exception Types And Priorities161................................................................................................................................................................

Exception Flow164................................................................................................................................................................

Exception Source Acceptance165................................................................................................................................................................

Figure 5.3 Example Of General Exception Acceptance Order166................................................................................................................................................................

Exception Requests And Bl Bit167................................................................................................................................................................

Resets168................................................................................................................................................................

Table 5.3 Types Of Reset169................................................................................................................................................................

General Exceptions173................................................................................................................................................................

Interrupts187................................................................................................................................................................

Priority Order With Multiple Exceptions190................................................................................................................................................................

Usage Notes191................................................................................................................................................................

Restrictions192................................................................................................................................................................

Section 6 Floating-point Unit194................................................................................................................................................................

Figure 6.2 Format Of Double-precision Floating-point Number195................................................................................................................................................................

Non-numbers (nan)196................................................................................................................................................................

Denormalized Numbers197................................................................................................................................................................

Registers198................................................................................................................................................................

Figure 6.4 Floating-point Registers199................................................................................................................................................................

Floating-point Status/control Register (fpscr)200................................................................................................................................................................

Floating-point Communication Register (fpul)201................................................................................................................................................................

Floating-point Exceptions202................................................................................................................................................................

Graphics Support Functions203................................................................................................................................................................

Pair Single-precision Data Transfer205................................................................................................................................................................

Section 7 Instruction Set206................................................................................................................................................................

Addressing Modes208................................................................................................................................................................

Instruction Set212................................................................................................................................................................

Table 7.3 Fixed-point Transfer Instructions213................................................................................................................................................................

Table 7.4 Arithmetic Operation Instructions215................................................................................................................................................................

Table 7.5 Logic Operation Instructions217................................................................................................................................................................

Table 7.6 Shift Instructions218................................................................................................................................................................

Table 7.7 Branch Instructions219................................................................................................................................................................

Table 7.8 System Control Instructions220................................................................................................................................................................

Table 7.9 Floating-point Single-precision Instructions222................................................................................................................................................................

Table 7.10 Floating-point Double-precision Instructions223................................................................................................................................................................

Table 7.12 Floating-point Graphics Acceleration Instructions224................................................................................................................................................................

Section 8 Pipelining226................................................................................................................................................................

Figure 8.1 Basic Pipelines227................................................................................................................................................................

Figure 8.2 Instruction Execution Patterns228................................................................................................................................................................

Parallel-executability233................................................................................................................................................................

Execution Cycles And Pipeline Stalling237................................................................................................................................................................

Figure 8.3 Examples Of Pipelined Execution240................................................................................................................................................................

Table 8.3 Execution Cycles244................................................................................................................................................................

Section 9 Power-down Modes254................................................................................................................................................................

Table 9.1 Status Of Cpu And Peripheral Modules In Power-down Modes255................................................................................................................................................................

Peripheral Module Pin High Impedance Control259................................................................................................................................................................

Standby Control Register 2 (stbcr2)260................................................................................................................................................................

Clock Stop Register 00 (clkstp00)261................................................................................................................................................................

Clock Stop Clear Register 00 (clkstpclr00)262................................................................................................................................................................

Sleep Mode263................................................................................................................................................................

Exit From Deep Sleep Mode264................................................................................................................................................................

Exit From Standby Mode265................................................................................................................................................................

Clock Pause Function266................................................................................................................................................................

Exit From Module Standby Function267................................................................................................................................................................

Hardware Standby Mode268................................................................................................................................................................

In Exit From Standby Mode270................................................................................................................................................................

Figure 9.4 Status Output In Standby Power-on Reset Sequence271................................................................................................................................................................

In Exit From Sleep Mode272................................................................................................................................................................

In Exit From Deep Sleep Mode275................................................................................................................................................................

Hardware Standby Mode Timing277................................................................................................................................................................

Figure 9.13 Hardware Standby Mode Timing (when Ca = Low In Wdt Operation)278................................................................................................................................................................

Section 10 Clock Oscillation Circuits280................................................................................................................................................................

Overview Of Cpg282................................................................................................................................................................

Figure 10.1(2) Block Diagram Of Cpg (sh7751r)283................................................................................................................................................................

Cpg Pin Configuration285................................................................................................................................................................

Clock Operating Modes286................................................................................................................................................................

Table 10.4 Frqcr Settings And Internal Clock Frequencies287................................................................................................................................................................

Cpg Register Description288................................................................................................................................................................

Changing The Frequency290................................................................................................................................................................

Changing Bus Clock Division Ratio (when Pll Circuit 2 Is On)291................................................................................................................................................................

Output Clock Control292................................................................................................................................................................

Watchdog Timer Control/status Register (wtcsr)294................................................................................................................................................................

Notes On Register Access296................................................................................................................................................................

Using The Wdt297................................................................................................................................................................

Using Watchdog Timer Mode298................................................................................................................................................................

Notes On Board Design299................................................................................................................................................................

Figure 10.5 Points For Attention When Using Pll Oscillator Circuit300................................................................................................................................................................

Section 11 Realtime Clock (rtc)302................................................................................................................................................................

Pin Configuration304................................................................................................................................................................

Minute Counter (rmincnt)307................................................................................................................................................................

Day-of-week Counter (rwkcnt)308................................................................................................................................................................

Day Counter (rdaycnt)309................................................................................................................................................................

Year Counter (ryrcnt)310................................................................................................................................................................

Second Alarm Register (rsecar)311................................................................................................................................................................

Hour Alarm Register (rhrar)312................................................................................................................................................................

Day Alarm Register (rdayar)313................................................................................................................................................................

Month Alarm Register (rmonar)314................................................................................................................................................................

Rtc Control Register 2 (rcr2)316................................................................................................................................................................

Rtc Control Register (rcr3) And Year-alarm Register (ryrar Sh7751r Only)319................................................................................................................................................................

Operation320................................................................................................................................................................

Time Reading Procedures321................................................................................................................................................................

Figure 11.3 Examples Of Time Reading Procedures322................................................................................................................................................................

Alarm Function323................................................................................................................................................................

Figure 11.5 Example Of Crystal Oscillator Circuit Connection325................................................................................................................................................................

Section 12 Timer Unit (tmu)326................................................................................................................................................................

Timer Start Register (tstr)330................................................................................................................................................................

Timer Start Register 2 (tstr2)331................................................................................................................................................................

Timer Constant Registers (tcor)332................................................................................................................................................................

Timer Control Registers (tcr)333................................................................................................................................................................

Input Capture Register (tcpr2)336................................................................................................................................................................

Figure 12.2 Example Of Count Operation Setting Procedure338................................................................................................................................................................

Figure 12.4 Count Timing When Operating On Internal Clock339................................................................................................................................................................

Input Capture Function340................................................................................................................................................................

Section 13 Bus State Controller (bsc)344................................................................................................................................................................

Overview Of Areas350................................................................................................................................................................

Table 13.3 External Memory Space Map351................................................................................................................................................................

Figure 13.3 External Memory Space Allocation352................................................................................................................................................................

Pcmcia Support353................................................................................................................................................................

Table 13.5 Pcmcia Support Interfaces354................................................................................................................................................................

Bus Control Register 2 (bcr2)365................................................................................................................................................................

Bus Control Register 3 (bcr3) (sh7751r Only)366................................................................................................................................................................

Bus Control Register 4 (bcr4) (sh7751r Only)368................................................................................................................................................................

Wait Control Register 1 (wcr1)370................................................................................................................................................................

Table 13.6 Idle Insertion Between Accesses372................................................................................................................................................................

Wait Control Register 2 (wcr2)373................................................................................................................................................................

Table 13.7 When Mpx Interface Is Set (areas 0 To 6)380................................................................................................................................................................

Wait Control Register 3 (wcr3)381................................................................................................................................................................

Memory Control Register (mcr)383................................................................................................................................................................

Pcmcia Control Register (pcr)389................................................................................................................................................................

Synchronous Dram Mode Register (sdmr)391................................................................................................................................................................

Refresh Timer Control/status Register (rtcsr)393................................................................................................................................................................

Refresh Timer Counter (rtcnt)395................................................................................................................................................................

Refresh Time Constant Register (rtcor)396................................................................................................................................................................

Refresh Count Register (rfcr)397................................................................................................................................................................

Table 13.8 32-bit External Device/big-endian Access And Data Alignment399................................................................................................................................................................

Table 13.9 16-bit External Device/big-endian Access And Data Alignment400................................................................................................................................................................

Table 13.10 8-bit External Device/big-endian Access And Data Alignment401................................................................................................................................................................

Table 13.11 32-bit External Device/little-endian Access And Data Alignment402................................................................................................................................................................

Table 13.12 16-bit External Device/little-endian Access And Data Alignment403................................................................................................................................................................

Table 13.13 8-bit External Device/little-endian Access And Data Alignment404................................................................................................................................................................

Areas405................................................................................................................................................................

Sram Interface409................................................................................................................................................................

Figure 13.6 Basic Timing Of Sram Interface410................................................................................................................................................................

Figure 13.7 Example Of 32-bit Data Width Sram Connection411................................................................................................................................................................

Figure 13.8 Example Of 16-bit Data Width Sram Connection412................................................................................................................................................................

Figure 13.9 Example Of 8-bit Data Width Sram Connection413................................................................................................................................................................

Figure 13.10 Sram Interface Wait Timing (software Wait Only)414................................................................................................................................................................

Figure 13.12 Sram Interface Wait State Timing (read Strobe Negate Timing Setting)416................................................................................................................................................................

Dram Interface417................................................................................................................................................................

Table 13.14 Relationship Between Amxext And Amx2–0 Bits And Address Multiplexing418................................................................................................................................................................

Figure 13.14 Basic Dram Access Timing419................................................................................................................................................................

Figure 13.15 Dram Wait State Timing420................................................................................................................................................................

Figure 13.16 Dram Burst Access Timing421................................................................................................................................................................

Figure 13.17 Dram Bus Cycle (edo Mode, Rcd = 0, Anw = 0, Tpc = 1)422................................................................................................................................................................

Figure 13.18 Burst Access Timing In Dram Edo Mode423................................................................................................................................................................

Figure 13.19(1) Dram Burst Bus Cycle, Ras Down Mode Start Fast Page Mode, Rcd = 0, Anw = 0)424................................................................................................................................................................

Figure 13.19(2) Dram Burst Bus Cycle, Ras Down Mode Continuation Fast Page Mode, Rcd = 0, Anw = 0)425................................................................................................................................................................

Figure 13.19(3) Dram Burst Bus Cycle, Ras Down Mode Start Edo Mode, Rcd = 0, Anw = 0)426................................................................................................................................................................

Figure 13.19(4) Dram Burst Bus Cycle, Ras Down Mode Continuation Edo Mode, Rcd = 0, Anw = 0)427................................................................................................................................................................

Figure 13.20 Cas-before-ras Refresh Operation428................................................................................................................................................................

Figure 13.21 Dram Cas-before-ras Refresh Cycle Timing (tras = 0, Trc = 1)429................................................................................................................................................................

Figure 13.22 Dram Self-refresh Cycle Timing431................................................................................................................................................................

Synchronous Dram Interface432................................................................................................................................................................

Figure 13.23 Example Of 32-bit Data Width Synchronous Dram Connection (area 3)433................................................................................................................................................................

Table 13.15 Example Of Correspondence Between Sh7751 Series And Synchronous Dram Address Pins (32-bit Bus Width, Amx2–amx0 = 000, Amxext = 0)434................................................................................................................................................................

Figure 13.24 Basic Timing For Synchronous Dram Burst Read435................................................................................................................................................................

Figure 13.25 Basic Timing For Synchronous Dram Single Read437................................................................................................................................................................

Figure 13.26 Basic Timing For Synchronous Dram Burst Write438................................................................................................................................................................

Figure 13.27 Basic Timing For Synchronous Dram Single Write440................................................................................................................................................................

Figure 13.28 Burst Read Timing442................................................................................................................................................................

Figure 13.29 Burst Read Timing (ras Down, Same Row Address)443................................................................................................................................................................

Figure 13.30 Burst Read Timing (ras Down, Different Row Addresses)444................................................................................................................................................................

Figure 13.31 Burst Write Timing445................................................................................................................................................................

Figure 13.32 Burst Write Timing (same Row Address)446................................................................................................................................................................

Figure 13.33 Burst Write Timing (different Row Addresses)447................................................................................................................................................................

Table 13.16 Cycles In Which Pipelined Access Can Be Used448................................................................................................................................................................

Burst Read Cycle449................................................................................................................................................................

Figure 13.35 Auto-refresh Operation450................................................................................................................................................................

Figure 13.36 Synchronous Dram Auto-refresh Timing451................................................................................................................................................................

Figure 13.37 Synchronous Dram Self-refresh Timing452................................................................................................................................................................

Figure 13.38(1) Synchronous Dram Mode Write Timing (pall)454................................................................................................................................................................

Figure 13.38(2) Synchronous Dram Mode Write Timing (mode Register Setting)455................................................................................................................................................................

Figure 13.40 Basic Timing Of A Burst Write To Synchronous Dram457................................................................................................................................................................

Burst Rom Interface458................................................................................................................................................................

Figure 13.41 Burst Rom Basic Access Timing459................................................................................................................................................................

Figure 13.42 Burst Rom Wait Access Timing460................................................................................................................................................................

Pcmcia Interface461................................................................................................................................................................

Table 13.17 Relationship Between Address And Ce When Using Pcmcia Interface463................................................................................................................................................................

Figure 13.44 Example Of Pcmcia Interface465................................................................................................................................................................

Figure 13.45 Basic Timing For Pcmcia Memory Card Interface466................................................................................................................................................................

Figure 13.46 Wait Timing For Pcmcia Memory Card Interface467................................................................................................................................................................

Figure 13.47 Pcmcia Space Allocation468................................................................................................................................................................

Figure 13.48 Basic Timing For Pcmcia I/o Card Interface469................................................................................................................................................................

Figure 13.49 Wait Timing For Pcmcia I/o Card Interface470................................................................................................................................................................

Figure 13.50 Dynamic Bus Sizing Timing For Pcmcia I/o Card Interface471................................................................................................................................................................

Mpx Interface472................................................................................................................................................................

Figure 13.51 Example Of 32-bit Data Width Mpx Connection473................................................................................................................................................................

Figure 13.52 Mpx Interface Timing474................................................................................................................................................................

Figure 13.53 Mpx Interface Timing475................................................................................................................................................................

Figure 13.54 Mpx Interface Timing476................................................................................................................................................................

Figure 13.55 Mpx Interface Timing477................................................................................................................................................................

Figure 13.56 Mpx Interface Timing478................................................................................................................................................................

Figure 13.57 Mpx Interface Timing479................................................................................................................................................................

Figure 13.58 Mpx Interface Timing480................................................................................................................................................................

Figure 13.59 Mpx Interface Timing481................................................................................................................................................................

Figure 13.60 Mpx Interface Timing482................................................................................................................................................................

Figure 13.61 Mpx Interface Timing483................................................................................................................................................................

Figure 13.62 Mpx Interface Timing484................................................................................................................................................................

Figure 13.63 Mpx Interface Timing485................................................................................................................................................................

Figure 13.64 Mpx Interface Timing486................................................................................................................................................................

Figure 13.65 Mpx Interface Timing487................................................................................................................................................................

Figure 13.66 Mpx Interface Timing488................................................................................................................................................................

Figure 13.67 Mpx Interface Timing489................................................................................................................................................................

Byte Control Sram Interface490................................................................................................................................................................

Figure 13.69 Byte Control Sram Basic Read Cycle (no Wait)491................................................................................................................................................................

Figure 13.70 Byte Control Sram Basic Read Cycle (one Internal Wait Cycle)492................................................................................................................................................................

Figure 13.71 Byte Control Sram Basic Read Cycle (one Internal Wait + One External Wait)493................................................................................................................................................................

Waits Between Access Cycles494................................................................................................................................................................

Figure 13.72 Waits Between Access Cycles495................................................................................................................................................................

Bus Arbitration496................................................................................................................................................................

Figure 13.73 Arbitration Sequence498................................................................................................................................................................

Master Mode499................................................................................................................................................................

Slave Mode500................................................................................................................................................................

Notes On Usage501................................................................................................................................................................

Section 14 Direct Memory Access Controller (dmac)502................................................................................................................................................................

Block Diagram (sh7751)505................................................................................................................................................................

Pin Configuration (sh7751)506................................................................................................................................................................

Register Configuration (sh7751)507................................................................................................................................................................

Dma Destination Address Registers 0–3 (dar0–dar3)510................................................................................................................................................................

Dma Transfer Count Registers 0–3 (dmatcr0–dmatcr3)511................................................................................................................................................................

Dma Channel Control Registers 0–3 (chcr0–chcr3)512................................................................................................................................................................

Dma Operation Register (dmaor)520................................................................................................................................................................

Figure 14.2 Dmac Transfer Flowchart524................................................................................................................................................................

Dma Transfer Requests525................................................................................................................................................................

Table 14.4 Selecting External Request Mode With Rs Bits526................................................................................................................................................................

Table 14.5 Selecting On-chip Peripheral Module Request Mode With Rs Bits528................................................................................................................................................................

Channel Priorities529................................................................................................................................................................

Figure 14.3 Round Robin Mode530................................................................................................................................................................

Figure 14.4 Example Of Changes In Priority Order In Round Robin Mode531................................................................................................................................................................

Types Of Dma Transfer532................................................................................................................................................................

Figure 14.5 Data Flow In Single Address Mode533................................................................................................................................................................

Figure 14.6 Dma Transfer Timing In Single Address Mode534................................................................................................................................................................

Figure 14.7 Operation In Dual Address Mode535................................................................................................................................................................

Figure 14.8 Example Of Transfer Timing In Dual Address Mode536................................................................................................................................................................

Figure 14.9 Example Of Dma Transfer In Cycle Steal Mode537................................................................................................................................................................

Table 14.7 Relationship Between Dma Transfer Type, Request Mode, And Bus Mode538................................................................................................................................................................

Table 14.8 External Request Transfer Sources And Destinations In Normal Mode539................................................................................................................................................................

Table 14.9 External Request Transfer Sources And Destinations In Ddt Mode540................................................................................................................................................................

Figure 14.11 Bus Handling With Two Dmac Channels Operating541................................................................................................................................................................

Figure 14.12 Dual Address Mode/cycle Steal Mode External Bus External Bus Level Detection), Dack (read Cycle)544................................................................................................................................................................

Figure 14.13 Dual Address Mode/cycle Steal Mode External Bus External Bus Edge Detection), Dack (read Cycle)545................................................................................................................................................................

Figure 14.14 Dual Address Mode/burst Mode External Bus External Bus Level Detection), Dack (read Cycle)546................................................................................................................................................................

Edge Detection), Dack (read Cycle)547................................................................................................................................................................

Figure 14.16 Dual Address Mode/cycle Steal Mode On-chip Sci (level Detection External Bus548................................................................................................................................................................

Level Detection)/32-byte Block Transfer (bus Width: 32 Bits, Sdram Row Hit Write)554................................................................................................................................................................

Ending Dma Transfer555................................................................................................................................................................

Examples Of Use558................................................................................................................................................................

On-demand Data Transfer Mode (ddt Mode)559................................................................................................................................................................

Pins In Ddt Mode561................................................................................................................................................................

Figure 14.25 Data Transfer Request Format562................................................................................................................................................................

Table 14.11 Usable Sz, Id, And Md Combination In Ddt Mode563................................................................................................................................................................

Transfer Request Acceptance On Each Channel564................................................................................................................................................................

Transfer Sdram Auto-precharge Read Bus Cycle, Burst (rcd=1, Cas Latency=3, Tpc=3)565................................................................................................................................................................

Figure 14.28 Dual Address Mode/synchronous Dram Sram Longword Transfer567................................................................................................................................................................

Figure 14.33 Handshake Protocol Using Data Bus (channel 0 On-demand Data Transfer)571................................................................................................................................................................

Figure 14.34 Handshake Protocol Without Use Of Data Bus (channel 0 On-demand Data Transfer)572................................................................................................................................................................

Figure 14.35 Read From Synchronous Dram Precharge Bank573................................................................................................................................................................

Figure 14.37 Read From Synchronous Dram (row Hit)574................................................................................................................................................................

Figure 14.39 Write To Synchronous Dram Non-precharge Bank (row Miss)575................................................................................................................................................................

Figure 14.42 Ddt Mode Setting577................................................................................................................................................................

Figure 14.47 Single Address Mode/burst Mode/32-byte Block Transfer/dma Transfer Request To Channels 1–3 Using Data Bus580................................................................................................................................................................

Without Using Data Bus581................................................................................................................................................................

Notes On Use Of Ddt Module586................................................................................................................................................................

Configuration Of The Dmac (sh7751r)589................................................................................................................................................................

Pin Configuration (sh7751r)590................................................................................................................................................................

Register Configuration (sh7751r)591................................................................................................................................................................

Table 14.14 Register Configuration592................................................................................................................................................................

Register Descriptions (sh7751r)594................................................................................................................................................................

Dma Transfer Count Registers 0–7 (dmatcr0–dmatcr7)595................................................................................................................................................................

Figure 14.54 Dtr Format (transfer Request Format) (sh7751r)599................................................................................................................................................................

Operation (sh7751r)601................................................................................................................................................................

Clearing Request Queues By Dtr Format602................................................................................................................................................................

Interrupt-request Codes603................................................................................................................................................................

Table 14.19 Dmac Interrupt-request Codes604................................................................................................................................................................

Figure 14.56 Single Address Mode/cycle Steal Mode/external Bus External Device 32-byte Block Transfer/on-demand Data Transfer On Channel 4605................................................................................................................................................................

Section 15 Serial Communication Interface (sci)608................................................................................................................................................................

Transmit Shift Register (sctsr1)613................................................................................................................................................................

Serial Mode Register (scsmr1)614................................................................................................................................................................

Serial Control Register (scscr1)616................................................................................................................................................................

Serial Status Register (scssr1)620................................................................................................................................................................

Serial Port Register (scsptr1)624................................................................................................................................................................

Figure 15.3 Txd Pin627................................................................................................................................................................

Bit Rate Register (scbrr1)628................................................................................................................................................................

Table 15.3 Examples Of Bit Rates And Scbrr1 Settings In Asynchronous Mode630................................................................................................................................................................

Table 15.4 Examples Of Bit Rates And Scbrr1 Settings In Synchronous Mode633................................................................................................................................................................

Table 15.6 Maximum Bit Rate With External Clock Input (asynchronous Mode)635................................................................................................................................................................

Table 15.8 Scsmr1 Settings For Serial Transfer Format Selection637................................................................................................................................................................

Operation In Asynchronous Mode638................................................................................................................................................................

Table 15.10 Serial Transfer Formats (asynchronous Mode)639................................................................................................................................................................

Figure 15.7 Sample Sci Initialization Flowchart641................................................................................................................................................................

Figure 15.8 Sample Serial Transmission Flowchart642................................................................................................................................................................

Figure 15.10 Sample Serial Reception Flowchart (1)645................................................................................................................................................................

Table 15.11 Receive Error Conditions647................................................................................................................................................................

Multiprocessor Communication Function648................................................................................................................................................................

Figure 15.13 Sample Multiprocessor Serial Transmission Flowchart651................................................................................................................................................................

Figure 15.15 Sample Multiprocessor Serial Reception Flowchart (1)654................................................................................................................................................................

Operation In Synchronous Mode657................................................................................................................................................................

Figure 15.18 Sample Sci Initialization Flowchart659................................................................................................................................................................

Figure 15.19 Sample Serial Transmission Flowchart660................................................................................................................................................................

Figure 15.20 Example Of Sci Transmit Operation661................................................................................................................................................................

Figure 15.21 Sample Serial Reception Flowchart (1)662................................................................................................................................................................

Figure 15.22 Example Of Sci Receive Operation664................................................................................................................................................................

Figure 15.23 Sample Flowchart For Serial Data Transmission And Reception665................................................................................................................................................................

Sci Interrupt Sources And Dmac666................................................................................................................................................................

Figure 15.24 Receive Data Sampling Timing In Asynchronous Mode669................................................................................................................................................................

Figure 15.25 Example Of Synchronous Transmission By Dmac670................................................................................................................................................................

Section 16 Serial Communication Interface With Fifo (scif)672................................................................................................................................................................

Transmit Shift Register (sctsr2)677................................................................................................................................................................

Serial Mode Register (scsmr2)678................................................................................................................................................................

Serial Control Register (scscr2)680................................................................................................................................................................

Serial Status Register (scfsr2)683................................................................................................................................................................

Bit Rate Register (scbrr2)689................................................................................................................................................................

Fifo Control Register (scfcr2)690................................................................................................................................................................

Fifo Data Count Register (scfdr2)693................................................................................................................................................................

Serial Port Register (scsptr2)694................................................................................................................................................................

Figure 16.2 Md8/rts2 Pin697................................................................................................................................................................

Figure 16.3 Md7/cts2 Pin698................................................................................................................................................................

Figure 16.4 Md1/txd2 Pin699................................................................................................................................................................

Figure 16.6 Md0/sck2 Pin700................................................................................................................................................................

Line Status Register (sclsr2)701................................................................................................................................................................

Serial Operation703................................................................................................................................................................

Table 16.5 Serial Transfer Formats704................................................................................................................................................................

Figure 16.7 Sample Scif Initialization Flowchart706................................................................................................................................................................

Figure 16.8 Sample Serial Transmission Flowchart707................................................................................................................................................................

Figure 16.9 Example Of Transmit Operation (example With 8-bit Data, Parity One Stop Bit)709................................................................................................................................................................

Figure 16.11 Sample Serial Reception Flowchart (1)710................................................................................................................................................................

Figure 16.11 Sample Serial Reception Flowchart (2)711................................................................................................................................................................

Figure 16.12 Example Of Scif Receive Operation (example With 8-bit Data, Parity One Stop Bit)713................................................................................................................................................................

Scif Interrupt Sources And The Dmac714................................................................................................................................................................

Figure 16.14 Receive Data Sampling Timing In Asynchronous Mode716................................................................................................................................................................

Section 17 Smart Card Interface718................................................................................................................................................................

Pin Connections726................................................................................................................................................................

Data Format727................................................................................................................................................................

Register Settings728................................................................................................................................................................

Figure 17.4 Tend Generation Timing729................................................................................................................................................................

Clock730................................................................................................................................................................

Table 17.5 Examples Of Bit Rate B (bits/s) For Various Scbrr1 Settings (when N = 0)731................................................................................................................................................................

Figure 17.6 Difference In Clock Output According To Gm Bit Setting732................................................................................................................................................................

Data Transfer Operations733................................................................................................................................................................

Figure 17.7 Sample Initialization Flowchart734................................................................................................................................................................

Figure 17.8 Sample Transmission Processing Flowchart736................................................................................................................................................................

Figure 17.9 Sample Reception Processing Flowchart738................................................................................................................................................................

Table 17.9 Smart Card Mode Operating States And Interrupt Sources739................................................................................................................................................................

Figure 17.11 Retransfer Operation In Sci Receive Mode741................................................................................................................................................................

Figure 17.12 Retransfer Operation In Sci Transmit Mode742................................................................................................................................................................

Figure 17.13 Procedure For Stopping And Restarting The Clock743................................................................................................................................................................

Section 18 I/o Ports746................................................................................................................................................................

Block Diagrams747................................................................................................................................................................

Figure 18.2 16-bit Port B748................................................................................................................................................................

Figure 18.3 Sck Pin749................................................................................................................................................................

Figure 18.4 Txd Pin750................................................................................................................................................................

Figure 18.6 Md1/txd2 Pin751................................................................................................................................................................

Figure 18.8 Md0/sck2 Pin752................................................................................................................................................................

Figure 18.9 Md7/cts2 Pin753................................................................................................................................................................

Table 18.2 Sci I/o Port Pins756................................................................................................................................................................

Port Data Register A (pdtra)759................................................................................................................................................................

Port Data Register B (pdtrb)761................................................................................................................................................................

Section 19 Interrupt Controller (intc)768................................................................................................................................................................

Figure 19.1 Block Diagram Of Intc769................................................................................................................................................................

Interrupt Sources771................................................................................................................................................................

Irl Interrupts772................................................................................................................................................................

On-chip Peripheral Module Interrupts774................................................................................................................................................................

Interrupt Exception Handling And Priority775................................................................................................................................................................

Table 19.4 Interrupt Exception Handling Sources And Priority Order776................................................................................................................................................................

Interrupt Control Register (icr)779................................................................................................................................................................

Interrupt Priority Level Settting Register 00 (intpri00)781................................................................................................................................................................

Interrupt Factor Register 00 (intreq00)782................................................................................................................................................................

Interrupt Mask Register 00 (intmsk00)783................................................................................................................................................................

Interrupt Mask Clear Register 00 (intmskclr00)784................................................................................................................................................................

Intreq00, Intmsk00, And Intmskclr00 Bit Allocation785................................................................................................................................................................

Intc Operation786................................................................................................................................................................

Figure 19.3 Interrupt Operation Flowchart787................................................................................................................................................................

Multiple Interrupts788................................................................................................................................................................

Interrupt Response Time789................................................................................................................................................................

Section 20 User Break Controller (ubc)790................................................................................................................................................................

Table 20.1 Ubc Registers792................................................................................................................................................................

Break Address Register A (bara)794................................................................................................................................................................

Break Asid Register A (basra)795................................................................................................................................................................

Break Bus Cycle Register A (bbra)796................................................................................................................................................................

Break Address Register B (barb)798................................................................................................................................................................

Break Data Mask Register B (bdmrb)799................................................................................................................................................................

Break Bus Cycle Register B (bbrb)800................................................................................................................................................................

Explanation Of Terms Relating To Instruction Intervals803................................................................................................................................................................

User Break Operation Sequence804................................................................................................................................................................

Instruction Access Cycle Break805................................................................................................................................................................

Operand Access Cycle Break806................................................................................................................................................................

Condition Match Flag Setting807................................................................................................................................................................

Contiguous A And B Settings For Sequential Conditions808................................................................................................................................................................

User Break Debug Support Function810................................................................................................................................................................

Figure 20.2 User Break Debug Support Function Flowchart811................................................................................................................................................................

User Break Controller Stop Function814................................................................................................................................................................

Examples Of Stopping And Restarting The User Break Controller815................................................................................................................................................................

Section 21 Hitachi User Debug Interface (h-udi)816................................................................................................................................................................

Figure 21.1 Block Diagram Of H-udi Circuit817................................................................................................................................................................

Data Register (sddr)821................................................................................................................................................................

Interrupt Factor Register (sdint)822................................................................................................................................................................

Table 21.3 Structure Of Boundary Scan Register823................................................................................................................................................................

H-udi Reset838................................................................................................................................................................

Boundary Scan (extest, Sample/preload, Bypass)839................................................................................................................................................................

Section 22 Pci Controller (pcic)840................................................................................................................................................................

Table 22.2 List Of Pci Configuration Registers845................................................................................................................................................................

Table 22.3 Pci Configuration Register Configuration846................................................................................................................................................................

Table 22.4 List Of Pcic Local Registers847................................................................................................................................................................

Pcic Register Descriptions850................................................................................................................................................................

Pci Configuration Register 1 (pciconf1)851................................................................................................................................................................

Pci Configuration Register 2 (pciconf2)856................................................................................................................................................................

Table 22.5 List Of Class23 To 16 Base Class Codes (class23 To 16)857................................................................................................................................................................

Pci Configuration Register 3 (pciconf3)858................................................................................................................................................................

Pci Configuration Register 4 (pciconf4)860................................................................................................................................................................

Pci Configuration Register 5 (pciconf5)862................................................................................................................................................................

Table 22.6 Memory Space Base Address Register (base0)863................................................................................................................................................................

Pci Configuration Register 6 (pciconf6)864................................................................................................................................................................

Table 22.7 Memory Space Base Address Register (base1)865................................................................................................................................................................

Pci Configuration Register 7 (pciconf7) To Pci Configuration Register866................................................................................................................................................................

Pci Configuration Register 11 (pciconf11)867................................................................................................................................................................

Pci Configuration Register 12 (pciconf12)868................................................................................................................................................................

Pci Configuration Register 13 (pciconf13)869................................................................................................................................................................

Pci Configuration Register 14 (pciconf14)870................................................................................................................................................................

Pci Configuration Register 15 (pciconf15)871................................................................................................................................................................

Pci Configuration Register 16 (pciconf16)873................................................................................................................................................................

Pci Configuration Register 17 (pciconf17)875................................................................................................................................................................

Reserved Area877................................................................................................................................................................

Pci Control Register (pcicr)878................................................................................................................................................................

Pci Local Space Register [1:0] (pcilsr [1:0])881................................................................................................................................................................

Pci Local Address Register [1:0] (pcilar [1:0])883................................................................................................................................................................

Pci Interrupt Register (pciint)885................................................................................................................................................................

Pci Interrupt Mask Register (pciintm)887................................................................................................................................................................

Pci Address Data Register At Error (pcialr)889................................................................................................................................................................

Pci Command Data Register At Error (pciclr)890................................................................................................................................................................

Pci Arbiter Interrupt Register (pciaint)892................................................................................................................................................................

Pci Arbiter Interrupt Mask Register (pciaintm)894................................................................................................................................................................

Pci Error Bus Master Data Register (pcibmlr)895................................................................................................................................................................

Pci Dma Transfer Arbitration Register (pcidmabt)896................................................................................................................................................................

Pci Dma Transfer Pci Address Register [3:0] (pcidpa [3:0])897................................................................................................................................................................

Pci Dma Transfer Local Bus Start Address Register [3:0] (pcidla [3:0])898................................................................................................................................................................

Pci Dma Transfer Counter Register [3:0] (pcidtc [3:0])899................................................................................................................................................................

Pci Dma Control Register [3:0] (pcidcr [3:0])901................................................................................................................................................................

Pio Address Register (pcipar)904................................................................................................................................................................

Memory Space Base Register (pcimbr)906................................................................................................................................................................

I/o Space Base Register (pciiobr)907................................................................................................................................................................

Pci Power Management Interrupt Register (pcipint)909................................................................................................................................................................

Pci Power Management Interrupt Mask Register (pcipintm)910................................................................................................................................................................

Pci Clock Control Register (pciclkr)911................................................................................................................................................................

Pcic-bsc Registers912................................................................................................................................................................

Port Control Register (pcipctr)913................................................................................................................................................................

Port Data Register (pcipdtr)916................................................................................................................................................................

Pio Data Register (pcipdr)917................................................................................................................................................................

Description Of Operation918................................................................................................................................................................

Pci Commands919................................................................................................................................................................

Pcic Initialization920................................................................................................................................................................

Local Register Access921................................................................................................................................................................

Pci Bus Arbitration In Non-host Mode924................................................................................................................................................................

Figure 22.2 Pio Memory Space Access926................................................................................................................................................................

Target Transfers927................................................................................................................................................................

Figure 22.4 Local Address Space Accessing Method928................................................................................................................................................................

Dma Transfers930................................................................................................................................................................

Figure 22.5 Example Of Dma Transfer Control Register Settings932................................................................................................................................................................

Figure 22.6 Example Of Dma Transfer Flowchart934................................................................................................................................................................

Transfer Contention Within Pcic936................................................................................................................................................................

Pci Bus Basic Interface937................................................................................................................................................................

Figure 22.7 Master Write Cycle In Host Mode (single)938................................................................................................................................................................

Figure 22.8 Master Read Cycle In Host Mode (single)939................................................................................................................................................................

Figure 22.9 Master Memory Write Cycle In Non-host Mode (burst)940................................................................................................................................................................

Figure 22.10 Master Memory Read Cycle In Non-host Mode (burst)941................................................................................................................................................................

Figure 22.11 Target Read Cycle In Non-host Mode (single)943................................................................................................................................................................

Figure 22.12 Target Write Cycle In Non-host Mode (single)944................................................................................................................................................................

Figure 22.13 Target Memory Read Cycle In Host Mode (burst)945................................................................................................................................................................

Figure 22.14 Target Memory Write Cycle In Host Mode (burst)946................................................................................................................................................................

Figure 22.15 Master Memory Write Cycle In Host Mode (burst, With Stepping)947................................................................................................................................................................

Figure 22.16 Target Memory Read Cycle In Host Mode (burst, With Stepping)948................................................................................................................................................................

Endians949................................................................................................................................................................

Table 22.10 Access Size950................................................................................................................................................................

Endian Control For Local Bus951................................................................................................................................................................

Figure 22.20 Data Alignment At Dma Transfer952................................................................................................................................................................

Endian Control In Target Transfers (memory Read/memory Write)953................................................................................................................................................................

Figure 22.21(1) Data Alignment At Target Memory Transfer (big-endian Local Bus)954................................................................................................................................................................

Figure 22.21(2) Data Alignment At Target Memory Transfer (little-endian Local Bus)955................................................................................................................................................................

Endian Control In Target Transfers (i/o Read/i/o Write)956................................................................................................................................................................

Resetting958................................................................................................................................................................

Interrupts From External Pci Devices960................................................................................................................................................................

Error Detection961................................................................................................................................................................

Power Management962................................................................................................................................................................

Stopping The Clock963................................................................................................................................................................

Table 22.14 Method Of Stopping Clock Per Operating Mode964................................................................................................................................................................

Compatibility With Standby And Sleep966................................................................................................................................................................

Version Management967................................................................................................................................................................

Section 23 Electrical Characteristics968................................................................................................................................................................

Dc Characteristics969................................................................................................................................................................

Table 23.3 Dc Characteristics (hd6417751rf240)971................................................................................................................................................................

Table 23.4 Dc Characteristics (hd6417751rbp200)973................................................................................................................................................................

Table 23.5 Dc Characteristics (hd6417751rf200)975................................................................................................................................................................

Table 23.6 Dc Characteristics (hd6417751bp167)977................................................................................................................................................................

Table 23.7 Dc Characteristics (hd6417751bp167i)979................................................................................................................................................................

Table 23.8 Dc Characteristics (hd6417751f167)981................................................................................................................................................................

Table 23.9 Dc Characteristics (hd6417751f167i)983................................................................................................................................................................

Table 23.10 Dc Characteristics (hd6417751vf133)985................................................................................................................................................................

Ac Characteristics987................................................................................................................................................................

Table 23.14 Clock Timing (hd6417751rbp200)988................................................................................................................................................................

Clock And Control Signal Timing989................................................................................................................................................................

Table 23.19 Clock And Control Signal Timing (hd6417751rf240)990................................................................................................................................................................

Table 23.20 Clock And Control Signal Timing (hd6417751rbp200)991................................................................................................................................................................

Table 23.21 Clock And Control Signal Timing (hd6417751rf200)992................................................................................................................................................................

Table 23.22 Clock And Control Signal Timing (hd6417751bp167, Hd6417751f167 Hd6417751bp167i, Hd6417751f167i)993................................................................................................................................................................

Table 23.23 Clock And Control Signal Timing (hd6417751vf133)994................................................................................................................................................................

Figure 23.1 Extal Clock Input Timing995................................................................................................................................................................

Figure 23.3 Power-on Oscillation Settling Time996................................................................................................................................................................

Figure 23.5 Power-on Oscillation Settling Time997................................................................................................................................................................

Figure 23.7 Standby Return Oscillation Settling Time (return By Nmi)998................................................................................................................................................................

Figure 23.10 Pll Synchronization Settling Time In Case Of Irl Interrupt999................................................................................................................................................................

Control Signal Timing1000................................................................................................................................................................

Table 23.25 Control Signal Timing (2)1001................................................................................................................................................................

Figure 23.11 Control Signal Timing1002................................................................................................................................................................

Bus Timing1003................................................................................................................................................................

Table 23.27 Bus Timing (2)1005................................................................................................................................................................

Figure 23.13 Sram Bus Cycle: Basic Bus Cycle (no Wait)1007................................................................................................................................................................

Figure 23.14 Sram Bus Cycle: Basic Bus Cycle (one Internal Wait)1008................................................................................................................................................................

Figure 23.15 Sram Bus Cycle: Basic Bus Cycle (one Internal Wait + One External Wait)1009................................................................................................................................................................

Figure 23.17 Burst Rom Bus Cycle (no Wait)1011................................................................................................................................................................

Figure 23.18 Burst Rom Bus Cycle (1st Data: One Internal Wait + One External Wait 2nd/3rd/4th Data: One Internal Wait)1012................................................................................................................................................................

Figure 23.19 Burst Rom Bus Cycle (no Wait, Address Setup/hold Time Insertion Ans = 1, Anh = 1)1013................................................................................................................................................................

Figure 23.20 Burst Rom Bus Cycle (one Internal Wait + One External Wait)1014................................................................................................................................................................

Figure 23.21 Synchronous Dram Auto-precharge Read Bus Cycle Single (rcd [1:0] = 01, Cas Latency = 3, Tpc [2:0] = 011)1015................................................................................................................................................................

Figure 23.22 Synchronous Dram Auto-precharge Read Bus Cycle Burst (rcd [1:0] = 01, Cas Latency = 3, Tpc [2:0] = 011)1016................................................................................................................................................................

Figure 23.23 Synchronous Dram Normal Read Bus Cycle: Act + Read Commands Burst (rcd [1:0] = 01, Cas Latency = 3)1017................................................................................................................................................................

Figure 23.24 Synchronous Dram Normal Read Bus Cycle: Pre + Act + Read Commands, Burst (rcd [1:0] = 01, Tpc [2:0] = 001, Cas Latency = 3)1018................................................................................................................................................................

Figure 23.25 Synchronous Dram Normal Read Bus Cycle: Read Command Burst (cas Latency = 3)1019................................................................................................................................................................

Single (rcd [1:0] = 01, Tpc [2:0] = 001, Trwl [2:0] = 010)1020................................................................................................................................................................

Figure 23.27 Synchronous Dram Auto-precharge Write Bus Cycle Burst (rcd [1:0] = 01, Tpc [2:0] = 001, Trwl [2:0] = 010)1021................................................................................................................................................................

Figure 23.28 Synchronous Dram Normal Write Bus Cycle: Act + Write Commands Burst (rcd [1:0] = 01, Trwl [2:0] = 010)1022................................................................................................................................................................

Figure 23.29 Synchronous Dram Normal Write Bus Cycle: Pre + Act + Write Commands, Burst (rcd [1:0] = 01, Tpc [2:0] = 001, Trwl [2:0] = 010)1023................................................................................................................................................................

Figure 23.30 Synchronous Dram Normal Write Bus Cycle: Write Command Burst (trwl [2:0] = 010)1024................................................................................................................................................................

Figure 23.31 Synchronous Dram Bus Cycle: Precharge Command (tpc [2:0] = 001)1025................................................................................................................................................................

Figure 23.33 Synchronous Dram Bus Cycle: Self-refresh (trc [2:0] = 001)1027................................................................................................................................................................

Figure 23.34(a) Synchronous Dram Bus Cycle: Mode Register Setting (pall)1028................................................................................................................................................................

Figure 23.34(b) Synchronous Dram Bus Cycle: Mode Register Setting (set)1029................................................................................................................................................................

Figure 23.39 Dram Burst Bus Cycle (edo Mode, Rcd [1:0] = 01, Anw [2:0]1034................................................................................................................................................................

Figure 23.44 Dram Burst Bus Cycle (fast Page Mode, Rcd [1:0] = 01, Anw [2:0]1039................................................................................................................................................................

Figure 23.49 Dram Bus Cycle: Dram Self-refresh (trc [2:0] = 001)1044................................................................................................................................................................

Wait1045................................................................................................................................................................

St Data (one Internal Wait 2) 1st Data (one Internal Wait + One External Wait)1048................................................................................................................................................................

St Data (one Internal Wait 3) 1st Data (one Internal Wait + One External Wait)1049................................................................................................................................................................

St Data (one Internal Wait), 2nd To 8th Data (no Internal Wait + External Wait Control)1051................................................................................................................................................................

Basic Read Cycle (one Internal Wait 3) Basic Read Cycle (one Internal Wait + One External Wait)1052................................................................................................................................................................

Figure 23.58 Memory Byte Control Sram Bus Cycle: Basic Read Cycle (no Wait Address Setup/hold Time Insertion, Ans [0] = 1, Anh [1:0] = 01)1053................................................................................................................................................................

Peripheral Module Signal Timing1054................................................................................................................................................................

Table 23.29 Peripheral Module Signal Timing (2)1056................................................................................................................................................................

Figure 23.59 Tclk Input Timing1058................................................................................................................................................................

Figure 23.63 I/o Port Input/output Timing1059................................................................................................................................................................

Figure 23.65 Tck Input Timing1060................................................................................................................................................................

Nmi Input Timing1061................................................................................................................................................................

Table 23.30 Pcic Signal Timing (in Pcireq/pcignt Non-port Mode) (1)1062................................................................................................................................................................

Table 23.31 Pcic Signal Timing (in Pcireq/pcignt Non-port Mode) (2)1063................................................................................................................................................................

Pci Clock Input Timing1064................................................................................................................................................................

Output Signal Timing1065................................................................................................................................................................

I/o Port Input/output Timing1066................................................................................................................................................................

Output Load Circuit1067................................................................................................................................................................

Appendix A Address List1070................................................................................................................................................................

Appendix B Package Dimensions1078................................................................................................................................................................

Package Dimensions (256-pin Bga)1079................................................................................................................................................................

Appendix C Mode Pin Settings1080................................................................................................................................................................

Table C.3 Area 0 Memory Map And Bus Width1081................................................................................................................................................................

Table C.7 Pci Mode1082................................................................................................................................................................

Appendix D Pin Functions1083................................................................................................................................................................

Table D.2 Pin States In Reset, Power-down State, And Bus-released State (pci Enable)1085................................................................................................................................................................

Table D.3 Pin States In Reset, Power-down State, And Bus-released State (pci Disable)1086................................................................................................................................................................

D.2 Handling Of Unused Pins1087................................................................................................................................................................

Table D.4 Handling Of Pins When Pci Is Not Used1088................................................................................................................................................................

Appendix F Instruction Prefetching And Its Side Effects1100................................................................................................................................................................

Appendix G Power-on And Power-off Procedures1101................................................................................................................................................................

Appendix H List Of Models1102................................................................................................................................................................