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Hitachi SH7751 manual available for free PDF download: Hardware Manual
Hitachi SH7751 Hardware Manual (1104 pages)
SuperH RISC engine
Brand:
Hitachi
| Category:
Engine
| Size: 5.43 MB
Table of Contents
6
Table of Contents
40
Section 1 Overview
40
SH7751 Series Features
41
Figure 13.61 MPX Interface Timing
41
Table 1.1 SH7751 Series Features
49
Block Diagram
49
Figure 1.1 Block Diagram of SH7751 Series Functions
50
Pin Arrangement
50
Figure 1.2 Pin Arrangement (256-Pin QFP)
51
Figure 1.3 Pin Arrangement (256-Pin BGA)
52
Pin Functions
52
Pin Functions (256-Pin QFP)
52
Table 1.2 Pin Functions
63
Pin Functions (256-Pin BGA)
63
Table 1.3 Pin Functions
74
Section 2 Programming Model
74
Data Formats
74
Figure 2.1 Data Formats
75
Register Configuration
75
Privileged Mode and Banks
76
Table 2.1 Initial Register Values
77
Figure 2.2 CPU Register Configuration in Each Processor Mode
78
General Registers
79
Figure 2.3 General Registers
80
Floating-Point Registers
81
Figure 2.4 Floating-Point Registers
82
Control Registers
83
System Registers
85
Memory-Mapped Registers
86
Data Format in Registers
86
Data Formats in Memory
86
Figure 2.5 Data Formats in Memory
87
Processor States
88
Processor Modes
88
Figure 2.6 Processor State Transitions
90
Memory Management Unit (MMU)
90
Overview
90
Features
90
Role of the MMU
92
Figure 3.1 Role of the MMU
93
Register Configuration
93
Caution
93
Table 3.1 MMU Registers
94
Register Descriptions
94
Figure 3.2 Mmu-Related Registers
97
Address Space
97
Physical Address Space
98
Figure 3.3 Physical Address Space (MMUCR.AT = 0)
99
Figure 3.4 P4 Area
100
External Memory Space
100
Figure 3.5 External Memory Space
101
Virtual Address Space
101
Figure 3.6 Virtual Address Space (MMUCR.AT = 1)
102
On-Chip RAM Space
102
Address Translation
103
Single Virtual Memory Mode and Multiple Virtual Memory Mode
103
Address Space Identifier (ASID)
104
TLB Functions
104
Unified TLB (UTLB) Configuration
104
Figure 3.7 UTLB Configuration
105
Figure 3.8 Relationship Between Page Size and Address Format
108
Instruction TLB (ITLB) Configuration
108
Address Translation Method
108
Figure 3.9 ITLB Configuration
109
Figure 3.10 Flowchart of Memory Access Using UTLB
110
Figure 3.11 Flowchart of Memory Access Using ITLB
111
MMU Functions
111
MMU Hardware Management
111
MMU Software Management
111
MMU Instruction (LDTLB)
112
Hardware ITLB Miss Handling
112
Figure 3.12 Operation of LDTLB Instruction
113
Avoiding Synonym Problems
114
MMU Exceptions
114
Instruction TLB Multiple Hit Exception
114
Instruction TLB Miss Exception
115
Instruction TLB Protection Violation Exception
116
Data TLB Multiple Hit Exception
117
Data TLB Miss Exception
118
Data TLB Protection Violation Exception
118
Initial Page Write Exception
119
Memory-Mapped TLB Configuration
120
ITLB Address Array
120
Figure 3.13 Memory-Mapped ITLB Address Array
121
ITLB Data Array 1
121
Figure 3.14 Memory-Mapped ITLB Data Array 1
122
ITLB Data Array 2
122
UTLB Address Array
122
Figure 3.15 Memory-Mapped ITLB Data Array 2
123
Figure 3.16 Memory-Mapped UTLB Address Array
124
UTLB Data Array 1
124
Figure 3.17 Memory-Mapped UTLB Data Array 1
125
UTLB Data Array 2
125
Figure 3.18 Memory-Mapped UTLB Data Array 2
126
Section 4 Caches
126
Overview
126
Features
126
Table 4.1 Cache Features (SH7751)
127
Register Configuration
127
Table 4.2 Cache Features (SH7751R)
127
Table 4.3 Store Queue Features
127
Table 4.4 Cache Control Registers
128
Register Descriptions
128
Figure 4.1 Cache and Store Queue Control Registers (CCR)
130
Operand Cache (OC)
130
Configuration
131
Figure 4.2 Configuration of Operand Cache (SH7751)
132
Figure 4.3 Configuration of Operand Cache (SH7751R)
133
Read Operation
134
Write Operation
136
Write-Back Buffer
136
Write-Through Buffer
136
RAM Mode
136
Figure 4.4 Configuration of Write-Back Buffer
136
Figure 4.5 Configuration of Write-Through Buffer
138
OC Index Mode
138
Coherency Between Cache and External Memory
138
Prefetch Operation
138
Instruction Cache (IC)
138
Configuration
139
Figure 4.6 Configuration of Instruction Cache (SH7751)
140
Figure 4.7 Configuration of Instruction Cache (SH7751R)
141
Read Operation
141
IC Index Mode
142
Memory-Mapped Cache Configuration (SH7751)
142
IC Address Array
143
IC Data Array
143
Figure 4.8 Memory-Mapped IC Address Array
144
OC Address Array
144
Figure 4.9 Memory-Mapped IC Data Array
145
OC Data Array
145
Figure 4.10 Memory-Mapped OC Address Array
146
Memory-Mapped Cache Configuration (SH7751R)
146
Figure 4.11 Memory-Mapped OC Data Array
147
IC Address Array
148
Figure 4.12 Memory-Mapped IC Address Array
148
IC Data Array
149
Figure 4.13 Memory-Mapped IC Data Array
149
OC Address Array
150
Figure 4.14 Memory-Mapped OC Address Array
150
OC Data Array
151
Figure 4.15 Memory-Mapped OC Data Array
151
Summary of Memory-Mapped OC Addresses
152
Store Queues
152
SQ Configuration
152
SQ Writes
152
Transfer to External Memory
152
Figure 4.16 Store Queue Configuration
154
Determination of SQ Access Exception
154
SQ Read (SH7751R Only)
155
SQ Usage Notes
158
Section 5 Exceptions
158
Overview
158
Features
158
Register Configuration
158
Table 5.1 Exception-Related Registers
159
Register Descriptions
159
Figure 5.1 Register Bit Configurations
160
Exception Handling Functions
160
Exception Handling Flow
160
Exception Handling Vector Addresses
161
Exception Types and Priorities
161
Table 5.2 Exceptions
164
Exception Flow
164
Figure 5.2 Instruction Execution and Exception Handling
165
Exception Source Acceptance
166
Figure 5.3 Example of General Exception Acceptance Order
167
Exception Requests and BL Bit
167
Return From Exception Handling
167
Description of Exceptions
168
Resets
169
Table 5.3 Types of Reset
173
General Exceptions
187
Interrupts
190
Priority Order with Multiple Exceptions
191
Usage Notes
192
Restrictions
194
Section 6 Floating-Point Unit
194
Overview
194
Data Formats
194
Floating-Point Format
194
Figure 6.1 Format of Single-Precision Floating-Point Number
195
Figure 6.2 Format of Double-Precision Floating-Point Number
195
Table 6.1 Floating-Point Number Formats and Parameters
196
Non-Numbers (Nan)
196
Table 6.2 Floating-Point Ranges
197
Denormalized Numbers
197
Figure 6.3 Single-Precision Nan Bit Pattern
198
Registers
198
Floating-Point Registers
199
Figure 6.4 Floating-Point Registers
200
Floating-Point Status/Control Register (FPSCR)
201
Floating-Point Communication Register (FPUL)
201
Rounding
202
Floating-Point Exceptions
203
Graphics Support Functions
203
Geometric Operation Instructions
205
Pair Single-Precision Data Transfer
206
Section 7 Instruction Set
206
Execution Environment
208
Addressing Modes
211
Table 7.1 Addressing Modes and Effective Addresses
212
Instruction Set
212
Table 7.2 Notation Used in Instruction List
213
Table 7.3 Fixed-Point Transfer Instructions
216
Table 7.4 Arithmetic Operation Instructions
217
Table 7.5 Logic Operation Instructions
218
Table 7.6 Shift Instructions
219
Table 7.7 Branch Instructions
220
Table 7.8 System Control Instructions
222
Table 7.9 Floating-Point Single-Precision Instructions
223
Table 7.10 Floating-Point Double-Precision Instructions
223
Table 7.11 Floating-Point Control Instructions
224
Table 7.12 Floating-Point Graphics Acceleration Instructions
226
Section 8 Pipelining
226
Pipelines
227
Figure 8.1 Basic Pipelines
228
Figure 8.2 Instruction Execution Patterns
233
Parallel-Executability
233
Table 8.1 Instruction Groups
237
Execution Cycles and Pipeline Stalling
237
Table 8.2 Parallel-Executability
240
Figure 8.3 Examples of Pipelined Execution
244
Table 8.3 Execution Cycles
254
Section 9 Power-Down Modes
254
Overview
254
Types of Power-Down Modes
255
Table 9.1 Status of CPU and Peripheral Modules in Power-Down Modes
256
Register Configuration
256
Pin Configuration
256
Table 9.2 Power-Down Mode Registers
256
Table 9.3 Power-Down Mode Pins
257
Register Descriptions
257
Standby Control Register (STBCR)
259
Peripheral Module Pin High Impedance Control
259
Peripheral Module Pin Pull-Up Control
260
Standby Control Register 2 (STBCR2)
261
Clock Stop Register 00 (CLKSTP00)
262
Clock Stop Clear Register 00 (CLKSTPCLR00)
263
Sleep Mode
263
Transition to Sleep Mode
263
Exit From Sleep Mode
263
Deep Sleep Mode
263
Transition to Deep Sleep Mode
264
Exit From Deep Sleep Mode
264
Pin Sleep Mode
264
Transition to Pin Sleep Mode
264
Exit From Pin Sleep Mode
264
Standby Mode
264
Transition to Standby Mode
265
Exit From Standby Mode
265
Table 9.4 State of Registers in Standby Mode
266
Clock Pause Function
266
Module Standby Function
266
Transition to Module Standby Function
267
Exit From Module Standby Function
268
Hardware Standby Mode
268
Transition to Hardware Standby Mode
268
Exit From Hardware Standby Mode
269
Usage Notes
269
STATUS Pin Change Timing
269
In Reset
269
Figure 9.1 STATUS Output in Power-On Reset
270
In Exit From Standby Mode
270
Figure 9.2 STATUS Output in Manual Reset
270
Figure 9.3 STATUS Output in Standby Interrupt Sequence
271
Figure 9.4 STATUS Output in Standby Power-On Reset Sequence
272
In Exit From Sleep Mode
272
Figure 9.5 STATUS Output in Standby Manual Reset Sequence
272
Figure 9.6 STATUS Output in Sleep Interrupt Sequence
273
Figure 9.7 STATUS Output in Sleep Power-On Reset Sequence
274
Figure 9.8 STATUS Output in Sleep Manual Reset Sequence
275
In Exit From Deep Sleep Mode
275
Figure 9.9 STATUS Output in Deep Sleep Interrupt Sequence
275
Figure 9.10 STATUS Output in Deep Sleep Power-On Reset Sequence
276
Figure 9.11 STATUS Output in Deep Sleep Manual Reset Sequence
277
Hardware Standby Mode Timing
277
Figure 9.12 Hardware Standby Mode Timing (When CA = Low in Normal Operation)
278
Figure 9.13 Hardware Standby Mode Timing (When CA = Low in WDT Operation)
278
Figure 9.14 Timing When Power Other Than VDD-RTC Is Off
279
Figure 9.15 Timing When VDD-RTC Power Is Off On
280
Section 10 Clock Oscillation Circuits
280
Overview
280
Features
282
Overview of CPG
282
Block Diagram of CPG
282
Figure 10.1(1) Block Diagram of CPG (SH7751)
283
Figure 10.1(2) Block Diagram of CPG (SH7751R)
285
CPG Pin Configuration
285
CPG Register Configuration
285
Table 10.1 CPG Pins
285
Table 10.2 CPG Register
286
Clock Operating Modes
286
Table 10.3(1) Clock Operating Modes (SH7751)
286
Table 10.3(2) Clock Operating Modes (SH7751R)
287
Table 10.4 FRQCR Settings and Internal Clock Frequencies
288
CPG Register Description
288
Frequency Control Register (FRQCR)
290
Changing the Frequency
290
Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 Is Off)
290
Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 Is On)
291
Changing Bus Clock Division Ratio (When PLL Circuit 2 Is On)
291
Changing Bus Clock Division Ratio (When PLL Circuit 2 Is Off)
291
Changing CPU or Peripheral Module Clock Division Ratio
292
Output Clock Control
292
Overview of Watchdog Timer
292
Block Diagram
292
Figure 10.2 Block Diagram of WDT
293
Register Configuration
293
WDT Register Descriptions
293
Watchdog Timer Counter (WTCNT)
293
Table 10.5 WDT Registers
294
Watchdog Timer Control/Status Register (WTCSR)
296
Notes On Register Access
296
Figure 10.3 Writing to WTCNT and WTCSR
297
Using the WDT
297
Standby Clearing Procedure
297
Frequency Changing Procedure
298
Using Watchdog Timer Mode
298
Using Interval Timer Mode
299
Notes On Board Design
299
Figure 10.4 Points for Attention When Using Crystal Resonator
300
Figure 10.5 Points for Attention When Using PLL Oscillator Circuit
302
Section 11 Realtime Clock (RTC)
302
Overview
302
Features
303
Block Diagram
303
Figure 11.1 Block Diagram of RTC
304
Pin Configuration
304
Register Configuration
304
Table 11.1 RTC Pins
304
Table 11.2 RTC Registers
306
Register Descriptions
306
64 Hz Counter (R64CNT)
306
Second Counter (RSECCNT)
307
Minute Counter (RMINCNT)
307
Hour Counter (RHRCNT)
308
Day-Of-Week Counter (RWKCNT)
309
Day Counter (RDAYCNT)
309
Month Counter (RMONCNT)
310
Year Counter (RYRCNT)
311
Second Alarm Register (RSECAR)
311
Minute Alarm Register (RMINAR)
312
Hour Alarm Register (RHRAR)
312
Day-Of-Week Alarm Register (RWKAR)
313
Day Alarm Register (RDAYAR)
314
Month Alarm Register (RMONAR)
314
RTC Control Register 1 (RCR1)
316
RTC Control Register 2 (RCR2)
319
RTC Control Register (RCR3) and Year-Alarm Register (RYRAR)
319
(SH7751R Only)
320
Operation
320
Time Setting Procedures
320
Figure 11.2 Examples of Time Setting Procedures
321
Time Reading Procedures
322
Figure 11.3 Examples of Time Reading Procedures
323
Alarm Function
323
Figure 11.4 Example of Use of Alarm Function
324
Interrupts
324
Usage Notes
324
Register Initialization
324
Carry Flag and Interrupt Flag in Standby Mode
324
Crystal Oscillator Circuit
324
Table 11.3 Crystal Oscillator Circuit Constants (Recommended Values)
325
Figure 11.5 Example of Crystal Oscillator Circuit Connection
326
Section 12 Timer Unit (TMU)
326
Overview
326
Features
327
Block Diagram
327
Pin Configuration
327
Figure 12.1 Block Diagram of TMU
327
Table 12.1 TMU Pins
328
Register Configuration
328
Table 12.2 TMU Registers
329
Register Descriptions
329
Timer Output Control Register (TOCR)
330
Timer Start Register (TSTR)
331
Timer Start Register 2 (TSTR2)
332
Timer Constant Registers (TCOR)
332
Timer Counters (TCNT)
333
Timer Control Registers (TCR)
336
Input Capture Register (TCPR2)
337
Operation
337
Counter Operation
338
Figure 12.2 Example of Count Operation Setting Procedure
338
Figure 12.3 TCNT Auto-Reload Operation
339
Figure 12.4 Count Timing When Operating On Internal Clock
339
Figure 12.5 Count Timing When Operating On External Clock
340
Input Capture Function
340
Figure 12.6 Count Timing When Operating On On-Chip RTC Output Clock
341
Interrupts
341
Figure 12.7 Operation Timing When Using Input Capture Function
342
Usage Notes
342
Register Writes
342
TCNT Register Reads
342
Resetting the RTC Frequency Divider
342
External Clock Frequency
342
Table 12.3 TMU Interrupt Sources
344
Section 13 Bus State Controller (BSC)
344
Overview
344
Features
346
Block Diagram
346
Figure 13.1 Block Diagram of BSC
347
Pin Configuration
347
Table 13.1 BSC Pins
349
Register Configuration
349
Table 13.2 BSC Registers
350
Overview of Areas
350
Figure 13.2 Correspondence Between Virtual Address Space and External Memory Space
351
Table 13.3 External Memory Space Map
352
Figure 13.3 External Memory Space Allocation
353
PCMCIA Support
353
Table 13.4 PCMCIA Interface Features
354
Table 13.5 PCMCIA Support Interfaces
357
Register Descriptions
357
Bus Control Register 1 (BCR1)
365
Bus Control Register 2 (BCR2)
366
Bus Control Register 3 (BCR3) (SH7751R Only)
368
Bus Control Register 4 (BCR4) (SH7751R Only)
370
Wait Control Register 1 (WCR1)
372
Table 13.6 Idle Insertion Between Accesses
373
Wait Control Register 2 (WCR2)
380
Table 13.7 When MPX Interface Is Set (Areas 0 to 6)
381
Wait Control Register 3 (WCR3)
383
Memory Control Register (MCR)
389
PCMCIA Control Register (PCR)
391
Synchronous DRAM Mode Register (SDMR)
393
Refresh Timer Control/Status Register (RTCSR)
395
Refresh Timer Counter (RTCNT)
396
Refresh Time Constant Register (RTCOR)
397
Refresh Count Register (RFCR)
397
13.2.15 Notes On Accessing Refresh Control Registers
398
Operation
398
Endian/Access Size and Data Alignment
398
Figure 13.5 Writing to RTCSR, RTCNT, RTCOR, and RFCR
399
Table 13.8 32-Bit External Device/Big-Endian Access and Data Alignment
400
Table 13.9 16-Bit External Device/Big-Endian Access and Data Alignment
401
Table 13.10 8-Bit External Device/Big-Endian Access and Data Alignment
402
Table 13.11 32-Bit External Device/Little-Endian Access and Data Alignment
403
Table 13.12 16-Bit External Device/Little-Endian Access and Data Alignment
404
Table 13.13 8-Bit External Device/Little-Endian Access and Data Alignment
405
Areas
409
SRAM Interface
410
Figure 13.6 Basic Timing of SRAM Interface
411
Figure 13.7 Example of 32-Bit Data Width SRAM Connection
412
Figure 13.8 Example of 16-Bit Data Width SRAM Connection
413
Figure 13.9 Example of 8-Bit Data Width SRAM Connection
414
Figure 13.10 SRAM Interface Wait Timing (Software Wait Only)
415
Figure 13.11 SRAM Interface Wait State Timing (Wait State Insertion By Signal)
416
Figure 13.12 SRAM Interface Wait State Timing (Read Strobe Negate Timing Setting)
417
DRAM Interface
417
Figure 13.13 Example of DRAM Connection (32-Bit Data Width, Area 3)
418
Table 13.14 Relationship Between AMXEXT and AMX2-0 Bits and Address Multiplexing
419
Figure 13.14 Basic DRAM Access Timing
420
Figure 13.15 DRAM Wait State Timing
421
Figure 13.16 DRAM Burst Access Timing
422
Figure 13.17 DRAM Bus Cycle (EDO Mode, RCD = 0, Anw = 0, TPC = 1)
423
Figure 13.18 Burst Access Timing in DRAM EDO Mode
424
Figure 13.19(1) DRAM Burst Bus Cycle, RAS Down Mode Start (Fast Page Mode, RCD = 0, Anw = 0)
425
Figure 13.19(2) DRAM Burst Bus Cycle, RAS Down Mode Continuation (Fast Page Mode, RCD = 0, Anw = 0)
426
Figure 13.19(3) DRAM Burst Bus Cycle, RAS Down Mode Start (EDO Mode, RCD = 0, Anw = 0)
427
Figure 13.19(4) DRAM Burst Bus Cycle, RAS Down Mode Continuation (EDO Mode, RCD = 0, Anw = 0)
428
Figure 13.20 Cas-Before-Ras Refresh Operation
429
Figure 13.21 DRAM Cas-Before-Ras Refresh Cycle Timing (TRAS = 0, TRC = 1)
431
Figure 13.22 DRAM Self-Refresh Cycle Timing
432
Synchronous DRAM Interface
433
Figure 13.23 Example of 32-Bit Data Width Synchronous DRAM Connection (Area 3)
434
Table 13.15 Example of Correspondence Between SH7751 Series and Synchronous DRAM
435
Figure 13.24 Basic Timing for Synchronous DRAM Burst Read
437
Figure 13.25 Basic Timing for Synchronous DRAM Single Read
438
Figure 13.26 Basic Timing for Synchronous DRAM Burst Write
440
Figure 13.27 Basic Timing for Synchronous DRAM Single Write
442
Figure 13.28 Burst Read Timing
443
Figure 13.29 Burst Read Timing (RAS Down, Same Row Address)
444
Figure 13.30 Burst Read Timing (RAS Down, Different Row Addresses)
445
Figure 13.31 Burst Write Timing
446
Figure 13.32 Burst Write Timing (Same Row Address)
447
Figure 13.33 Burst Write Timing (Different Row Addresses)
448
Table 13.16 Cycles in Which Pipelined Access Can Be Used
449
Figure 13.34 Burst Read Cycle for Different Bank and Row Address Following Preceding Burst Read Cycle
450
Figure 13.35 Auto-Refresh Operation
451
Figure 13.36 Synchronous DRAM Auto-Refresh Timing
452
Figure 13.37 Synchronous DRAM Self-Refresh Timing
454
Figure 13.38(1) Synchronous DRAM Mode Write Timing (PALL)
455
Figure 13.38(2) Synchronous DRAM Mode Write Timing (Mode Register Setting)
456
Figure 13.39 Basic Timing of a Burst Read From Synchronous DRAM (Burst Length = 8)
457
Figure 13.40 Basic Timing of a Burst Write to Synchronous DRAM
458
Burst ROM Interface
459
Figure 13.41 Burst ROM Basic Access Timing
460
Figure 13.42 Burst ROM Wait Access Timing
460
Figure 13.43 Burst ROM Wait Access Timing
461
PCMCIA Interface
463
Table 13.17 Relationship Between Address and CE When Using PCMCIA Interface
465
Figure 13.44 Example of PCMCIA Interface
466
Figure 13.45 Basic Timing for PCMCIA Memory Card Interface
467
Figure 13.46 Wait Timing for PCMCIA Memory Card Interface
468
Figure 13.47 PCMCIA Space Allocation
469
Figure 13.48 Basic Timing for PCMCIA I/O Card Interface
470
Figure 13.49 Wait Timing for PCMCIA I/O Card Interface
471
Figure 13.50 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface
472
MPX Interface
473
Figure 13.51 Example of 32-Bit Data Width MPX Connection
474
Figure 13.52 MPX Interface Timing 1 (Single Read Cycle, Anw = 0, No External Wait)
475
Figure 13.53 MPX Interface Timing 2 (Single Read, Anw = 0, One External Wait Inserted)
476
Figure 13.54 MPX Interface Timing 3 (Single Write Cycle, Anw = 0, No External Wait)
477
Figure 13.55 MPX Interface Timing 4 (Single Write, Anw = 1, One External Wait Inserted)
478
Figure 13.56 MPX Interface Timing 5 (Burst Read Cycle, Anw = 0, No External Wait)
479
Figure 13.57 MPX Interface Timing 6 (Burst Read Cycle, Anw = 0, External Wait Control)
480
Figure 13.58 MPX Interface Timing 7 (Burst Write Cycle, Anw = 0, No External Wait)
481
Figure 13.59 MPX Interface Timing 8 (Burst Write Cycle, Anw = 1, External Wait Control)
482
Figure 13.60 MPX Interface Timing 1 (Burst Read Cycle, Anw = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 64 Bits)
484
Figure 13.62 MPX Interface Timing
485
Figure 13.63 MPX Interface Timing
486
Figure 13.64 MPX Interface Timing
487
Figure 13.65 MPX Interface Timing
488
Figure 13.66 MPX Interface Timing
489
Figure 13.67 MPX Interface Timing
490
Byte Control SRAM Interface
490
Figure 13.68 Example of 52-Bit Data Width Byte Control SRAM
491
Figure 13.69 Byte Control SRAM Basic Read Cycle (No Wait)
492
Figure 13.70 Byte Control SRAM Basic Read Cycle (One Internal Wait Cycle)
493
Figure 13.71 Byte Control SRAM Basic Read Cycle
494
13.3.10 Waits Between Access Cycles
495
Figure 13.72 Waits Between Access Cycles
496
13.3.11 Bus Arbitration
498
Figure 13.73 Arbitration Sequence
499
13.3.12 Master Mode
500
13.3.13 Slave Mode
500
13.3.14 Cooperation Between Master and Slave
501
13.3.15 Notes On Usage
502
Section 14 Direct Memory Access Controller (DMAC)
502
Overview
502
Features
505
Block Diagram (SH7751)
505
Figure 14.1 Block Diagram of DMAC
506
Pin Configuration (SH7751)
506
Table 14.1 DMAC Pins
507
Register Configuration (SH7751)
507
Table 14.2 DMAC Pins in DDT Mode
507
Table 14.3 DMAC Registers
509
Register Descriptions
509
DMA Source Address Registers 0-3 (SAR0-SAR3)
510
DMA Destination Address Registers 0-3 (DAR0-DAR3)
511
DMA Transfer Count Registers 0-3 (DMATCR0-DMATCR3)
512
DMA Channel Control Registers 0-3 (CHCR0-CHCR3)
520
DMA Operation Register (DMAOR)
522
Operation
522
DMA Transfer Procedure
524
Figure 14.2 DMAC Transfer Flowchart
525
DMA Transfer Requests
526
Table 14.4 Selecting External Request Mode with RS Bits
528
Table 14.5 Selecting On-Chip Peripheral Module Request Mode with RS Bits
529
Channel Priorities
530
Figure 14.3 Round Robin Mode
531
Figure 14.4 Example of Changes in Priority Order in Round Robin Mode
532
Types of DMA Transfer
532
Table 14.6 Supported DMA Transfers
533
Figure 14.5 Data Flow in Single Address Mode
534
Figure 14.6 DMA Transfer Timing in Single Address Mode
535
Figure 14.7 Operation in Dual Address Mode
536
Figure 14.8 Example of Transfer Timing in Dual Address Mode
537
Figure 14.9 Example of DMA Transfer in Cycle Steal Mode
537
Figure 14.10 Example of DMA Transfer in Burst Mode
538
Table 14.7 Relationship Between DMA Transfer Type, Request Mode, and Bus Mode
539
Table 14.8 External Request Transfer Sources and Destinations in Normal Mode
540
Table 14.9 External Request Transfer Sources and Destinations in DDT Mode
541
Types of DMA Transfer
541
Figure 14.11 Bus Handling with Two DMAC Channels Operating
544
Figure 14.12 Dual Address Mode/Cycle Steal Mode External Bus External Bus
545
Figure 14.13 Dual Address Mode/Cycle Steal Mode External Bus External Bus
546
Figure 14.14 Dual Address Mode/Burst Mode External Bus External Bus Level Detection), DACK (Read Cycle)
547
Edge Detection), DACK (Read Cycle)
548
Figure 14.16 Dual Address Mode/Cycle Steal Mode On-Chip SCI (Level Detection External Bus
554
Figure 14.22 Single Address Mode/Burst Mode External Bus External Bus
555
Ending DMA Transfer
558
Examples of Use
558
Examples of Transfer Between External Memory and an External Device with DACK
558
Table 14.10 Conditions for Transfer Between External Memory and an External Device with DACK, and Corresponding Register Settings
559
On-Demand Data Transfer Mode (DDT Mode)
559
Operation
559
Figure 14.23 On-Demand Transfer Mode Block Diagram
561
Pins in DDT Mode
561
Figure 14.24 System Configuration in On-Demand Data Transfer Mode
562
Figure 14.25 Data Transfer Request Format
563
Table 14.11 Usable SZ, ID, and MD Combination in DDT Mode
564
Transfer Request Acceptance On Each Channel
565
Figure 14.26 Single Address Mode/Synchronous DRAM External Device Longword Transfer SDRAM Auto-Precharge Read Bus Cycle, Burst (RCD=1, CAS Latency=3, TPC=3)
566
Figure 14.27 Single Address Mode/External Device Synchronous DRAM Longword Transfer SDRAM Auto-Precharge Write Bus Cycle, Burst (RCD=1, TRWL=2, TPC=1)
567
Figure 14.28 Dual Address Mode/Synchronous DRAM SRAM Longword Transfer
568
Figure 14.29 Single Address Mode/Burst Mode/External Bus External Device 32-Byte
568
Figure 14.30 Single Address Mode/Burst Mode/External Device External Bus 32-Byte
569
Figure 14.31 Single Address Mode/Burst Mode/External Bus External Device 32-Bit Transfer/Channel 0 On-Demand Data Transfer
570
Figure 14.32 Single Address Mode/Burst Mode/External Device External Bus 32-Bit Transfer/Channel 0 On-Demand Data Transfer
571
Figure 14.33 Handshake Protocol Using Data Bus (Channel 0 On-Demand Data Transfer)
572
Figure 14.34 Handshake Protocol Without Use of Data Bus
573
Figure 14.35 Read From Synchronous DRAM Precharge Bank
573
Figure 14.36 Read From Synchronous DRAM Non-Precharge Bank (Row Miss)
574
Figure 14.37 Read From Synchronous DRAM (Row Hit)
574
Figure 14.38 Write to Synchronous DRAM Precharge Bank
575
Figure 14.39 Write to Synchronous DRAM Non-Precharge Bank (Row Miss)
575
Figure 14.40 Write to Synchronous DRAM (Row Hit)
576
Figure 14.41 Single Address Mode/Burst Mode/External Bus External Device 32-Byte Block Transfer/Channel 0 On-Demand Data Transfer
577
Figure 14.42 DDT Mode Setting
577
Figure 14.43 Single Address Mode/Burst Mode/Edge Detection/External Device
578
Figure 14.44 Single Address Mode/Burst Mode/Level Detection/ External Bus External Device Data Transfer
578
Figure 14.45 Single Address Mode/Burst Mode/Edge Detection/Byte, Word, Longword
579
Figure 14.46 Single Address Mode/Burst Mode/Edge Detection/Byte, Word, Longword, Quadword/External Device External Bus Data Transfer
580
Figure 14.47 Single Address Mode/Burst Mode/32-Byte Block Transfer/Dma Transfer Request to Channels 1-3 Using Data Bus
581
Figure 14.48 Single Address Mode/Burst Mode/32-Byte Block Transfer/ External Bus
582
Figure 14.49 Single Address Mode/Burst Mode/External Bus External Device Data Transfer/Direct Data Transfer Request to Channel 2
583
Figure 14.50 Single Address Mode/Burst Mode/External Device External Bus Data Transfer/Direct Data Transfer Request to Channel 2
586
Notes On Use of DDT Module
589
Configuration of the DMAC (SH7751R)
589
Block Diagram of the DMAC
589
Figure 14.53 Block Diagram of the DMAC
590
Pin Configuration (SH7751R)
590
Table 14.12 DMAC Pins
591
Register Configuration (SH7751R)
591
Table 14.13 DMAC Pins in DDT Mode
592
Table 14.14 Register Configuration
594
Register Descriptions (SH7751R)
594
DMA Source Address Registers 0-7 (SAR0-SAR7)
594
DMA Destination Address Registers 0-7 (DAR0-DAR7)
595
DMA Transfer Count Registers 0-7 (DMATCR0-DMATCR7)
595
DMA Channel Control Registers 0-7 (CHCR0-CHCR7)
598
DMA Operation Register (DMAOR)
599
Figure 14.54 DTR Format (Transfer Request Format) (SH7751R)
599
Table 14.15 Channel Selection By DTR Format (DMAOR.DBL = 1)
601
Operation (SH7751R)
601
Channel Specification for a Normal DMA Transfer
601
Channel Specification for Ddt-Mode DMA Transfer
601
Transfer Channel Notification in DDT Mode
602
Clearing Request Queues By DTR Format
602
Table 14.16 Notification of Transfer Channel in Eight-Channel DDT Mode
602
Table 14.17 Function of
603
Interrupt-Request Codes
603
Table 14.18 DTR Format for Clearing Request Queues
604
Figure 14.55 Single Address Mode/Burst Mode/External Bus External Device 32-Byte Block Transfer/Channel 0 On-Demand Data Transfer
604
Table 14.19 DMAC Interrupt-Request Codes
605
Figure 14.56 Single Address Mode/Cycle Steal Mode/External Bus External Device
606
Usage Notes
608
Section 15 Serial Communication Interface (SCI)
608
Overview
608
Features
610
Block Diagram
610
Figure 15.1 Block Diagram of SCI
611
Pin Configuration
611
Register Configuration
611
Table 15.1 SCI Pins
611
Table 15.2 SCI Registers
612
Register Descriptions
612
Receive Shift Register (SCRSR1)
612
Receive Data Register (SCRDR1)
613
Transmit Shift Register (SCTSR1)
613
Transmit Data Register (SCTDR1)
614
Serial Mode Register (SCSMR1)
616
Serial Control Register (SCSCR1)
620
Serial Status Register (SCSSR1)
624
Serial Port Register (SCSPTR1)
626
Figure 15.2 SCK Pin
627
Figure 15.3 Txd Pin
627
Figure 15.4 Rxd Pin
628
Bit Rate Register (SCBRR1)
630
Table 15.3 Examples of Bit Rates and SCBRR1 Settings in Asynchronous Mode
633
Table 15.4 Examples of Bit Rates and SCBRR1 Settings in Synchronous Mode
634
Table 15.5 Maximum Bit Rate for Various Frequencies with Baud Rate Generator
635
Table 15.6 Maximum Bit Rate with External Clock Input (Asynchronous Mode)
635
Table 15.7 Maximum Bit Rate with External Clock Input (Synchronous Mode)
636
Operation
636
Overview
637
Table 15.8 SCSMR1 Settings for Serial Transfer Format Selection
637
Table 15.9 SCSMR1 and SCSCR1 Settings for SCI Clock Source Selection
638
Operation in Asynchronous Mode
638
Figure 15.5 Data Format in Asynchronous Communication
639
Table 15.10 Serial Transfer Formats (Asynchronous Mode)
640
Figure 15.6 Relation Between Output Clock and Transfer Data Phase
641
Figure 15.7 Sample SCI Initialization Flowchart
642
Figure 15.8 Sample Serial Transmission Flowchart
644
Figure 15.9 Example of Transmit Operation in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit)
645
Figure 15.10 Sample Serial Reception Flowchart (1)
647
Table 15.11 Receive Error Conditions
648
Multiprocessor Communication Function
648
Figure 15.11 Example of SCI Receive Operation (Example with 8-Bit Data, Parity, One Stop Bit)
649
Figure 15.12 Example of Inter-Processor Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A)
651
Figure 15.13 Sample Multiprocessor Serial Transmission Flowchart
653
Figure 15.14 Example of SCI Transmit Operation (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
654
Figure 15.15 Sample Multiprocessor Serial Reception Flowchart (1)
656
Figure 15.16 Example of SCI Receive Operation (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
657
Operation in Synchronous Mode
657
Figure 15.17 Data Format in Synchronous Communication
659
Figure 15.18 Sample SCI Initialization Flowchart
660
Figure 15.19 Sample Serial Transmission Flowchart
661
Figure 15.20 Example of SCI Transmit Operation
662
Figure 15.21 Sample Serial Reception Flowchart (1)
664
Figure 15.22 Example of SCI Receive Operation
665
Figure 15.23 Sample Flowchart for Serial Data Transmission and Reception
666
SCI Interrupt Sources and DMAC
666
Table 15.12 SCI Interrupt Sources
667
Usage Notes
667
Table 15.13 SCSSR1 Status Flags and Transfer of Receive Data
669
Figure 15.24 Receive Data Sampling Timing in Asynchronous Mode
670
Figure 15.25 Example of Synchronous Transmission By DMAC
672
Section 16 Serial Communication Interface with FIFO (SCIF)
672
Overview
672
Features
674
Block Diagram
674
Figure 16.1 Block Diagram of SCIF
675
Pin Configuration
675
Register Configuration
675
Table 16.1 SCIF Pins
675
Table 16.2 SCIF Registers
676
Register Descriptions
676
Receive Shift Register (SCRSR2)
676
Receive FIFO Data Register (SCFRDR2)
677
Transmit Shift Register (SCTSR2)
677
Transmit FIFO Data Register (SCFTDR2)
678
Serial Mode Register (SCSMR2)
680
Serial Control Register (SCSCR2)
683
Serial Status Register (SCFSR2)
689
Bit Rate Register (SCBRR2)
690
FIFO Control Register (SCFCR2)
693
FIFO Data Count Register (SCFDR2)
694
Serial Port Register (SCSPTR2)
697
Figure 16.2 MD8/RTS2 Pin
698
Figure 16.3 MD7/CTS2 Pin
699
Figure 16.4 Md1/Txd2 Pin
699
Figure 16.5 Md2/Rxd2 Pin
700
Figure 16.6 MD0/SCK2 Pin
701
Line Status Register (SCLSR2)
702
Operation
702
Overview
702
Table 16.3 SCSMR2 Settings for Serial Transfer Format Selection
703
Serial Operation
703
Table 16.4 SCSCR2 Settings for SCIF Clock Source Selection
704
Table 16.5 Serial Transfer Formats
706
Figure 16.7 Sample SCIF Initialization Flowchart
707
Figure 16.8 Sample Serial Transmission Flowchart
709
Figure 16.9 Example of Transmit Operation (Example with 8-Bit Data, Parity, One Stop Bit)
709
Figure 16.10 Example of Operation Using Modem Control (CTS2)
710
Figure 16.11 Sample Serial Reception Flowchart (1)
711
Figure 16.11 Sample Serial Reception Flowchart (2)
713
Figure 16.12 Example of SCIF Receive Operation (Example with 8-Bit Data, Parity, One Stop Bit)
713
Figure 16.13 Example of Operation Using Modem Control (RTS2)
714
SCIF Interrupt Sources and the DMAC
714
Table 16.6 SCIF Interrupt Sources
715
Usage Notes
716
Figure 16.14 Receive Data Sampling Timing in Asynchronous Mode
718
Section 17 Smart Card Interface
718
Overview
718
Features
719
Block Diagram
719
Figure 17.1 Block Diagram of Smart Card Interface
720
Pin Configuration
720
Register Configuration
720
Table 17.1 Smart Card Interface Pins
720
Table 17.2 Smart Card Interface Registers
721
Register Descriptions
721
Smart Card Mode Register (SCSCMR1)
722
Serial Mode Register (SCSMR1)
723
Serial Control Register (SCSCR1)
724
Serial Status Register (SCSSR1)
725
Operation
725
Overview
726
Pin Connections
726
Figure 17.2 Schematic Diagram of Smart Card Interface Pin Connections
727
Data Format
727
Figure 17.3 Smart Card Interface Data Format
728
Register Settings
728
Table 17.3 Smart Card Interface Register Settings
729
Figure 17.4 TEND Generation Timing
730
Clock
730
Figure 17.5 Sample Start Character Waveforms
730
Table 17.4 Values of N and Corresponding CKS1 and CKS0 Settings
731
Table 17.5 Examples of Bit Rate B (Bits/S) for Various SCBRR1 Settings (When N = 0)
731
Table 17.6 Examples of SCBRR1 Settings for Bit Rate B (Bits/S) (When N = 0)
731
Table 17.7 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode)
732
Figure 17.6 Difference in Clock Output According to GM Bit Setting
732
Table 17.8 Register Settings and SCK Pin State
733
Data Transfer Operations
734
Figure 17.7 Sample Initialization Flowchart
736
Figure 17.8 Sample Transmission Processing Flowchart
738
Figure 17.9 Sample Reception Processing Flowchart
739
Table 17.9 Smart Card Mode Operating States and Interrupt Sources
740
Usage Notes
740
Figure 17.10 Receive Data Sampling Timing in Smart Card Mode
741
Figure 17.11 Retransfer Operation in SCI Receive Mode
742
Figure 17.12 Retransfer Operation in SCI Transmit Mode
743
Figure 17.13 Procedure for Stopping and Restarting the Clock
746
Section 18 I/O Ports
746
Overview
746
Features
747
Block Diagrams
747
Figure 18.1 16-Bit Port a
748
Figure 18.2 16-Bit Port B
749
Figure 18.3 SCK Pin
750
Figure 18.4 Txd Pin
750
Figure 18.5 Rxd Pin
751
Figure 18.6 Md1/Txd2 Pin
751
Figure 18.7 Md2/Rxd2 Pin
752
Figure 18.8 MD0/SCK2 Pin
753
Figure 18.9 MD7/CTS2 Pin
754
Pin Configuration
754
Figure 18.10 MD8/RTS2 Pin
754
Table 18.1 32-Bit General-Purpose I/O Port Pins
756
Table 18.2 SCI I/O Port Pins
756
Table 18.3 SCIF I/O Port Pins
757
Register Configuration
757
Table 18.4 I/O Port Registers
758
Register Descriptions
758
Port Control Register a (PCTRA)
759
Port Data Register a (PDTRA)
759
Port Control Register B (PCTRB)
761
Port Data Register B (PDTRB)
761
GPIO Interrupt Control Register (GPIOIC)
762
Serial Port Register (SCSPTR1)
764
Serial Port Register (SCSPTR2)
768
Section 19 Interrupt Controller (INTC)
768
Overview
768
Features
768
Block Diagram
769
Figure 19.1 Block Diagram of INTC
770
Pin Configuration
770
Register Configuration
770
Table 19.1 INTC Pins
770
Table 19.2 INTC Registers
771
Interrupt Sources
771
NMI Interrupt
772
IRL Interrupts
772
Figure 19.2 Example of IRL Interrupt Connection
773
Table 19.3 - Pins and Interrupt Levels
774
On-Chip Peripheral Module Interrupts
775
Interrupt Exception Handling and Priority
776
Table 19.4 Interrupt Exception Handling Sources and Priority Order
778
Register Descriptions
778
Interrupt Priority Registers a to D (IPRA-IPRD)
779
Interrupt Control Register (ICR)
779
Table 19.5 Interrupt Request Sources and IPRA-IPRD Registers
781
Interrupt Priority Level Settting Register 00 (INTPRI00)
782
Interrupt Factor Register 00 (INTREQ00)
782
Table 19.6 Interrupt Request Sources and INTPRI00 Register
783
Interrupt Mask Register 00 (INTMSK00)
784
Interrupt Mask Clear Register 00 (INTMSKCLR00)
785
INTREQ00, INTMSK00, and INTMSKCLR00 Bit Allocation
785
Table 19.7 Bit Allocation
786
INTC Operation
786
Interrupt Operation Sequence
787
Figure 19.3 Interrupt Operation Flowchart
788
Multiple Interrupts
788
Interrupt Masking with MAI Bit
789
Interrupt Response Time
789
Table 19.8 Interrupt Response Time
790
Section 20 User Break Controller (UBC)
790
Overview
790
Features
791
Block Diagram
791
Figure 20.1 Block Diagram of User Break Controller
792
Table 20.1 UBC Registers
793
Register Descriptions
793
Access to UBC Registers
794
Break Address Register a (BARA)
795
Break ASID Register a (BASRA)
795
Break Address Mask Register a (BAMRA)
796
Break Bus Cycle Register a (BBRA)
798
Break Address Register B (BARB)
798
Break ASID Register B (BASRB)
798
Break Address Mask Register B (BAMRB)
798
Break Data Register B (BDRB)
799
Break Data Mask Register B (BDMRB)
800
Break Bus Cycle Register B (BBRB)
800
Break Control Register (BRCR)
802
Operation
802
Explanation of Terms Relating to Accesses
803
Explanation of Terms Relating to Instruction Intervals
804
User Break Operation Sequence
805
Instruction Access Cycle Break
806
Operand Access Cycle Break
807
Condition Match Flag Setting
807
Program Counter (PC) Value Saved
808
Contiguous a and B Settings for Sequential Conditions
809
Usage Notes
810
User Break Debug Support Function
811
Figure 20.2 User Break Debug Support Function Flowchart
812
Examples of Use
814
User Break Controller Stop Function
814
Transition to User Break Controller Stopped State
814
Cancelling the User Break Controller Stopped State
815
Examples of Stopping and Restarting the User Break Controller
816
Section 21 Hitachi User Debug Interface (H-UDI)
816
Overview
816
Features
816
Block Diagram
817
Figure 21.1 Block Diagram of H-UDI Circuit
818
Pin Configuration
818
Table 21.1 H-UDI Pins
819
Register Configuration
819
Table 21.2 H-UDI Registers
820
Register Descriptions
820
Instruction Register (SDIR)
821
Data Register (SDDR)
821
Bypass Register (SDBPR)
822
Interrupt Factor Register (SDINT)
822
Boundary Scan Register (SDBSR)
823
Table 21.3 Structure of Boundary Scan Register
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