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SH7750 series
Hitachi SH7750 series Manuals
Manuals and User Guides for Hitachi SH7750 series. We have
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Hitachi SH7750 series manuals available for free PDF download: Hardware Manual, Programming Manual
Hitachi SH7750 series Hardware Manual (1037 pages)
SH7750 Series SuperH RISC engine
Brand:
Hitachi
| Category:
Engine
| Size: 5.51 MB
Table of Contents
21
Table of Contents
43
Table of Contents
51
Overview
51
SH7750 Series (SH7750, SH7750S, SH7750R) Features
53
Table 1.1 SH7750 Series Features
59
Block Diagram
59
Figure 1.1 Block Diagram of SH7750 Series Functions
60
Figure 1.2 Pin Arrangement (256-Pin BGA)
60
Pin Arrangement
61
Figure 1.3 Pin Arrangement (208-Pin QFP)
62
Figure 1.4 Pin Arrangement (264-Pin CSP)
63
Pin Functions
63
Pin Functions (256-Pin BGA)
63
Table 1.2 Pin Functions
73
Pin Functions (208-Pin QFP)
73
Table 1.3 Pin Functions
81
Pin Functions (264-Pin CSP)
81
Table 1.4 Pin Functions
91
Data Formats
91
Programming Model
92
Register Configuration
92
Privileged Mode and Banks
93
Table 2.1 Initial Register Values
94
Appendix H Power-On and Power-Off Procedures
94
Appendix Iproduct Code Lineup
94
Figure 2.2 CPU Register Configuration in Each Processor Mode
95
General Registers
96
Figure 2.3 General Registers
97
Floating-Point Registers
98
Figure 2.4 Floating-Point Registers
99
Control Registers
100
System Registers
94
Index
102
Memory-Mapped Registers
103
Data Format in Registers
103
Data Formats in Memory
103
Figure 2.1 Data Formats
103
Figure 2.5 Data Formats in Memory
104
Processor States
105
Figure 2.6 Processor State Transitions
105
Processor Modes
107
Memory Management Unit (MMU)
107
Overview
107
Features
107
Role of the MMU
109
Figure 3.1 Role of the MMU
110
Register Configuration
110
Caution
110
Table 3.1 MMU Registers
111
Figure 3.2 Mmu-Related Registers
111
Register Descriptions
114
Address Space
114
Physical Address Space
115
Figure 3.3 Physical Address Space (MMUCR.AT = 0)
116
Figure 3.4 P4 Area
117
External Memory Space
117
Figure 3.5 External Memory Space
118
Virtual Address Space
118
Figure 3.6 Virtual Address Space (MMUCR.AT = 1)
119
On-Chip RAM Space
119
Address Translation
120
Single Virtual Memory Mode and Multiple Virtual Memory Mode
120
Address Space Identifier (ASID)
121
TLB Functions
121
Unified TLB (UTLB) Configuration
121
Figure 3.7 UTLB Configuration
122
Figure 3.8 Relationship Between Page Size and Address Format
125
Instruction TLB (ITLB) Configuration
125
Address Translation Method
125
Figure 3.9 ITLB Configuration
126
Figure 3.10 Flowchart of Memory Access Using UTLB
127
Figure 3.11 Flowchart of Memory Access Using ITLB
128
MMU Functions
128
MMU Hardware Management
128
MMU Software Management
128
MMU Instruction (LDTLB)
129
Hardware ITLB Miss Handling
129
Figure 3.12 Operation of LDTLB Instruction
130
Avoiding Synonym Problems
131
MMU Exceptions
131
Instruction TLB Multiple Hit Exception
132
Instruction TLB Miss Exception
133
Instruction TLB Protection Violation Exception
134
Data TLB Multiple Hit Exception
134
Data TLB Miss Exception
135
Data TLB Protection Violation Exception
136
Initial Page Write Exception
137
Memory-Mapped TLB Configuration
138
ITLB Address Array
138
Figure 3.13 Memory-Mapped ITLB Address Array
139
ITLB Data Array 1
139
Figure 3.14 Memory-Mapped ITLB Data Array 1
140
ITLB Data Array 2
140
UTLB Address Array
140
Figure 3.15 Memory-Mapped ITLB Data Array 2
141
Figure 3.16 Memory-Mapped UTLB Address Array
142
UTLB Data Array 1
142
Figure 3.17 Memory-Mapped UTLB Data Array 1
143
UTLB Data Array 2
143
Figure 3.18 Memory-Mapped UTLB Data Array 2
145
Caches
145
Overview
145
Features
145
Table 4.1 Cache Features (SH7750, SH7750S)
145
Table 4.2 Cache Features (SH7750R)
146
Register Configuration
146
Table 4.3 Features of Store Queues
146
Table 4.4 Cache Control Registers
147
Figure 4.1 Cache and Store Queue Control Registers
147
Register Descriptions
149
Operand Cache (OC)
149
Configuration
150
Figure 4.2 Configuration of Operand Cache(Sh7750, SH7750S)
151
Figure 4.3 Configuration of Operand Cache (SH7750R)
153
Read Operation
154
Write Operation
155
Write-Back Buffer
155
Write-Through Buffer
155
Figure 4.4 Configuration of Write-Back Buffer
155
Figure 4.5 Configuration of Write-Through Buffer
156
RAM Mode
157
OC Index Mode
157
Coherency Between Cache and External Memory
158
Instruction Cache (IC)
158
Configuration
159
Figure 4.6 Configuration of Instruction Cache (SH7750, SH7750S)
160
Figure 4.7 Configuration of Instruction Cache (SH7750R)
161
Read Operation
161
IC Index Mode
162
Memory-Mapped Cache Configuration (SH7750, SH7750S)
162
IC Address Array
163
IC Data Array
163
Figure 4.8 Memory-Mapped IC Address Array
164
OC Address Array
164
Figure 4.9 Memory-Mapped IC Data Array
165
OC Data Array
165
Figure 4.10 Memory-Mapped OC Address Array
166
Figure 4.11 Memory-Mapped OC Data Array
167
IC Address Array
168
IC Data Array
168
Figure 4.12 Memory-Mapped IC Address Array
169
OC Address Array
169
Figure 4.13 Memory-Mapped IC Data Array
170
OC Data Array
170
Figure 4.14 Memory-Mapped OC Address Array
171
Summary of the Memory-Mapping of the OC
171
Figure 4.15 Memory-Mapped OC Data Array
166
Memory-Mapped Cache Configuration (SH7750R)
172
Store Queues
172
SQ Configuration
172
SQ Writes
172
Transfer to External Memory
172
Figure 4.16 Store Queue Configuration
174
SQ Protection
174
Reading the Sqs (SH7750R Only)
175
SQ Usage Notes
177
Exceptions
177
Overview
177
Features
177
Register Configuration
177
Table 5.1 Exception-Related Registers
178
Figure 5.1 Register Bit Configurations
178
Register Descriptions
179
Exception Handling Functions
179
Exception Handling Flow
179
Exception Handling Vector Addresses
180
Exception Types and Priorities
180
Figure 21.3 H-UDI Reset
180
Table 5.2 Exceptions
182
Exception Flow
183
Exception Source Acceptance
183
Figure 5.2 Instruction Execution and Exception Handling
184
Figure 5.3 Example of General Exception Acceptance Order
185
Exception Requests and BL Bit
185
Return From Exception Handling
185
Description of Exceptions
186
Resets
187
Table 5.3 Types of Reset
191
General Exceptions
205
Interrupts
208
Priority Order with Multiple Exceptions
209
Usage Notes
210
Restrictions
211
Data Formats
211
Floating-Point Format
211
Figure 6.1 Format of Single-Precision Floating-Point Number
212
Figure 6.2 Format of Double-Precision Floating-Point Number
212
Table 6.1 Floating-Point Number Formats and Parameters
213
Non-Numbers (Nan)
213
Table 6.2 Floating-Point Ranges
214
Denormalized Numbers
214
Figure 6.3 Single-Precision Nan Bit Pattern
211
Floating-Point Unit
211
Overview
215
Registers
215
Floating-Point Registers
216
Figure 6.4 Floating-Point Registers
217
Floating-Point Status/Control Register (FPSCR)
218
Floating-Point Communication Register (FPUL)
218
Rounding
219
Floating-Point Exceptions
220
Graphics Support Functions
220
Geometric Operation Instructions
222
Pair Single-Precision Data Transfer
223
Execution Environment
223
Instruction Set
225
Addressing Modes
228
Table 7.1 Addressing Modes and Effective Addresses
229
Instruction Set
229
Table 7.2 Notation Used in Instruction List
230
Table 7.3 Fixed-Point Transfer Instructions
233
Table 7.4 Arithmetic Operation Instructions
234
Table 7.5 Logic Operation Instructions
235
Table 7.6 Shift Instructions
236
Table 7.7 Branch Instructions
237
Table 7.8 System Control Instructions
239
Table 7.9 Floating-Point Single-Precision Instructions
240
Table 7.10 Floating-Point Double-Precision Instructions
240
Table 7.11 Floating-Point Control Instructions
241
Table 7.12 Floating-Point Graphics Acceleration Instructions
243
Pipelines
243
Pipelining
244
Figure 8.1 Basic Pipelines
249
Figure 8.2 Instruction Execution Patterns
250
Parallel-Executability
250
Table 8.1 Instruction Groups
254
Execution Cycles and Pipeline Stalling
254
Table 8.2 Parallel-Executability
259
Figure 8.3 Examples of Pipelined Execution
261
Table 8.3 Execution Cycles
271
Overview
271
Types of Power-Down Modes
272
Table 9.1 Status of CPU and Peripheral Modules in Power-Down Modes
273
Register Configuration
273
Pin Configuration
273
Table 9.2 Power-Down Mode Registers
273
Table 9.3 Power-Down Mode Pins
271
Power-Down Modes
274
Register Descriptions
274
Standby Control Register (STBCR)
276
Peripheral Module Pin High Impedance Control
276
Peripheral Module Pin Pull-Up Control
277
Standby Control Register 2 (STBCR2)
278
Clock-Stop Register 00 (CLKSTP00) (SH7750R Only)
279
Clock-Stop Clear Register 00 (CLKSTPCLR00) (SH7750R Only)
280
Deep Sleep Mode
280
Transition to Deep Sleep Mode
281
Exit From Deep Sleep Mode
280
Sleep Mode
280
Transition to Sleep Mode
280
Exit From Sleep Mode
281
Standby Mode
281
Transition to Standby Mode
281
Table 9.4 State of Registers in Standby Mode
282
Exit From Standby Mode
282
Clock Pause Function
283
Module Standby Function
283
Transition to Module Standby Function
284
Exit From Module Standby Function
285
Hardware Standby Mode (SH7750S, SH7750R Only)
285
Transition to Hardware Standby Mode
285
Exit From Hardware Standby Mode
285
Usage Notes
286
STATUS Pin Change Timing
287
In Reset
287
Figure 9.1 STATUS Output in Power-On Reset
287
Figure 9.2 STATUS Output in Manual Reset
288
In Exit From Standby Mode
288
Figure 9.3 STATUS Output in Standby → Interrupt Sequence
288
Figure 9.4 STATUS Output in Standby → Power-On Reset Sequence
289
Figure 9.5 STATUS Output in Standby → Manual Reset Sequence
290
In Exit From Sleep Mode
290
Figure 9.6 STATUS Output in Sleep → Interrupt Sequence
290
Figure 9.7 STATUS Output in Sleep → Power-On Reset Sequence
291
Figure 9.8 STATUS Output in Sleep → Manual Reset Sequence
292
In Exit From Deep Sleep Mode
292
Figure 9.9 STATUS Output in Deep Sleep → Interrupt Sequence
292
Figure 9.10 STATUS Output in Deep Sleep → Power-On Reset Sequence
293
Figure 9.11 STATUS Output in Deep Sleep → Manual Reset Sequence
294
Hardware Standby Mode Timing (SH7750S, SH7750R Only)
294
Figure 9.12 Hardware Standby Mode Timing (When CA = Low in Normal Operation)
295
Figure 9.13 Hardware Standby Mode Timing (When CA = Low in WDT Operation)
296
Figure 9.14 Timing When Power Other Than VDD-RTC Is Off
296
Figure 9.15 Timing When VDD-RTC Power Is Off → On
297
Overview
297
Features
297
Section 10 Clock Oscillation Circuits
299
Overview of CPG
299
Block Diagram of CPG
299
Figure 10.1 (1) Block Diagram of CPG (SH7750, SH7750S)
300
Figure 10.1 (2) Block Diagram of CPG (SH7750R)
302
CPG Pin Configuration
302
CPG Register Configuration
302
Table 10.1 CPG Pins
302
Table 10.2 CPG Register
303
Clock Operating Modes
303
Table 10.3 (1) Clock Operating Modes (SH7750, SH7750S)
303
Table 10.3 (2) Clock Operating Modes (SH7750R)
304
CPG Register Description
304
Frequency Control Register (FRQCR)
304
Table 10.4 FRQCR Settings and Internal Clock Frequencies
307
Changing the Frequency
307
Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 Is Off)
307
Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 Is On)
308
Changing Bus Clock Division Ratio (When PLL Circuit 2 Is On)
308
Changing Bus Clock Division Ratio (When PLL Circuit 2 Is Off)
308
Changing CPU or Peripheral Module Clock Division Ratio
308
Output Clock Control
309
Overview of Watchdog Timer
309
Block Diagram
309
Figure 10.2 Block Diagram of WDT
310
Register Configuration
310
WDT Register Descriptions
310
Watchdog Timer Counter (WTCNT)
310
Table 10.5 WDT Registers
311
Watchdog Timer Control/Status Register (WTCSR)
313
Notes On Register Access
313
Using the WDT
313
Standby Clearing Procedure
313
Figure 10.3 Writing to WTCNT and WTCSR
314
Frequency Changing Procedure
314
Using Watchdog Timer Mode
315
Using Interval Timer Mode
315
Figure 10.4 Points for Attention When Using Crystal Resonator
315
Notes On Board Design
316
Figure 10.5 Points for Attention When Using PLL Oscillator Circuit
317
Overview
317
Features
318
Block Diagram
318
Figure 11.1 Block Diagram of RTC
319
Pin Configuration
319
Register Configuration
319
Table 11.1 RTC Pins
319
Table 11.2 RTC Registers
317
Section 11 Realtime Clock (RTC)
321
Register Descriptions
321
64 Hz Counter (R64CNT)
321
Second Counter (RSECCNT)
322
Minute Counter (RMINCNT)
322
Hour Counter (RHRCNT)
323
Day-Of-Week Counter (RWKCNT)
324
Day Counter (RDAYCNT)
324
Month Counter (RMONCNT)
325
Year Counter (RYRCNT)
326
Second Alarm Register (RSECAR)
326
Minute Alarm Register (RMINAR)
327
Hour Alarm Register (RHRAR)
327
Day-Of-Week Alarm Register (RWKAR)
328
Day Alarm Register (RDAYAR)
329
Month Alarm Register (RMONAR)
329
RTC Control Register 1 (RCR1)
331
RTC Control Register 2 (RCR2)
333
RTC Control Register 3 (RCR3) and Year-Alarm Register (RYRAR)
333
(SH7750R Only)
335
Operation
335
Time Setting Procedures
335
Figure 11.2 Examples of Time Setting Procedures
336
Time Reading Procedures
337
Figure 11.3 Examples of Time Reading Procedures
338
Alarm Function
338
Figure 11.4 Example of Use of Alarm Function
339
Interrupts
339
Usage Notes
339
Register Initialization
339
Carry Flag and Interrupt Flag in Standby Mode
339
Crystal Oscillator Circuit
339
Table 11.3 Crystal Oscillator Circuit Constants (Recommended Values)
340
Figure 11.5 Example of Crystal Oscillator Circuit Connection
341
Overview
341
Features
342
Block Diagram
342
Pin Configuration
342
Figure 12.1 Block Diagram of TMU
342
Table 12.1 TMU Pins
343
Register Configuration
343
Table 12.2 TMU Registers
341
Section 12 Timer Unit (TMU)
345
Register Descriptions
345
Timer Output Control Register (TOCR)
346
Timer Start Register (TSTR)
347
Timer Start Register 2 (TSTR2) (SH7750R Only)
348
Timer Constant Registers (TCOR)
348
Timer Counters (TCNT)
349
Timer Control Registers (TCR)
353
Input Capture Register (TCPR2)
354
Operation
354
Counter Operation
355
Figure 12.2 Example of Count Operation Setting Procedure
355
Figure 12.3 TCNT Auto-Reload Operation
356
Figure 12.4 Count Timing When Operating On Internal Clock
356
Figure 12.5 Count Timing When Operating On External Clock
357
Input Capture Function
357
Figure 12.6 Count Timing When Operating On On-Chip RTC Output Clock
358
Figure 12.7 Operation Timing When Using Input Capture Function
358
Interrupts
359
Usage Notes
359
Register Writes
359
TCNT Register Reads
359
Resetting the RTC Frequency Divider
359
External Clock Frequency
359
Table 12.3 TMU Interrupt Sources
361
Overview
361
Features
363
Block Diagram
363
Figure 13.1 Block Diagram of BSC
364
Pin Configuration
364
Table 13.1 BSC Pins
368
Register Configuration
368
Table 13.2 BSC Registers
369
Overview of Areas
369
Figure 13.2 Correspondence Between Virtual Address Space and External Memory Space
370
Table 13.3 External Memory Space Map
371
Figure 13.3 External Memory Space Allocation
372
PCMCIA Support
372
Table 13.4 PCMCIA Interface Features
373
Table 13.5 PCMCIA Support Interfaces
361
Section 13 Bus State Controller (BSC)
376
Register Descriptions
376
Bus Control Register 1 (BCR1)
385
Bus Control Register 2 (BCR2)
387
Bus Control Register 3 (BCR3) (SH7750R Only)
388
Bus Control Register 4 (BCR4) (SH7750R Only)
388
Figure 13.4 Example of RDY Sampling Timing at Which BCR4 Is Set (Two Wait Cycles Are Inserted By WCR2)
390
Wait Control Register 1 (WCR1)
393
Wait Control Register 2 (WCR2)
400
Table 13.6 MPX Interface Is Selected (Areas 0 to 6)
401
Wait Control Register 3 (WCR3)
402
Memory Control Register (MCR)
409
PCMCIA Control Register (PCR)
412
Synchronous DRAM Mode Register (SDMR)
414
Refresh Timer Control/Status Register (RTCSR)
417
Refresh Timer Counter (RTCNT)
418
Refresh Time Constant Register (RTCOR)
419
Refresh Count Register (RFCR)
419
13.2.15 Notes On Accessing Refresh Control Registers
420
Operation
420
Endian/Access Size and Data Alignment
420
Figure 13.5 Writing to RTCSR, RTCNT, RTCOR, and RFCR
422
Table 13.7 (1) 64-Bit External Device/Big-Endian Access and Data Alignment
423
Table 13.7 (2) 64-Bit External Device/Big-Endian Access and Data Alignment
424
Table 13.8 32-Bit External Device/Big-Endian Access and Data Alignment
425
Table 13.9 16-Bit External Device/Big-Endian Access and Data Alignment
426
Table 13.10 8-Bit External Device/Big-Endian Access and Data Alignment
427
Table 13.11 (1) 64-Bit External Device/Little-Endian Access and Data Alignment
428
Table 13.11 (2) 64-Bit External Device/Little-Endian Access and Data Alignment
429
Table 13.12 32-Bit External Device/Little-Endian Access and Data Alignment
430
Table 13.13 16-Bit External Device/Little-Endian Access and Data Alignment
431
Table 13.14 8-Bit External Device/Little-Endian Access and Data Alignment
432
Areas
437
SRAM Interface
438
Figure 13.6 Basic Timing of SRAM Interface
439
Figure 13.7 Example of 64-Bit Data Width SRAM Connection
440
Figure 13.8 Example of 32-Bit Data Width SRAM Connection
441
Figure 13.9 Example of 16-Bit Data Width SRAM Connection
442
Figure 13.10 Example of 8-Bit Data Width SRAM Connection
443
Figure 13.11 SRAM Interface Wait Timing (Software Wait Only)
444
Figure 13.12 SRAM Interface Wait State Timing (Wait State Insertion By RDY Signal)
445
DRAM Interface
446
Figure 13.13 SRAM Interface Read-Strobe Negate Timing (Ans = 1, Anw = 4, Anh = 2) 395 Figure 13.14 Example of DRAM Connection (64-Bit Data Width, Area 3)
447
Figure 13.15 Example of DRAM Connection (32-Bit Data Width, Area 3)
448
Figure 13.16 Example of DRAM Connection (16-Bit Data Width, Areas 2 and 3)
449
Table 13.15 Relationship Between AMXEXT and AMX2-0 Bits and
450
Figure 13.17 Basic DRAM Access Timing
451
Figure 13.18 DRAM Wait State Timing
452
Figure 13.19 DRAM Burst Access Timing
453
Figure 13.20 DRAM Bus Cycle (EDO Mode, RCD = 0, Anw = 0, TPC = 1)
454
Figure 13.21 Burst Access Timing in DRAM EDO Mode
455
Figure 13.22 (1) DRAM Burst Bus Cycle, RAS Down Mode Start (Fast Page Mode, RCD = 0, Anw = 0)
456
Figure 13.22 (2) DRAM Burst Bus Cycle, RAS Down Mode Continuation (Fast Page Mode, RCD = 0, Anw = 0)
457
Figure 13.22 (3) DRAM Burst Bus Cycle, RAS Down Mode Start (EDO Mode, RCD = 0, Anw = 0)
458
Figure 13.22 (4) DRAM Burst Bus Cycle, RAS Down Mode Continuation (EDO Mode, RCD = 0, Anw = 0)
459
Figure 13.23 Cas-Before-Ras Refresh Operation
460
Figure 13.24 DRAM Cas-Before-Ras Refresh Cycle Timing (TRAS = 0, TRC = 1)
462
Figure 13.25 DRAM Self-Refresh Cycle Timing
463
Synchronous DRAM Interface
466
Table 13.16 Example of Correspondence Between SH7750 Series and Synchronous DRAM
466
Address Pins (64-Bit Bus Width, AMX2-AMX0 = 011, AMXEXT = 0)
481
Table 13.17 Cycles for Which Pipeline Access Is Possible
491
Burst ROM Interface
494
PCMCIA Interface
496
Table 13.18 Relationship Between Address and CE When Using PCMCIA Interface
505
MPX Interface
523
Byte Control SRAM Interface
528
13.3.10 Waits Between Access Cycles
530
13.3.11 Bus Arbitration
533
13.3.12 Master Mode
534
13.3.13 Slave Mode
535
13.3.14 Partial-Sharing Master Mode
536
13.3.15 Cooperation Between Master and Slave
537
13.3.16 Notes On Usage
539
Overview
539
Features
542
Block Diagram (SH7750, SH7750S)
543
Pin Configuration (SH7750, SH7750S)
543
Table 14.1 DMAC Pins
544
Register Configuration (SH7750, SH7750S)
544
Table 14.2 DMAC Pins in DDT Mode
544
Table 14.3 DMAC Registers
539
Section 14 Direct Memory Access Controller (DMAC)
546
Register Descriptions (SH7750, SH7750S)
546
DMA Source Address Registers 0-3 (SAR0-SAR3)
547
DMA Destination Address Registers 0-3 (DAR0-DAR3)
548
DMA Transfer Count Registers 0-3 (DMATCR0-DMATCR3)
549
DMA Channel Control Registers 0-3 (CHCR0-CHCR3)
557
DMA Operation Register (DMAOR)
560
Operation
560
DMA Transfer Procedure
562
DMA Transfer Requests
563
Table 14.4 Selecting External Request Mode with RS Bits
564
Table 14.5 Selecting On-Chip Peripheral Module Request Mode with RS Bits
565
Channel Priorities
568
Types of DMA Transfer
568
Table 14.6 Supported DMA Transfers
574
Table 14.7 Relationship Between DMA Transfer Type, Request Mode, and Bus Mode
575
Table 14.8 External Request Transfer Sources and Destinations in Normal Mode
576
Table 14.9 External Request Transfer Sources and Destinations in DDT Mode
577
Number of Bus Cycle States and DREQ Pin Sampling Timing
591
Ending DMA Transfer
594
Examples of Use
594
Examples of Transfer Between External Memory and an External Device with DACK
594
Table 14.10 Conditions for Transfer Between External Memory and an External Device with DACK, and Corresponding Register Settings
595
On-Demand Data Transfer Mode (DDT Mode)
595
Operation
597
Pins in DDT Mode
600
Transfer Request Acceptance On Each Channel
621
Notes On Use of DDT Module
624
Configuration of the DMAC (SH7750R)
624
Block Diagram of the DMAC
625
Pin Configuration (SH7750R)
625
Table 14.11 DMAC Pins
626
Register Configuration (SH7750R)
626
Table 14.12 DMAC Pins in DDT Mode
627
Table 14.13 Register Configuration
629
Register Descriptions (SH7750R)
629
DMA Source Address Registers 0-7 (SAR0-SAR7)
629
DMA Destination Address Registers 0-7 (DAR0-DAR7)
630
DMA Transfer Count Registers 0-7 (DMATCR0-DMATCR7)
630
DMA Channel Control Registers 0-7 (CHCR0-CHCR7)
633
DMA Operation Register (DMAOR)
634
Table 14.14 Channel Selection By DTR Format (DMAOR.DBL = 1)
636
Operation (SH7750R)
636
Channel Specification for a Normal DMA Transfer
636
Channel Specification for Ddt-Mode DMA Transfer
636
Transfer Channel Notification in DDT Mode
637
Clearing Request Queues By DTR Format
637
Table 14.15 Notification of Transfer Channel in Eight-Channel DDT Mode
637
Table 14.16 Function of BAVL
638
Interrupt-Request Codes
638
Table 14.17 DTR Format for Clearing Request Queues
639
Table 14.18 DMAC Interrupt-Request Codes
641
Usage Notes
643
Overview
643
Features
645
Block Diagram
646
Pin Configuration
646
Register Configuration
646
Table 15.1 SCI Pins
646
Table 15.2 SCI Registers
643
Section 15 Serial Communication Interface (SCI)
647
Register Descriptions
647
Receive Shift Register (SCRSR1)
647
Receive Data Register (SCRDR1)
648
Transmit Shift Register (SCTSR1)
648
Transmit Data Register (SCTDR1)
649
Serial Mode Register (SCSMR1)
651
Serial Control Register (SCSCR1)
655
Serial Status Register (SCSSR1)
659
Serial Port Register (SCSPTR1)
663
Bit Rate Register (SCBRR1)
665
Table 15.3 Examples of Bit Rates and SCBRR1 Settings in Asynchronous Mode
668
Table 15.4 Examples of Bit Rates and SCBRR1 Settings in Synchronous Mode
669
Table 15.5 Maximum Bit Rate for Various Frequencies with Baud Rate Generator (Asynchronous Mode)
670
Table 15.6 Maximum Bit Rate with External Clock Input (Asynchronous Mode)
670
Table 15.7 Maximum Bit Rate with External Clock Input (Synchronous Mode)
671
Operation
671
Overview
672
Table 15.8 SCSMR1 Settings for Serial Transfer Format Selection
672
Table 15.9 SCSMR1 and SCSCR1 Settings for SCI Clock Source Selection
673
Operation in Asynchronous Mode
674
Table 15.10 Serial Transfer Formats (Asynchronous Mode)
682
Table 15.11 Receive Error Conditions
684
Multiprocessor Communication Function
692
Operation in Synchronous Mode
701
SCI Interrupt Sources and DMAC
701
Table 15.12 SCI Interrupt Sources
702
Table 15.13 SCSSR1 Status Flags and Transfer of Receive Data
702
Usage Notes
707
Overview
707
Features
709
Block Diagram
710
Pin Configuration
710
Table 16.1 SCIF Pins
711
Register Configuration
707
Section 16 Serial Communication Interface with FIFO (SCIF)
711
Register Descriptions
711
Receive Shift Register (SCRSR2)
711
Table 16.2 SCIF Registers
712
Receive FIFO Data Register (SCFRDR2)
712
Transmit Shift Register (SCTSR2)
713
Transmit FIFO Data Register (SCFTDR2)
713
Serial Mode Register (SCSMR2)
715
Serial Control Register (SCSCR2)
718
Serial Status Register (SCFSR2)
724
Bit Rate Register (SCBRR2)
725
FIFO Control Register (SCFCR2)
728
FIFO Data Count Register (SCFDR2)
729
Serial Port Register (SCSPTR2)
734
Line Status Register (SCLSR2)
735
Operation
735
Overview
735
Table 16.3 SCSMR2 Settings for Serial Transfer Format Selection
736
Serial Operation
736
Table 16.4 SCSCR2 Settings for SCIF Clock Source Selection
737
Table 16.5 Serial Transmit/Receive Formats
747
SCIF Interrupt Sources and the DMAC
747
Table 16.6 SCIF Interrupt Sources
748
Usage Notes
753
Overview
753
Features
754
Block Diagram
755
Pin Configuration
755
Register Configuration
755
Table 17.1 Smart Card Interface Pins
755
Table 17.2 Smart Card Interface Registers
753
Section 17 Smart Card Interface
756
Register Descriptions
756
Smart Card Mode Register (SCSCMR1)
757
Serial Mode Register (SCSMR1)
758
Serial Control Register (SCSCR1)
759
Serial Status Register (SCSSR1)
760
Operation
760
Overview
761
Pin Connections
762
Data Format
763
Register Settings
763
Table 17.3 Smart Card Interface Register Settings
765
Clock
765
Table 17.4 Values of N and Corresponding CKS1 and CKS0 Settings
766
Table 17.5 Examples of Bit Rate B (Bits/S) for Various SCBRR1 Settings (When N = 0)
766
Table 17.6 Examples of SCBRR1 Settings for Bit Rate B (Bits/S) (When N = 0)
766
Table 17.7 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode)
767
Table 17.8 Register Settings and SCK Pin State
768
Data Transmit/Receive Operations
774
Table 17.9 Smart Card Mode Operating States and Interrupt Sources
775
Usage Notes
781
Overview
781
Features
782
Block Diagrams
789
Pin Configuration
789
Table 18.1 20-Bit General-Purpose I/O Port Pins
790
Table 18.2 SCI I/O Port Pins
790
Table 18.3 SCIF I/O Port Pins
791
Register Configuration
791
Table 18.4 I/O Port Registers
781
Section 18 I/O Ports
792
Register Descriptions
792
Port Control Register a (PCTRA)
793
Port Data Register a (PDTRA)
794
Port Control Register B (PCTRB)
795
Port Data Register B (PDTRB)
795
GPIO Interrupt Control Register (GPIOIC)
796
Serial Port Register (SCSPTR1)
798
Serial Port Register (SCSPTR2)
801
Overview
801
Features
801
Block Diagram
803
Pin Configuration
803
Register Configuration
803
Table 19.1 INTC Pins
803
Table 19.2 INTC Registers
801
Section 19 Interrupt Controller (INTC)
804
Interrupt Sources
804
NMI Interrupt
805
IRL Interrupts
806
Table 19.3 IRL3-IRL0 Pins and Interrupt Levels
807
On-Chip Peripheral Module Interrupts
807
Table 19.4 SH7750 IRL3-IRL0 Pins and Interrupt Levels (When IRLM = 1)
808
Interrupt Exception Handling and Priority
809
Table 19.5 Interrupt Exception Handling Sources and Priority Order
811
Register Descriptions
811
Interrupt Priority Registers a to D (IPRA-IPRD)
812
Interrupt Control Register (ICR)
812
Table 19.6 Interrupt Request Sources and IPRA-IPRD Registers
814
Interrupt-Priority-Level Setting Register 00 (INTPRI00) (SH7750R Only)
815
Interrupt Source Register 00 (INTREQ00) (SH7750R Only)
815
Table 19.7 Interrupt Request Sources and the Bits of the INTPRI00 Register
816
Interrupt Mask Register 00 (INTMSK00) (SH7750R Only)
817
Interrupt Mask Clear Register 00 (INTMSKCLR00) (SH7750R Only)
817
Bit Assignments of INTREQ00, INTMSK00, and INTMSKCLR00 (SH7750R Only)
817
Table 19.8 Bit Assignments
818
INTC Operation
818
Interrupt Operation Sequence
820
Multiple Interrupts
820
Interrupt Masking with MAI Bit
821
Interrupt Response Time
821
Table 19.9 Interrupt Response Time
823
Overview
823
Features
824
Block Diagram
825
Table 20.1 UBC Registers
823
Section 20 User Break Controller (UBC)
826
Register Descriptions
826
Access to UBC Control Registers
827
Break Address Register a (BARA)
828
Break ASID Register a (BASRA)
828
Break Address Mask Register a (BAMRA)
829
Break Bus Cycle Register a (BBRA)
831
Break Address Register B (BARB)
831
Break ASID Register B (BASRB)
831
Break Address Mask Register B (BAMRB)
831
Break Data Register B (BDRB)
832
Break Data Mask Register B (BDMRB)
833
Break Bus Cycle Register B (BBRB)
833
Break Control Register (BRCR)
835
Operation
835
Explanation of Terms Relating to Accesses
836
Explanation of Terms Relating to Instruction Intervals
837
User Break Operation Sequence
838
Instruction Access Cycle Break
839
Operand Access Cycle Break
840
Condition Match Flag Setting
840
Program Counter (PC) Value Saved
841
Contiguous a and B Settings for Sequential Conditions
842
Usage Notes
843
User Break Debug Support Function
845
Examples of Use
847
User Break Controller Stop Function
847
Transition to User Break Controller Stopped State
847
Cancelling the User Break Controller Stopped State
848
Examples of Stopping and Restarting the User Break Controller
849
Overview
849
Features
849
Block Diagram
851
Pin Configuration
851
Table 21.1 H-UDI Pins
852
Register Configuration
852
Table 21.2 H-UDI Registers
849
Section 21 Hitachi User Debug Interface (H-UDI)
853
Register Descriptions
853
Instruction Register (SDIR)
855
Data Register (SDDR)
855
Bypass Register (SDBPR)
856
Interrupt Source Register (SDINT) (SH7750R Only)
856
Boundary Scan Register (SDBSR) (SH7750R Only)
857
Table 21.3 Configuration of the Boundary Scan Register (1)
858
Table 21.3 Configuration of the Boundary Scan Register (2)
859
Table 21.3 Configuration of the Boundary Scan Register (3)
860
Operation
860
TAP Control
861
H-UDI Reset
861
H-UDI Interrupt
862
Boundary Scan (EXTEST, SAMPLE/PRELOAD, BYPASS) (SH7750R Only)
862
Usage Notes
863
Absolute Maximum Ratings
863
Section 22 Electrical Characteristics
863
Table 22.1 Absolute Maximum Ratings
864
DC Characteristics
864
Table 22.2 DC Characteristics (HD6417750RBP240)
866
Table 22.3 DC Characteristics (HD6417750RF240)
868
Table 22.4 DC Characteristics (HD6417750RBP200)
870
Table 22.5 DC Characteristics (HD6417750RF200)
872
Table 22.6 DC Characteristics (HD6417750SBP200)
874
Table 22.7 DC Characteristics (HD6417750SF200)
876
Table 22.8 DC Characteristics (HD6417750BP200M)
878
Table 22.9 DC Characteristics (HD6417750SF167)
880
Table 22.10 DC Characteristics (HD6417750SF167I)
882
Table 22.11 DC Characteristics (HD6417750F167)
884
Table 22.12 DC Characteristics (HD6417750F167I)
886
Table 22.13 DC Characteristics (HD6417750SVF133)
888
Table 22.14 DC Characteristics (HD6417750SVBT133)
890
Table 22.15 DC Characteristics (HD6417750VF128)
891
Table 22.16 Permissible Output Currents
892
AC Characteristics
892
Table 22.17 Clock Timing (HD6417750RBP240)
892
Table 22.18 Clock Timing (HD6417750RF240)
892
Table 22.19 Clock Timing (HD6417750BP200M, HD6417750SBP200, HD6417750RBP200)
892
Table 22.20 Clock Timing (HD6417750RF200)
892
Table 22.21 Clock Timing (HD6417750SF200)
893
Table 22.22 Clock Timing (HD6417750F167, HD6417750F167I, HD6417750SF167, HD6417750SF167I)
893
Table 22.23 Clock Timing (HD6417750SVF133, HD6417750SVBT133)
893
Table 22.24 Clock Timing (HD6417750VF128)
894
Clock and Control Signal Timing
894
Table 22.25 Clock and Control Signal Timing (HD6417750RBP240)
896
Table 22.26 Clock and Control Signal Timing (HD6417750RF240)
898
Table 22.27 Clock and Control Signal Timing (HD6417750RBP200)
900
Table 22.28 Clock and Control Signal Timing (HD6417750RF200)
902
Table 22.29 Clock and Control Signal Timing
904
Table 22.30 Clock and Control Signal Timing (HD6417750SF200)
906
Table 22.31 Clock and Control Signal Timing
906
Hd6417750Sf167, Hd6417750Sf167I)
908
Hd6417750Svbt133: V
910
Table 22.33 Clock and Control Signal Timing (HD6417750VF128)
912
Figure 22.1 EXTAL Clock Input Timing
912
Figure 22.2(1) CKIO Clock Output Timing
912
Figure 22.2(2) CKIO Clock Output Timing
913
Figure 22.3 Power-On Oscillation Settling Time
913
Figure 22.4 Standby Return Oscillation Settling Time (Return By RESET)
914
Figure 22.5 Power-On Oscillation Settling Time
914
Figure 22.6 Standby Return Oscillation Settling Time (Return By RESET)
915
Figure 22.7 Standby Return Oscillation Settling Time (Return By NMI)
915
Figure 22.8 Standby Return Oscillation Settling Time (Return By IRL3-IRL0)
916
Figure 22.10 PLL Synchronization Settling Time in Case of IRL Interrupt
916
Figure 22.9 PLL Synchronization Settling Time in Case of RESET or NMI Interrupt
917
Figure 22.11 Manual Reset Input Timing
917
Figure 22.12 Mode Input Timing
918
Control Signal Timing
918
Table 22.34 Control Signal Timing (1)
919
Table 22.34 Control Signal Timing (2)
920
Figure 22.13 Control Signal Timing
920
Figure 22.14 Pin Drive Timing for Standby Mode
921
Bus Timing
921
Table 22.35 Bus Timing (1)
923
Table 22.35 Bus Timing (2)
925
Table 22.35 Bus Timing (3)
927
Figure 22.15 SRAM Bus Cycle: Basic Bus Cycle (No Wait)
928
Figure 22.16 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait)
930
Insertion, Ans = 1, Anh = 1)
931
Figure 22.19 Burst ROM Bus Cycle (No Wait)
932
Figure 22.20 Burst ROM Bus Cycle (1St Data: One Internal Wait + One External Wait; 2Nd/3Rd/4Th Data: One Internal Wait)
933
Figure 22.21 Burst ROM Bus Cycle (No Wait, Address Setup/Hold Time Insertion, Ans = 1, Anh = 1)
934
Figure 22.22 Burst ROM Bus Cycle (One Internal Wait + One External Wait)
935
Figure 22.23 Synchronous DRAM Auto-Precharge Read Bus Cycle: Single (RCD[1:0] = 01, CAS Latency = 3, TPC[2:0] = 011)
937
Burst (RCD[1:0] = 01, CAS Latency = 3, TPC[2:0] = 011)
937
Figure 22.25 Synchronous DRAM Normal Read Bus Cycle: ACT + READ Commands, Burst (RCD[1:0] = 01, CAS Latency = 3)
938
CAS Latency = 3)
939
Figure 22.27 Synchronous DRAM Normal Read Bus Cycle: READ Command, Burst (CAS Latency = 3)
940
Figure 22.28 Synchronous DRAM Auto-Precharge Write Bus Cycle: Single (RCD[1:0] = 01, TPC[2:0] = 001, TRWL[2:0] = 010)
941
Figure 22.29 Synchronous DRAM Auto-Precharge Write Bus Cycle: Burst (RCD[1:0] = 01, TPC[2:0] = 001, TRWL[2:0] = 010)
942
Figure 22.30 Synchronous DRAM Normal Write Bus Cycle: ACT + WRITE Commands, Burst (RCD[1:0] = 01, TRWL[2:0] = 010)
943
Figure 22.31 Synchronous DRAM Normal Write Bus Cycle: PRE + ACT + WRITE Commands, Burst (RCD[1:0] = 01, TPC[2:0] = 001, TRWL[2:0] = 010)
944
Figure 22.32 Synchronous DRAM Normal Write Bus Cycle: WRITE Command, Burst (TRWL[2:0] = 010)
945
Figure 22.33 Synchronous DRAM Bus Cycle: Synchronous DRAM Precharge Command (TPC[2:0] = 001)
946
Figure 22.34 Synchronous DRAM Bus Cycle: Synchronous DRAM Auto-Refresh (TRAS = 1, TRC[2:0] = 001)
947
Figure 22.35 Synchronous DRAM Bus Cycle: Synchronous DRAM Self-Refresh (TRC[2:0] = 001)
948
Figure 22.36 (A) Synchronous DRAM Bus Cycle: Synchronous DRAM Mode Register Setting (PALL)
949
Figure 22.36 (B) Synchronous DRAM Bus Cycle: Synchronous DRAM Mode Register Setting (SET)
950
Figure 22.37 DRAM Bus Cycles (1) RCD[1:0] = 00, Anw[2:0] = 000, TPC[2:0] = 001 (2) RCD[1:0] = 01, Anw[2:0] = 001, TPC[2:0] = 010
951
Figure 22.38 DRAM Bus Cycle (EDO Mode, RCD[1:0] = 00, Anw[2:0] = 000, TPC[2:0] = 001)
952
Figure 22.39 DRAM Burst Bus Cycle (EDO Mode, RCD[1:0] = 00, Anw[2:0] = 000, TPC[2:0] = 001)
953
Figure 22.40 DRAM Burst Bus Cycle (EDO Mode, RCD[1:0] = 01, Anw[2:0] = 001, TPC[2:0] = 001)
954
TPC[2:0] = 001, 2-Cycle CAS Negate Pulse Width)
955
Figure 22.42 DRAM Burst Bus Cycle: RAS Down Mode State (EDO Mode, RCD[1:0] = 00, Anw[2:0] = 000)
956
Figure 22.43 DRAM Burst Bus Cycle: RAS Down Mode Continuation (EDO Mode, RCD[1:0] = 00, Anw[2:0] = 000)
957
Figure 22.44 DRAM Burst Bus Cycle (Fast Page Mode, RCD[1:0] = 00, Anw[2:0] = 000, TPC[2:0] = 001)
958
Figure 22.45 DRAM Burst Bus Cycle (Fast Page Mode, RCD[1:0] = 01, Anw[2:0] = 001, TPC[2:0] = 001)
959
Figure 22.46 DRAM Burst Bus Cycle (Fast Page Mode, RCD[1:0] = 01, Anw[2:0] = 001, TPC[2:0] = 001, 2-Cycle CAS Negate Pulse Width)
960
Figure 22.47 DRAM Burst Bus Cycle: RAS Down Mode State (Fast Page Mode, RCD[1:0] = 00, Anw[2:0] = 000)
961
(Fast Page Mode, RCD[1:0] = 00, Anw[2:0] = 000)
962
(Tras[2:0] = 000, Trc[2:0] = 001)
963
(Tras[2:0] = 001, Trc[2:0] = 001)
964
Figure 22.51 DRAM Bus Cycle: DRAM Self-Refresh (TRC[2:0] = 001)
965
Figure 22.52 PCMCIA Memory Bus Cycle (1) TED[2:0] = 000, TEH[2:0] = 000, No Wait (2) TED[2:0] = 001, TEH[2:0] = 001, One Internal Wait + One External Wait
966
Figure 22.53 PCMCIA I/O Bus Cycle (1) TED[2:0] = 000, TEH[2:0] = 000, No Wait (2) TED[2:0] = 001, TEH[2:0] = 001, One Internal Wait + One External Wait
967
Figure 22.54 PCMCIA I/O Bus Cycle (TED[2:0] = 001, TEH[2:0] = 001, One Internal Wait, Bus Sizing)
968
1St Data (One Internal Wait + One External Wait)
969
1St Data (One Internal Wait + One External Wait)
970
1St Data (One Internal Wait), 2Nd to 4Th Data (One Internal Wait + One External Wait)
971
Figure 22.58 MPX Bus Cycle: Burst Write (1) No Internal Wait (2) 1St Data (One Internal Wait), 2Nd to 4Th Data (No Internal Wait + External Wait Control)
972
Basic Read Cycle (One Internal Wait + One External Wait)
973
Figure 22.60 Memory Byte Control SRAM Bus Cycle: Basic Read Cycle (No Wait, Address Setup/Hold Time Insertion, Ans[0] = 1, Anh[1:0] =01)
974
Peripheral Module Signal Timing
974
Table 22.36 Peripheral Module Signal Timing (1)
976
Table 22.36 Peripheral Module Signal Timing (2)
978
Table 22.36 Peripheral Module Signal Timing (3)
980
Figure 22.61 TCLK Input Timing
980
Figure 22.62 RTC Oscillation Settling Time at Power-On
980
Figure 22.63 SCK Input Clock Timing
981
Figure 22.64 SCI I/O Synchronous Mode Clock Timing
981
Figure 22.65 I/O Port Input/Output Timing
981
Figure 22.66(A) DREQ/DRAK Timing
982
Figure 22.66(B) DBREQ/TR Input Timing and BAVL Output Timing
984
AC Characteristic Test Conditions
985
Delay Time Variation Due to Load Capacitance
987
Appendix A Address List
988
Table A.1 Address List
993
Appendix B Package Dimensions
997
Appendix C Mode Pin Settings
999
Appendix D CKIO2ENB Pin Configuration
1001
Appendix E Pin Functions
1001
Pin States
1001
Table E.1 Pin States in Reset, Power-Down State, and Bus-Released State
1004
Handling of Unused Pins
1005
Appendix F Synchronous DRAM Address Multiplexing Tables
1027
Appendix G Prefetching of Instructions and Its Side Effects
1029
Hd6417750Sbp200
1029
Table I.1 SH7750 Series Product Code Lineup
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Hitachi SH7750 series Hardware Manual (858 pages)
SuperH RISC engine
Brand:
Hitachi
| Category:
Engine
| Size: 4.47 MB
Table of Contents
6
Table of Contents
18
Overview
18
SH7750 Series Features
25
Block Diagram
26
Programming Model
26
Data Formats
27
Register Configuration
27
Privileged Mode and Banks
28
General Registers
32
Floating-Point Registers
34
Control Registers
35
System Registers
37
Memory-Mapped Registers
38
Data Format in Registers
38
Data Formats in Memory
39
Processor States
41
Processor Modes
42
Memory Management Unit (MMU)
42
Overview
42
Features
42
Role of the MMU
45
Register Configuration
45
Caution
46
Register Descriptions
49
Memory Space
49
Physical Memory Space
50
External Memory Space
53
Virtual Memory Space
54
On-Chip RAM Space
54
Address Translation
55
Single Virtual Memory Mode and Multiple Virtual Memory Mode
55
Address Space Identifier (ASID)
55
TLB Functions
55
Unified TLB (UTLB) Configuration
59
Instruction TLB (ITLB) Configuration
59
Address Translation Method
62
MMU Functions
62
MMU Hardware Management
62
MMU Software Management
62
MMU Instruction (LDTLB)
63
Hardware ITLB Miss Handling
64
Avoiding Synonym Problems
65
MMU Exceptions
65
Instruction TLB Multiple Hit Exception
66
Instruction TLB Miss Exception
67
Instruction TLB Protection Violation Exception
68
Data TLB Multiple Hit Exception
68
Data TLB Miss Exception
69
Data TLB Protection Violation Exception
70
Initial Page Write Exception
71
Memory-Mapped TLB Configuration
72
ITLB Address Array
73
ITLB Data Array 1
74
ITLB Data Array 2
74
UTLB Address Array
76
UTLB Data Array 1
77
UTLB Data Array 2
78
Caches
78
Overview
78
Features
79
Register Configuration
79
Register Descriptions
82
Operand Cache (OC)
82
Configuration
83
Read Operation
84
Write Operation
86
Write-Back Buffer
86
Write-Through Buffer
86
RAM Mode
87
OC Index Mode
88
Coherency Between Cache and External Memory
88
Prefetch Operation
89
Instruction Cache (IC)
89
Configuration
90
Read Operation
91
IC Index Mode
91
Memory-Mapped Cache Configuration
91
IC Address Array
92
IC Data Array
93
OC Address Array
95
OC Data Array
96
Store Queues
96
SQ Configuration
96
SQ Writes
96
Transfer to External Memory
98
SQ Protection
99
Exceptions
99
Overview
99
Features
99
Register Configuration
100
Register Descriptions
101
Exception Handling Functions
101
Exception Handling Flow
101
Exception Handling Vector Addresses
102
Exception Types and Priorities
104
Exception Flow
105
Exception Source Acceptance
107
Exception Requests and BL Bit
107
Return From Exception Handling
107
Description of Exceptions
108
Resets
113
General Exceptions
127
Interrupts
130
Priority Order with Multiple Exceptions
131
Usage Notes
132
Restrictions
133
Floating-Point Unit
133
Data Formats
133
Floating-Point Format
135
Non-Numbers (Nan)
136
Denormalized Numbers
133
Overview
137
Registers
137
Floating-Point Registers
139
Floating-Point Status/Control Register (FPSCR)
140
Floating-Point Communication Register (FPUL)
140
Rounding
141
Floating-Point Exceptions
142
Graphics Support Functions
142
Geometric Operation Instructions
144
Pair Single-Precision Data Transfer
145
Instruction Set
145
Execution Environment
147
Addressing Modes
151
Instruction Set
164
Pipelining
164
Pipelines
171
Parallel-Executability
175
Execution Cycles and Pipeline Stalling
191
Power-Down Modes
191
Overview
191
Types of Power-Down Modes
193
Register Configuration
193
Pin Configuration
193
Register Descriptions
193
Standby Control Register (STBCR)
196
Peripheral Module Pin High Impedance Control
196
Peripheral Module Pin Pull-Up Control
197
Standby Control Register 2 (STBCR2)
198
Deep Sleep Mode
198
Transition to Deep Sleep Mode
198
Exit From Deep Sleep Mode
198
Sleep Mode
198
Transition to Sleep Mode
198
Exit From Sleep Mode
199
Standby Mode
199
Transition to Standby Mode
200
Exit From Standby Mode
200
Clock Pause Function
201
Module Standby Function
201
Transition to Module Standby Function
201
Exit From Module Standby Function
202
STATUS Pin Change Timing
202
In Reset
203
In Exit From Standby Mode
205
In Exit From Sleep Mode
208
In Exit From Deep Sleep Mode
210
Overview
210
Features
210
Section 10 Clock Oscillation Circuits
212
Overview of CPG
212
Block Diagram of CPG
214
CPG Pin Configuration
214
CPG Register Configuration
215
Clock Operating Modes
216
CPG Register Description
216
Frequency Control Register (FRQCR)
219
Changing the Frequency
219
Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 Is Off)
219
Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 Is On)
220
Changing Bus Clock Division Ratio (When PLL Circuit 2 Is On)
220
Changing Bus Clock Division Ratio (When PLL Circuit 2 Is Off)
220
Changing CPU or Peripheral Module Clock Division Ratio
220
Output Clock Control
221
Overview of Watchdog Timer
221
Block Diagram
222
Register Configuration
222
WDT Register Descriptions
222
Watchdog Timer Counter (WTCNT)
223
Watchdog Timer Control/Status Register (WTCSR)
225
Notes On Register Access
225
Using the WDT
225
Standby Clearing Procedure
226
Frequency Changing Procedure
226
Using Watchdog Timer Mode
227
Using Interval Timer Mode
227
Notes On Board Design
229
Overview
229
Features
230
Block Diagram
231
Pin Configuration
231
Register Configuration
229
Section 11 Realtime Clock (RTC)
233
Register Descriptions
233
64 Hz Counter (R64CNT)
233
Second Counter (RSECCNT)
234
Minute Counter (RMINCNT)
234
Hour Counter (RHRCNT)
235
Day-Of-Week Counter (RWKCNT)
236
Day Counter (RDAYCNT)
236
Month Counter (RMONCNT)
237
Year Counter (RYRCNT)
238
Second Alarm Register (RSECAR)
238
Minute Alarm Register (RMINAR)
239
Hour Alarm Register (RHRAR)
239
Day-Of-Week Alarm Register (RWKAR)
240
Day Alarm Register (RDAYAR)
241
Month Alarm Register (RMONAR)
241
RTC Control Register 1 (RCR1)
243
RTC Control Register 2 (RCR2)
246
Operation
246
Time Setting Procedures
247
Time Reading Procedures
249
Alarm Function
250
Interrupts
250
Usage Notes
250
Register Initialization
250
Crystal Oscillator Circuit
252
Overview
252
Features
253
Block Diagram
253
Pin Configuration
254
Register Configuration
252
Section 12 Timer Unit (TMU)
255
Register Descriptions
255
Timer Output Control Register (TOCR)
256
Timer Start Register (TSTR)
257
Timer Constant Registers (TCOR)
257
Timer Counters (TCNT)
258
Timer Control Registers (TCR)
261
Input Capture Register (TCPR2)
262
Operation
262
Counter Operation
265
Input Capture Function
266
Interrupts
267
Usage Notes
267
Register Writes
267
TCNT Register Reads
267
Resetting the RTC Frequency Divider
267
External Clock Frequency
268
Overview
268
Features
270
Block Diagram
271
Pin Configuration
275
Register Configuration
276
Overview of Areas
279
PCMCIA Support
268
Section 13 Bus State Controller (BSC)
283
Register Descriptions
283
Bus Control Register 1 (BCR1)
291
Bus Control Register 2 (BCR2)
292
Wait Control Register 1 (WCR1)
294
Wait Control Register 2 (WCR2)
302
Wait Control Register 3 (WCR3)
303
Memory Control Register (MCR)
310
PCMCIA Control Register (PCR)
313
Synchronous DRAM Mode Register (SDMR)
315
Refresh Timer Control/Status Register (RTSCR)
317
Refresh Timer Counter (RTCNT)
317
Refresh Time Constant Register (RTCOR)
318
Refresh Count Register (RFCR)
319
13.2.13 Notes On Accessing Refresh Control Registers
Hitachi SH7750 series Programming Manual (412 pages)
High-Performance RISC Engine SuperH (SH) 32-Bit RISC MCU/MPU Series
Brand:
Hitachi
| Category:
Engine
| Size: 1.68 MB
Table of Contents
7
Table of Contents
15
Section 1 Overview
15
SH7750 Features
22
Block Diagram
23
Section 2 Programming Model
23
Data Formats
24
Register Configuration
24
Privileged Mode and Banks
27
General Registers
29
Floating-Point Registers
31
Control Registers
32
System Registers
34
Memory-Mapped Registers
35
Data Format in Registers
35
Data Formats in Memory
36
Processor States
37
Processor Modes
39
Section 3 Memory Management Unit (MMU)
39
Overview
39
Features
39
Role of the MMU
42
Register Configuration
42
Caution
43
Register Descriptions
46
Memory Space
46
Physical Memory Space
49
External Memory Space
50
Virtual Memory Space
51
On-Chip RAM Space
51
Address Translation
52
Single Virtual Memory Mode and Multiple Virtual Memory Mode
52
Address Space Identifier (ASID)
52
TLB Functions
52
Unified TLB (UTLB) Configuration
56
Instruction TLB (ITLB) Configuration
56
Address Translation Method
59
MMU Functions
59
MMU Hardware Management
59
MMU Software Management
59
MMU Instruction (LDTLB)
60
Hardware ITLB Miss Handling
61
Avoiding Synonym Problems
62
MMU Exceptions
62
Instruction TLB Multiple Hit Exception
63
Instruction TLB Miss Exception
64
Instruction TLB Protection Violation Exception
65
Data TLB Multiple Hit Exception
65
Data TLB Miss Exception
66
Data TLB Protection Violation Exception
67
Initial Page Write Exception
68
Memory-Mapped TLB Configuration
69
ITLB Address Array
70
ITLB Data Array 1
71
ITLB Data Array 2
71
UTLB Address Array
73
UTLB Data Array 1
74
UTLB Data Array 2
75
Section 4 Caches
75
Overview
75
Features
76
Register Configuration
76
Register Descriptions
79
Operand Cache (OC)
79
Configuration
80
Read Operation
81
Write Operation
83
Write-Back Buffer
83
Write-Through Buffer
83
RAM Mode
84
OC Index Mode
85
Coherency Between Cache and External Memory
85
Prefetch Operation
86
Instruction Cache (IC)
86
Configuration
87
Read Operation
88
IC Index Mode
88
Memory-Mapped Cache Configuration
88
IC Address Array
89
IC Data Array
90
OC Address Array
92
OC Data Array
93
Store Queues
93
SQ Configuration
93
SQ Writes
93
Transfer to External Memory
95
SQ Protection
97
Section 5 Exceptions
97
Overview
97
Features
97
Register Configuration
98
Register Descriptions
99
Exception Handling Functions
99
Exception Handling Flow
99
Exception Handling Vector Addresses
100
Exception Types and Priorities
102
Exception Flow
103
Exception Source Acceptance
105
Exception Requests and BL Bit
105
Return From Exception Handling
106
Description of Exceptions
106
Resets
111
General Exceptions
125
Interrupts
128
Priority Order with Multiple Exceptions
129
Usage Notes
129
Restrictions
131
Section 6 Floating-Point Unit
131
Overview
131
Data Formats
131
Floating-Point Format
133
Non-Numbers (Nan)
134
Denormalized Numbers
135
Registers
135
Floating-Point Registers
137
Floating-Point Status/Control Register (FPSCR)
138
Floating-Point Communication Register (FPUL)
138
Rounding
139
Floating-Point Exceptions
140
Graphics Support Functions
140
Geometric Operation Instructions
142
Pair Single-Precision Data Transfer
143
Section 7 Instruction Set
143
Execution Environment
145
Addressing Modes
149
Instruction Set
163
Section 8 Pipelining
163
Pipelines
170
Parallel-Executability
174
Execution Cycles and Pipeline Stalling
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