Buffer Registers (Bra, Brb) - Hitachi H8/3035 Series Hardware Manual

the general register. The corresponding IMFA or IMFB flag in TSR is set to 1 at the same time.
The valid edge or edges of the input capture signal are selected in TIOR.
TIOR settings are ignored in PWM mode, complementary PWM mode, and reset-synchronized
PWM mode.
General registers are linked to the CPU by an internal 16-bit bus and can be written or read by
either word access or byte access.
General registers are initialized to the output compare function (with no output signal) by a reset
and in standby mode. The initial value is H'FFFF.

8.2.9 Buffer Registers (BRA, BRB)

The buffer registers are 16-bit registers. The ITU has four buffer registers, two each in channels
3 and 4.
Channel Abbreviation Function
3 BRA3, BRB3
4 BRA4, BRB4
15 14
Bit
Initial value 1 1
Read/Write R/W R/W
A buffer register is a 16-bit readable/writable register that is used when buffering is selected.
Buffering can be selected independently by bits BFB4, BFA4, BFB3, and BFA3 in TFCR.
The buffer register and general register operate as a pair. When the general register functions as
an output compare register, the buffer register functions as an output compare buffer register.
When the general register functions as an input capture register, the buffer register functions as
an input capture buffer register.
186
Used for buffering
•
When the corresponding GRA or GRB functions as an output
compare register, BRA or BRB can function as an output
compare buffer register: the BRA or BRB value is automatically
transferred to GRA or GRB at compare match
•
When the corresponding GRA or GRB functions as an input
capture register, BRA or BRB can function as an input capture
buffer register: the GRA or GRB value is automatically
transferred to BRA or BRB at input capture
13 12 11 10 9
1 1 1 1 1
R/W R/W R/W R/W R/W
8 7 6 5 4
1 1 1 1 1
R/W R/W R/W R/W R/W
3 2 1 0
1 1 1 1
R/W R/W R/W R/W