Break On Instruction Fetch Cycle; Break On Data Access Cycle - Hitachi SH7095 Hardware User Manual

6.3.2

Break on Instruction Fetch Cycle

1. When CPU/instruction fetch/read/word is set in the break bus cycle registers (BBRA/BBRB),
the break condition becomes the CPU's instruction fetch cycle. Whether it then breaks before
or after the execution of the instruction can then be selected with the PCBA/PCBB bits of the
break control register (BRCR) for the appropriate channel.
2. The instruction fetch cycle always fetches 32 bits (two instructions). Only one bus cycle
occurs, but breaks can be placed on each instruction individually by setting the respective
addresses in the break address registers (BARA, BARB).
3. An instruction set for a break before execution breaks when it is confirmed that the instruction
has been fetched and will be executed. This means this feature cannot be used on instructions
fetched by overrun (instructions fetched at a branch or during an interrupt transition, but not
to be executed). When this kind of break is set for the delay slot of a delay branch instruction
or an instruction following an interrupt-disabled instruction, such as LDC, the interrupt is
generated prior to execution of the instruction that then first accepts the interrupt.
4. When the condition stipulates after execution, the instruction set with the break condition is
executed and then the interrupt is generated prior to the execution of the next instruction. As
with pre-execution breaks, this cannot be used with overrun fetch instructions. When this kind
of break is set for a delay branch instruction or an interrupt-disabled instruction, such as LDC,
the interrupt is generated at the instruction that then first accepts the interrupt.
5. When an instruction fetch cycle is set for channel B, break data register B (BDRB) is ignored.
There is thus no need to set break data for the break of the instruction fetch cycle.
6.3.3

Break on Data Access Cycle

1. The memory cycles in which CPU data access breaks occur are: memory cycles from
instructions, and stacking and vector reads during exception processing. These breaks cannot
be used in dummy cycles for single reads of synchronous DRAM.
2. The relationship between the data access cycle address and the comparison condition for
operand size are shown in table 6.3. This means that when address H'00001003 is set without
specifying the size condition, for example, the bus cycle in which the break condition is
satisfied is as follows (where other conditions are met):
Longword access at H'00001000
Word access at H'00001002
Byte access at H'00001003
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