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6.1.3 Input/Output Pins
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Table 6-1 summarizes the bus controller's input/output pins.
Table 6-1 Bus Controller Pins
Name
Chip select 0 to 7
Address strobe
Read
High write
Low write
Wait
Bus request
Bus acknowledge
6.1.4 Register Configuration
Table 6-2 summarizes the bus controller's registers.
Table 6-2 Bus Controller Registers
Address*
Name
H'FFEC
Bus width control register
H'FFED
Access state control register
H'FFEE
Wait control register
H'FFEF
Wait state controller enable
register
H'FFF3
Bus release control register
H'FF5F
Chip select control register
Note: * Lower 16 bits of the address.
Abbreviation
I/O
CS
to CS
Output
0
7
AS
Output
RD
Output
HWR
Output
LWR
Output
WAIT
Input
BREQ
Input
BACK
Output
Abbrevi-
ation
ABWCR
ASTCR
WCR
WCER
BRCR
CSCR
Function
Strobe signals selecting areas 0 to 7
Strobe signal indicating valid address output on the
address bus
Strobe signal indicating reading from the external
address space
Strobe signal indicating writing to the external
address space, with valid data on the upper data
bus (D
to D
)
15
8
Strobe signal indicating writing to the external
address space, with valid data on the lower data
bus (D
to D
)
7
0
Wait request signal for access to external three-
state-access areas
Request signal for releasing the bus to an external
device
Acknowledge signal indicating the bus is released
to an external device
R/W
Modes 1, 3, 5, 6
R/W
H'FF
R/W
H'FF
R/W
H'F3
R/W
H'FF
R/W
H'FE
R/W
H'0F
113
Initial Value
Modes 2, 4, 7
H'00
H'FF
H'F3
H'FF
H'FE
H'0F
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