Samsung S5PC100 User Manual page 1168

S5PC100 USER'S MANUAL (REV1.0)
8.36 Input DMA Cb Offset Register (CIICBOFFn)
CIICBOFF0, R/W, Address = 0xEE20_0178
CIICBOFF1, R/W, Address = 0xEE30_0178
CIICBOFF2, R/W, Address = 0xEE40_0178
CIICBOFFn Bit
Reserved [31]
ICBOFF_V [30:16]
Reserved [15]
ICBOFF_H [14:0]
8.37 Input DMA Cr Offset Register (CIICROFFn)
CIICRFF0, R/W, Address = 0xEE20_017C
CIICRFF1, R/W, Address = 0xEE30_017C
CIICRFF2, R/W, Address = 0xEE40_017C
CIICROFFn Bit
Reserved [31]
ICROFF_V [30:16]
Reserved [15]
ICROFF_H [14:0]
Reserved
Input DMA vertical offset for Cb component
Input format : YCbCr 3 plane → Cb height offset
Input format : YCbCr 2 plane → CbCr height offset
Reserved
Input DMA horizontal offset for Cb component
Input format : YCbCr 3 plane → Cb width offset
Input format : YCbCr 2 plane → CbCr width offset
Reserved
Input DMA vertical offset for Cr component
Input format : YCbCr 3 plane → Cr height offset
Reserved
Input DMA horizontal offset for Cr component
Input format : YCbCr 3 plane → Cr width offset
Description
Description
CAMERA INTERFACE
Reset
M L
Value
0
X X
0
O X
0
X X
0
O X
Reset
M L
Value
0
X X
0
O X
0
X X
0
O X
9.3-53